Hi Peter,
while this may break for your board, it fundamentally introduces the
possibility to speculate out of the RAM area on speculation happy
processors. Are you calling into SAMA5D3 ROM code somewhere? If so an
exception can be added similar to the handling for the HAB code
(arch/arm/cpu/mmu_early.c):
if (IS_ENABLED(CONFIG_HABV4) && IS_ENABLED(CONFIG_ARCH_IMX6))
map_region(0x0, SZ_1M, PMD_SECT_DEF_CACHED);
which allows calls into the NXP boot ROM to retrieve the HAB status.
Regards,
Rouven
On Sat, 2021-09-18 at 00:40 +0200, Peter Rosin wrote:
> This reverts commit 3e4a0405455f66fbae0a98dc1faee5c7c39f17a2.
>
> The patch breaks my SAMA5D3 board.
>
> Signed-off-by: Peter Rosin <peda@xxxxxxxxxx>
> ---
> arch/arm/cpu/mmu-early.c | 7 +------
> arch/arm/cpu/mmu.c | 7 +------
> arch/arm/cpu/mmu.h | 1 -
> 3 files changed, 2 insertions(+), 13 deletions(-)
>
> diff --git a/arch/arm/cpu/mmu-early.c b/arch/arm/cpu/mmu-early.c
> index b985aa455fe8..92b1161985fb 100644
> --- a/arch/arm/cpu/mmu-early.c
> +++ b/arch/arm/cpu/mmu-early.c
> @@ -29,12 +29,7 @@ void mmu_early_enable(unsigned long membase, unsigned long memsize,
> arm_set_cache_functions();
>
> set_ttbr(ttb);
> -
> - /* For the XN bit to take effect, we can't be using DOMAIN_MANAGER. */
> - if (cpu_architecture() >= CPU_ARCH_ARMv7)
> - set_domain(DOMAIN_CLIENT);
> - else
> - set_domain(DOMAIN_MANAGER);
> + set_domain(DOMAIN_MANAGER);
>
> /*
> * This marks the whole address space as uncachable as well as
> diff --git a/arch/arm/cpu/mmu.c b/arch/arm/cpu/mmu.c
> index 6388e1bf14f6..d0aff9e7f027 100644
> --- a/arch/arm/cpu/mmu.c
> +++ b/arch/arm/cpu/mmu.c
> @@ -452,12 +452,7 @@ void __mmu_init(bool mmu_on)
> ttb = xmemalign(ARM_TTB_SIZE, ARM_TTB_SIZE);
>
> set_ttbr(ttb);
> -
> - /* For the XN bit to take effect, we can't be using DOMAIN_MANAGER. */
> - if (cpu_architecture() >= CPU_ARCH_ARMv7)
> - set_domain(DOMAIN_CLIENT);
> - else
> - set_domain(DOMAIN_MANAGER);
> + set_domain(DOMAIN_MANAGER);
>
> create_flat_mapping(ttb);
> __mmu_cache_flush();
> diff --git a/arch/arm/cpu/mmu.h b/arch/arm/cpu/mmu.h
> index c85e0ea05033..e8b72662cddc 100644
> --- a/arch/arm/cpu/mmu.h
> +++ b/arch/arm/cpu/mmu.h
> @@ -36,7 +36,6 @@ static inline void set_ttbr(void *ttb)
> asm volatile ("mcr p15,0,%0,c2,c0,0" : : "r"(ttb) /*:*/);
> }
>
> -#define DOMAIN_CLIENT 1
> #define DOMAIN_MANAGER 3
>
> static inline unsigned long get_domain(void)
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