Set the NAND timings and enable the IFC NAND driver.
Signed-off-by: Renaud Barbier <renaud.barbier@xxxxxxxxx>
---
arch/arm/configs/layerscape_defconfig | 11 +++++++
arch/arm/mach-layerscape/Makefile | 1 +
arch/arm/mach-layerscape/nand.c | 44 +++++++++++++++++++++++++++
3 files changed, 56 insertions(+)
create mode 100644 arch/arm/mach-layerscape/nand.c
diff --git a/arch/arm/configs/layerscape_defconfig b/arch/arm/configs/layerscape_defconfig
index 394cd95c98..fb8e885353 100644
--- a/arch/arm/configs/layerscape_defconfig
+++ b/arch/arm/configs/layerscape_defconfig
@@ -34,6 +34,10 @@ CONFIG_CMD_GO=y
CONFIG_CMD_RESET=y
CONFIG_CMD_UIMAGE=y
CONFIG_CMD_PARTITION=y
+CONFIG_CMD_MOUNT=y
+CONFIG_CMD_UBI=y
+CONFIG_CMD_UBIFORMAT=y
+CONFIG_CMD_UMOUNT=y
CONFIG_CMD_EXPORT=y
CONFIG_CMD_LOADENV=y
CONFIG_CMD_PRINTENV=y
@@ -69,6 +73,7 @@ CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_LED=y
CONFIG_CMD_SPI=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_LED_TRIGGER=y
CONFIG_CMD_WD=y
CONFIG_CMD_BAREBOX_UPDATE=y
@@ -85,6 +90,10 @@ CONFIG_DP83867_PHY=y
CONFIG_REALTEK_PHY=y
CONFIG_NET_DSA_MV88E6XXX=y
CONFIG_DRIVER_SPI_FSL_QUADSPI=y
+CONFIG_NAND=y
+CONFIG_NAND_FSL_IFC=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_BEB_LIMIT=20
CONFIG_I2C=y
CONFIG_I2C_IMX=y
CONFIG_I2C_MUX=y
@@ -112,5 +121,7 @@ CONFIG_FS_NFS=y
CONFIG_FS_FAT=y
CONFIG_FS_FAT_WRITE=y
CONFIG_FS_FAT_LFN=y
+CONFIG_FS_UBIFS=y
+CONFIG_FS_UBIFS_COMPRESSION_LZO=y
CONFIG_ZLIB=y
CONFIG_LZO_DECOMPRESS=y
diff --git a/arch/arm/mach-layerscape/Makefile b/arch/arm/mach-layerscape/Makefile
index 854a327c91..99da7b2af0 100644
--- a/arch/arm/mach-layerscape/Makefile
+++ b/arch/arm/mach-layerscape/Makefile
@@ -6,3 +6,4 @@ obj-pbl-y += boot.o
pbl-y += xload-qspi.o xload.o
obj-$(CONFIG_ARCH_LAYERSCAPE_PPA) += ppa.o ppa-entry.o
obj-$(CONFIG_BOOTM) += pblimage.o
+obj-$(CONFIG_NAND_FSL_IFC) += nand.o
diff --git a/arch/arm/mach-layerscape/nand.c b/arch/arm/mach-layerscape/nand.c
new file mode 100644
index 0000000000..b36c6b3c46
--- /dev/null
+++ b/arch/arm/mach-layerscape/nand.c
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <common.h>
+#include <init.h>
+#include <of_address.h>
+#include <linux/fsl_ifc.h>
+
+static int rdb_nand_init(void)
+{
+ struct device_node *np;
+ void __iomem *ifc;
+
+ if (!of_machine_is_compatible("fsl,ls1046a-rdb"))
+ return 0;
+
+ np = of_find_compatible_node(NULL, NULL, "fsl,ifc");
+ if (!np)
+ return -EINVAL;
+
+ ifc = of_iomap(np, 0);
+ if (!ifc)
+ return -EINVAL;
+
+ set_ifc_cspr(ifc, IFC_CS0, CSPR_PHYS_ADDR(0x7e800000) |
+ CSPR_PORT_SIZE_8 | CSPR_MSEL_NAND | CSPR_V);
+ set_ifc_csor(ifc, IFC_CS0, CSOR_NAND_ECC_ENC_EN | CSOR_NAND_ECC_DEC_EN |
+ CSOR_NAND_ECC_MODE_8 |
+ CSOR_NAND_RAL_3 | CSOR_NAND_PGS_4K |
+ CSOR_NAND_SPRZ_224 | CSOR_NAND_PB(64) |
+ CSOR_NAND_TRHZ_20);
+ set_ifc_amask(ifc, IFC_CS0, IFC_AMASK(64*1024));
+ set_ifc_ftim(ifc, IFC_CS0, IFC_FTIM0, FTIM0_NAND_TCCST(0x07) |
+ FTIM0_NAND_TWP(0x18) | FTIM0_NAND_TWCHT(0x07) |
+ FTIM0_NAND_TWH(0x0a));
+ set_ifc_ftim(ifc, IFC_CS0, IFC_FTIM1, FTIM1_NAND_TADLE(0x32) |
+ FTIM1_NAND_TWBE(0x39) | FTIM1_NAND_TRR(0x0e)|
+ FTIM1_NAND_TRP(0x18));
+ set_ifc_ftim(ifc, IFC_CS0, IFC_FTIM2, FTIM2_NAND_TRAD(0xf) |
+ FTIM2_NAND_TREH(0xa) | FTIM2_NAND_TWHRE(0x1e));
+ set_ifc_ftim(ifc, IFC_CS0, IFC_FTIM3, 0);
+
+ return 0;
+}
+postcore_initcall(rdb_nand_init);
--
2.27.0
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