On 24.06.21 12:23, Michael Tretter wrote:
> The reset reason is available in the APB register set on the ZynqMP.
> Read the reset reason and set the reset source accordingly.
>
> There might be multiple bits set in the APB register. Use the MSB for
> determining the actual reset source.
APB is usually the AMBA Advanced Peripheral Bus. Perhaps CRL is the
actual name of the register and APB just tells that it's mapped there?
>
> Signed-off-by: Michael Tretter <m.tretter@xxxxxxxxxxxxxx>
> ---
> arch/arm/mach-zynqmp/Makefile | 1 +
> arch/arm/mach-zynqmp/include/mach/zynqmp.h | 6 ++
> arch/arm/mach-zynqmp/zynqmp.c | 74 ++++++++++++++++++++++
> 3 files changed, 81 insertions(+)
> create mode 100644 arch/arm/mach-zynqmp/include/mach/zynqmp.h
> create mode 100644 arch/arm/mach-zynqmp/zynqmp.c
>
> diff --git a/arch/arm/mach-zynqmp/Makefile b/arch/arm/mach-zynqmp/Makefile
> index 021efc94afaf..14b8a4e46b87 100644
> --- a/arch/arm/mach-zynqmp/Makefile
> +++ b/arch/arm/mach-zynqmp/Makefile
> @@ -1,2 +1,3 @@
> # SPDX-License-Identifier: GPL-2.0-or-later
> obj-y += firmware-zynqmp.o
> +obj-y += zynqmp.o
> diff --git a/arch/arm/mach-zynqmp/include/mach/zynqmp.h b/arch/arm/mach-zynqmp/include/mach/zynqmp.h
> new file mode 100644
> index 000000000000..f6c05f35a470
> --- /dev/null
> +++ b/arch/arm/mach-zynqmp/include/mach/zynqmp.h
Nitpick: revision.h sounds more self-describing.
> @@ -0,0 +1,6 @@
> +#ifndef __MACH_ZYNQMP_H
> +#define __MACH_ZYNQMP_H
> +
> +int zynqmp_soc_revision(void);
> +
> +#endif /* __MACH_ZYNQMP_H */
> diff --git a/arch/arm/mach-zynqmp/zynqmp.c b/arch/arm/mach-zynqmp/zynqmp.c
> new file mode 100644
> index 000000000000..2b3bd8406ce9
> --- /dev/null
> +++ b/arch/arm/mach-zynqmp/zynqmp.c
> @@ -0,0 +1,74 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (C) 2020 Michael Tretter <m.tretter@xxxxxxxxxxxxxx>
> + */
> +
> +#include <common.h>
> +#include <init.h>
> +#include <linux/types.h>
> +#include <reset_source.h>
> +
> +#include <mach/zynqmp.h>
> +
> +#define ZYNQMP_CRL_APB_BASE 0xff5e0000
> +#define ZYNQMP_CRL_APB_RESET_REASON (ZYNQMP_CRL_APB_BASE + 0x220)
> +
> +/* External POR: The PS_POR_B reset signal pin was asserted. */
> +#define ZYNQMP_CRL_APB_RESET_REASON_EXTERNAL BIT(0)
> +/* Internal POR: A system error triggered a POR reset. */
> +#define ZYNQMP_CRL_APB_RESET_REASON_INTERNAL BIT(1)
> +/* Internal system reset; A system error triggered a system reset. */
> +#define ZYNQMP_CRL_APB_RESET_REASON_PMU BIT(2)
> +/* PS-only reset: Write to PMU_GLOBAL.GLOBAL_RESET [PS_ONLY_RST]. */
> +#define ZYNQMP_CRL_APB_RESET_REASON_PSONLY BIT(3)
> +/* External system reset: The PS_SRST_B reset signal pin was asserted. */
> +#define ZYNQMP_CRL_APB_RESET_REASON_SRST BIT(4)
> +/* Software system reset: Write to RESET_CTRL [soft_reset]. */
> +#define ZYNQMP_CRL_APB_RESET_REASON_SOFT BIT(5)
> +/* Software debugger reset: Write to BLOCKONLY_RST [debug_only]. */
> +#define ZYNQMP_CRL_APB_RESET_REASON_DEBUG_SYS BIT(6)
> +
> +struct zynqmp_reset_reason {
> + u32 mask;
> + enum reset_src_type type;
> +};
> +
> +static const struct zynqmp_reset_reason reset_reasons[] = {
> + { ZYNQMP_CRL_APB_RESET_REASON_DEBUG_SYS, RESET_UKWN },
RESET_JTAG?
> + { ZYNQMP_CRL_APB_RESET_REASON_SOFT, RESET_RST },
> + { ZYNQMP_CRL_APB_RESET_REASON_SRST, RESET_POR },
> + { ZYNQMP_CRL_APB_RESET_REASON_PSONLY, RESET_POR },
> + { ZYNQMP_CRL_APB_RESET_REASON_PMU, RESET_POR },
> + { ZYNQMP_CRL_APB_RESET_REASON_INTERNAL, RESET_POR },
> + { ZYNQMP_CRL_APB_RESET_REASON_EXTERNAL, RESET_POR },
RESET_EXT?
> + { /* sentinel */ }
> +};
> +
> +static enum reset_src_type zynqmp_get_reset_src(void)
> +{
> + enum reset_src_type type = RESET_UKWN;
> + unsigned int i;
> + u32 val;
> +
> + val = readl(ZYNQMP_CRL_APB_RESET_REASON);
> +
> + for (i = 0; i < ARRAY_SIZE(reset_reasons); i++) {
> + if (val & reset_reasons[i].mask) {
> + type = reset_reasons[i].type;
> + break;
> + }
> + }
> +
> + pr_info("ZynqMP reset reason %s (ZYNQMP_CRL_APB_RESET_REASON: 0x%08x)\n",
> + reset_source_to_string(type), val);
> +
> + return type;
> +}
> +
> +static int zynqmp_init(void)
> +{
> + reset_source_set(zynqmp_get_reset_src());
> +
> + return 0;
> +}
> +postcore_initcall(zynqmp_init);
>
--
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