On 31.05.21 09:40, Ahmad Fatoum wrote: > Hello Antony, > > On 31.05.21 09:38, Ahmad Fatoum wrote: >> SiFive SoCs have separate I-Caches that require self-modifying code >> like barebox' relocation and PBL extraction code to do cache >> maintenance. Implement sync_caches_for_execution and use it where >> appropriate. >> >> Signed-off-by: Ahmad Fatoum <a.fatoum@xxxxxxxxxxxxxx> >> --- >> +void sync_caches_for_execution(void) >> +{ >> + if (IS_ENABLED(CONFIG_HAS_CACHE)) >> + asm volatile ("fence.i" ::: "memory"); > > If Erizo on FPGA chokes on this, we can have it pass > along a feature flag from PBL that says it doesn't > need cache maintenance. Please advise. I now skip over fence.i in the exception handler, so it should be ok to call this, even on systems that lack Zifencei ISA extension. I'll send out a v2 soon. -- Pengutronix e.K. | | Steuerwalder Str. 21 | http://www.pengutronix.de/ | 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | _______________________________________________ barebox mailing list barebox@xxxxxxxxxxxxxxxxxxx http://lists.infradead.org/mailman/listinfo/barebox