SiFive SoCs have separate I-Caches that require self-modifying code
like barebox' relocation and PBL extraction code to do cache
maintenance. Implement sync_caches_for_execution and use it where
appropriate.
Signed-off-by: Ahmad Fatoum <a.fatoum@xxxxxxxxxxxxxx>
---
arch/riscv/Kconfig.socs | 2 ++
arch/riscv/boot/uncompress.c | 2 ++
arch/riscv/cpu/core.c | 7 +++++++
arch/riscv/include/asm/barebox-riscv.h | 2 ++
arch/riscv/lib/reloc.c | 8 ++++++++
arch/riscv/lib/setupc.S | 2 ++
6 files changed, 23 insertions(+)
diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
index 9c82a36fe4bd..d2970ba1d67f 100644
--- a/arch/riscv/Kconfig.socs
+++ b/arch/riscv/Kconfig.socs
@@ -18,6 +18,7 @@ config SOC_VIRT
select RISCV_S_MODE
select BOARD_RISCV_GENERIC_DT
select CLINT_TIMER
+ select HAS_CACHE
help
Generates an image tht can be be booted by QEMU. The image is called
barebox-dt-2nd.img
@@ -30,6 +31,7 @@ config SOC_SIFIVE
select RISCV_TIMER
select HAS_MACB
select HAS_ASM_DEBUG_LL
+ select HAS_CACHE
help
This enables support for SiFive SoC platform hardware.
diff --git a/arch/riscv/boot/uncompress.c b/arch/riscv/boot/uncompress.c
index 35a91e8cb62a..9f1d25efb59b 100644
--- a/arch/riscv/boot/uncompress.c
+++ b/arch/riscv/boot/uncompress.c
@@ -63,6 +63,8 @@ void __noreturn barebox_pbl_start(unsigned long membase, unsigned long memsize,
pbl_barebox_uncompress((void*)barebox_base, pg_start, pg_len);
+ sync_caches_for_execution();
+
barebox = (void *)barebox_base;
pr_debug("jumping to uncompressed image at 0x%p. dtb=0x%p\n", barebox, fdt);
diff --git a/arch/riscv/cpu/core.c b/arch/riscv/cpu/core.c
index 62eb0ca87164..b4727fe7449b 100644
--- a/arch/riscv/cpu/core.c
+++ b/arch/riscv/cpu/core.c
@@ -18,6 +18,7 @@
#include <linux/clk.h>
#include <linux/err.h>
#include <memory.h>
+#include <asm/barebox-riscv.h>
#include <asm-generic/memory_layout.h>
#include <globalvar.h>
#include <magicvar.h>
@@ -91,3 +92,9 @@ static struct driver_d riscv_driver = {
.of_compatible = riscv_dt_ids,
};
postcore_platform_driver(riscv_driver);
+
+static void arch_shutdown(void)
+{
+ sync_caches_for_execution();
+}
+archshutdown_exitcall(arch_shutdown);
diff --git a/arch/riscv/include/asm/barebox-riscv.h b/arch/riscv/include/asm/barebox-riscv.h
index bbe6cd040642..abb320242769 100644
--- a/arch/riscv/include/asm/barebox-riscv.h
+++ b/arch/riscv/include/asm/barebox-riscv.h
@@ -27,6 +27,8 @@ void setup_c(void);
void relocate_to_current_adr(void);
void relocate_to_adr(unsigned long target);
+void sync_caches_for_execution(void);
+
void __noreturn __naked barebox_riscv_entry(unsigned long membase, unsigned long memsize,
void *boarddata, unsigned int flags);
diff --git a/arch/riscv/lib/reloc.c b/arch/riscv/lib/reloc.c
index 2fc8818cd698..165190775361 100644
--- a/arch/riscv/lib/reloc.c
+++ b/arch/riscv/lib/reloc.c
@@ -24,6 +24,12 @@
#define RISC_R_TYPE(x) ((x) & 0xFF)
+void sync_caches_for_execution(void)
+{
+ if (IS_ENABLED(CONFIG_HAS_CACHE))
+ asm volatile ("fence.i" ::: "memory");
+}
+
void relocate_to_current_adr(void)
{
unsigned long offset;
@@ -63,4 +69,6 @@ void relocate_to_current_adr(void)
panic("");
}
}
+
+ sync_caches_for_execution();
}
diff --git a/arch/riscv/lib/setupc.S b/arch/riscv/lib/setupc.S
index 5fdd81c2c3ec..d225186c79fd 100644
--- a/arch/riscv/lib/setupc.S
+++ b/arch/riscv/lib/setupc.S
@@ -46,6 +46,8 @@ ENTRY(relocate_to_adr)
jal __memcpy
+ jal sync_caches_for_execution
+
REG_L a0, (SZREG * 1)(sp)
jr a0 /* jump to relocated address */
copied:
--
2.29.2
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