[PATCH 04/12] PCI: dwc: Make use of BIT() in constant definitions

[Sascha Hauer <s.hauer@xxxxxxxxxxxxxx>]

Port of Linux commit 0e11faa48b07a063289d65363015a3d51ca4c337

    Avoid using explicit left shifts and convert various definitions to
    use BIT() instead. No functional change intended.

    Signed-off-by: Andrey Smirnov <andrew.smirnov@xxxxxxxxx>
    [lorenzo.pieralisi@xxxxxxx: fixed PORT_LOGIC_SPEED_CHANGE redefinition]
    Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@xxxxxxx>
    Acked-by: Gustavo Pimentel <gustavo.pimentel@xxxxxxxxxxxx>
    Cc: Lorenzo Pieralisi <lorenzo.pieralisi@xxxxxxx>
    Cc: Bjorn Helgaas <bhelgaas@xxxxxxxxxx>
    Cc: Fabio Estevam <fabio.estevam@xxxxxxx>
    Cc: Chris Healy <cphealy@xxxxxxxxx>
    Cc: Lucas Stach <l.stach@xxxxxxxxxxxxxx>
    Cc: Leonard Crestez <leonard.crestez@xxxxxxx>
    Cc: "A.s. Dong" <aisheng.dong@xxxxxxx>
    Cc: Richard Zhu <hongxing.zhu@xxxxxxx>
    Cc: linux-imx@xxxxxxx
    Cc: linux-arm-kernel@xxxxxxxxxxxxxxxxxxx
    Cc: linux-kernel@xxxxxxxxxxxxxxx
    Cc: linux-pci@xxxxxxxxxxxxxxx

Signed-off-by: Sascha Hauer <s.hauer@xxxxxxxxxxxxxx>
---
 drivers/pci/pci-imx6.c        |  1 -
 drivers/pci/pcie-designware.h | 12 ++++++------
 2 files changed, 6 insertions(+), 7 deletions(-)

diff --git a/drivers/pci/pci-imx6.c b/drivers/pci/pci-imx6.c
index 85307bad3e..6cbae1e223 100644
--- a/drivers/pci/pci-imx6.c
+++ b/drivers/pci/pci-imx6.c
@@ -112,7 +112,6 @@ struct imx6_pcie {
 #define PCIE_PHY_STAT_ACK_LOC 16
 
 #define PCIE_LINK_WIDTH_SPEED_CONTROL	0x80C
-#define PORT_LOGIC_SPEED_CHANGE		(0x1 << 17)
 
 /* PHY registers (not memory-mapped) */
 #define PCIE_PHY_RX_ASIC_OUT 0x100D
diff --git a/drivers/pci/pcie-designware.h b/drivers/pci/pcie-designware.h
index 1659d8f60b..30bdc0ed6e 100644
--- a/drivers/pci/pcie-designware.h
+++ b/drivers/pci/pcie-designware.h
@@ -27,7 +27,7 @@
 #define PORT_LINK_MODE_4_LANES		(0x7 << 16)
 
 #define PCIE_LINK_WIDTH_SPEED_CONTROL	0x80C
-#define PORT_LOGIC_SPEED_CHANGE		(0x1 << 17)
+#define PORT_LOGIC_SPEED_CHANGE		BIT(17)
 #define PORT_LOGIC_LINK_WIDTH_MASK	(0x1f << 8)
 #define PORT_LOGIC_LINK_WIDTH_1_LANES	(0x1 << 8)
 #define PORT_LOGIC_LINK_WIDTH_2_LANES	(0x2 << 8)
@@ -40,8 +40,8 @@
 #define PCIE_MSI_INTR0_STATUS		0x830
 
 #define PCIE_ATU_VIEWPORT		0x900
-#define PCIE_ATU_REGION_INBOUND		(0x1 << 31)
-#define PCIE_ATU_REGION_OUTBOUND	(0x0 << 31)
+#define PCIE_ATU_REGION_INBOUND		BIT(31)
+#define PCIE_ATU_REGION_OUTBOUND	0
 #define PCIE_ATU_REGION_INDEX2		(0x2 << 0)
 #define PCIE_ATU_REGION_INDEX1		(0x1 << 0)
 #define PCIE_ATU_REGION_INDEX0		(0x0 << 0)
@@ -51,8 +51,8 @@
 #define PCIE_ATU_TYPE_CFG0		(0x4 << 0)
 #define PCIE_ATU_TYPE_CFG1		(0x5 << 0)
 #define PCIE_ATU_CR2			0x908
-#define PCIE_ATU_ENABLE			(0x1 << 31)
-#define PCIE_ATU_BAR_MODE_ENABLE	(0x1 << 30)
+#define PCIE_ATU_ENABLE			BIT(31)
+#define PCIE_ATU_BAR_MODE_ENABLE	BIT(30)
 #define PCIE_ATU_LOWER_BASE		0x90C
 #define PCIE_ATU_UPPER_BASE		0x910
 #define PCIE_ATU_LIMIT			0x914
@@ -92,7 +92,7 @@
 #define PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING     (0x1 << 29)
 
 #define PCIE_MISC_CONTROL_1_OFF		0x8BC
-#define PCIE_DBI_RO_WR_EN		(0x1 << 0)
+#define PCIE_DBI_RO_WR_EN		BIT(0)
 
 /* PCIe Port Logic registers */
 #define PLR_OFFSET                     0x700
-- 
2.24.0


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