The TXEMPTY bit gets set as soon as the transmit FIFO gets empty, so flushing must wait until the bit is set instead of being unset. Signed-off-by: Lucas Stach <dev@xxxxxxxxxx> --- drivers/serial/serial_cadence.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/serial/serial_cadence.c b/drivers/serial/serial_cadence.c index 0501c400b129..6454888e3c5b 100644 --- a/drivers/serial/serial_cadence.c +++ b/drivers/serial/serial_cadence.c @@ -199,7 +199,7 @@ static void cadence_serial_flush(struct console_device *cdev) struct cadence_serial_priv, cdev); while ((readl(priv->regs + CADENCE_UART_CHANNEL_STS) & - CADENCE_STS_TEMPTY) != 0) + CADENCE_STS_TEMPTY) == 0) ; } -- 2.23.0 _______________________________________________ barebox mailing list barebox@xxxxxxxxxxxxxxxxxxx http://lists.infradead.org/mailman/listinfo/barebox
