[PATCH 1/3] Blackfin: Remove architecture

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Blackfin is dead and already removed from the Kernel. Remove it from
barebox as well. RIP.

Signed-off-by: Sascha Hauer <s.hauer@xxxxxxxxxxxxxx>
---
 Documentation/user/barebox.rst                |    1 -
 arch/blackfin/Kconfig                         |   66 -
 arch/blackfin/Makefile                        |   54 -
 arch/blackfin/boards/ipe337/.gitignore        |    1 -
 arch/blackfin/boards/ipe337/Makefile          |    4 -
 arch/blackfin/boards/ipe337/barebox.lds.S     |   97 -
 arch/blackfin/boards/ipe337/cmd_alternate.c   |   53 -
 arch/blackfin/boards/ipe337/config.h          |   46 -
 .../blackfin/boards/ipe337/env/bin/_alternate |    9 -
 arch/blackfin/boards/ipe337/env/bin/_update   |   37 -
 arch/blackfin/boards/ipe337/env/bin/boot      |   54 -
 arch/blackfin/boards/ipe337/env/bin/init      |   24 -
 arch/blackfin/boards/ipe337/env/bin/magic.bin |  Bin 4 -> 0 bytes
 .../boards/ipe337/env/bin/reset_ageing        |   27 -
 .../boards/ipe337/env/bin/update_application  |    8 -
 .../boards/ipe337/env/bin/update_bareboxenv   |    8 -
 .../boards/ipe337/env/bin/update_kernel       |   19 -
 .../boards/ipe337/env/bin/update_persistent   |    8 -
 .../boards/ipe337/env/bin/update_system       |   19 -
 arch/blackfin/boards/ipe337/env/config        |   27 -
 arch/blackfin/boards/ipe337/ipe337.c          |   48 -
 arch/blackfin/configs/ipe337_defconfig        |   29 -
 arch/blackfin/cpu-bf561/Makefile              |    2 -
 arch/blackfin/cpu-bf561/init_sdram.S          |  230 --
 arch/blackfin/cpu-bf561/start.S               |  354 --
 arch/blackfin/include/asm/bitops.h            |   35 -
 arch/blackfin/include/asm/bitsperlong.h       |    1 -
 arch/blackfin/include/asm/blackfin.h          |   74 -
 arch/blackfin/include/asm/blackfin_defs.h     |   79 -
 arch/blackfin/include/asm/byteorder.h         |   36 -
 arch/blackfin/include/asm/common.h            |    1 -
 arch/blackfin/include/asm/cplb.h              |   48 -
 arch/blackfin/include/asm/cpu.h               |   70 -
 arch/blackfin/include/asm/cpu/cdefBF531.h     |   24 -
 arch/blackfin/include/asm/cpu/cdefBF532.h     |  398 ---
 arch/blackfin/include/asm/cpu/cdefBF533.h     |   24 -
 arch/blackfin/include/asm/cpu/cdefBF53x.h     |   32 -
 arch/blackfin/include/asm/cpu/cdefBF561.h     | 1001 ------
 .../include/asm/cpu/cdef_LPBlackfin.h         |  185 -
 arch/blackfin/include/asm/cpu/defBF531.h      |   24 -
 arch/blackfin/include/asm/cpu/defBF532.h      | 1148 -------
 arch/blackfin/include/asm/cpu/defBF533.h      |   24 -
 arch/blackfin/include/asm/cpu/defBF533_extn.h |   76 -
 arch/blackfin/include/asm/cpu/defBF561.h      | 3057 -----------------
 arch/blackfin/include/asm/cpu/defBF561_extn.h |   76 -
 .../blackfin/include/asm/cpu/def_LPBlackfin.h |  445 ---
 arch/blackfin/include/asm/current.h           |   36 -
 arch/blackfin/include/asm/dma.h               |   13 -
 arch/blackfin/include/asm/elf.h               |  127 -
 arch/blackfin/include/asm/entry.h             |  380 --
 arch/blackfin/include/asm/hw_irq.h            |   32 -
 arch/blackfin/include/asm/io.h                |  120 -
 arch/blackfin/include/asm/irq.h               |    8 -
 arch/blackfin/include/asm/linkage.h           |   13 -
 arch/blackfin/include/asm/mem_init.h          |  283 --
 arch/blackfin/include/asm/mmu.h               |    6 -
 arch/blackfin/include/asm/module.h            |   14 -
 arch/blackfin/include/asm/page.h              |   24 -
 arch/blackfin/include/asm/page_offset.h       |   25 -
 arch/blackfin/include/asm/posix_types.h       |    1 -
 arch/blackfin/include/asm/processor.h         |  161 -
 arch/blackfin/include/asm/ptrace.h            |  265 --
 arch/blackfin/include/asm/sections.h          |    1 -
 arch/blackfin/include/asm/segment.h           |   42 -
 arch/blackfin/include/asm/setup.h             |   82 -
 arch/blackfin/include/asm/string.h            |   26 -
 arch/blackfin/include/asm/swab.h              |   50 -
 arch/blackfin/include/asm/system.h            |  177 -
 arch/blackfin/include/asm/traps.h             |   74 -
 arch/blackfin/include/asm/types.h             |   76 -
 arch/blackfin/include/asm/unaligned.h         |   11 -
 arch/blackfin/lib/Makefile                    |   18 -
 arch/blackfin/lib/ashldi3.c                   |   55 -
 arch/blackfin/lib/ashrdi3.c                   |   36 -
 arch/blackfin/lib/asm-offsets.c               |   12 -
 arch/blackfin/lib/bf533_string.c              |  181 -
 arch/blackfin/lib/blackfin_linux.c            |   82 -
 arch/blackfin/lib/board.c                     |   48 -
 arch/blackfin/lib/clock.c                     |   77 -
 arch/blackfin/lib/cpu.c                       |  140 -
 arch/blackfin/lib/divsi3.S                    |  212 --
 arch/blackfin/lib/flush.S                     |  402 ---
 arch/blackfin/lib/gcclib.h                    |   44 -
 arch/blackfin/lib/interrupt.S                 |   92 -
 arch/blackfin/lib/lshrdi3.c                   |   69 -
 arch/blackfin/lib/modsi3.S                    |   76 -
 arch/blackfin/lib/module.c                    |  306 --
 arch/blackfin/lib/muldi3.c                    |   75 -
 arch/blackfin/lib/smulsi3_highpart.S          |   30 -
 arch/blackfin/lib/traps.c                     |  107 -
 arch/blackfin/lib/udivsi3.S                   |  294 --
 arch/blackfin/lib/umodsi3.S                   |   63 -
 arch/blackfin/lib/umulsi3_highpart.S          |   23 -
 93 files changed, 12572 deletions(-)
 delete mode 100644 arch/blackfin/Kconfig
 delete mode 100644 arch/blackfin/Makefile
 delete mode 100644 arch/blackfin/boards/ipe337/.gitignore
 delete mode 100644 arch/blackfin/boards/ipe337/Makefile
 delete mode 100644 arch/blackfin/boards/ipe337/barebox.lds.S
 delete mode 100644 arch/blackfin/boards/ipe337/cmd_alternate.c
 delete mode 100644 arch/blackfin/boards/ipe337/config.h
 delete mode 100644 arch/blackfin/boards/ipe337/env/bin/_alternate
 delete mode 100644 arch/blackfin/boards/ipe337/env/bin/_update
 delete mode 100644 arch/blackfin/boards/ipe337/env/bin/boot
 delete mode 100644 arch/blackfin/boards/ipe337/env/bin/init
 delete mode 100644 arch/blackfin/boards/ipe337/env/bin/magic.bin
 delete mode 100644 arch/blackfin/boards/ipe337/env/bin/reset_ageing
 delete mode 100644 arch/blackfin/boards/ipe337/env/bin/update_application
 delete mode 100644 arch/blackfin/boards/ipe337/env/bin/update_bareboxenv
 delete mode 100644 arch/blackfin/boards/ipe337/env/bin/update_kernel
 delete mode 100644 arch/blackfin/boards/ipe337/env/bin/update_persistent
 delete mode 100644 arch/blackfin/boards/ipe337/env/bin/update_system
 delete mode 100644 arch/blackfin/boards/ipe337/env/config
 delete mode 100644 arch/blackfin/boards/ipe337/ipe337.c
 delete mode 100644 arch/blackfin/configs/ipe337_defconfig
 delete mode 100644 arch/blackfin/cpu-bf561/Makefile
 delete mode 100644 arch/blackfin/cpu-bf561/init_sdram.S
 delete mode 100644 arch/blackfin/cpu-bf561/start.S
 delete mode 100644 arch/blackfin/include/asm/bitops.h
 delete mode 100644 arch/blackfin/include/asm/bitsperlong.h
 delete mode 100644 arch/blackfin/include/asm/blackfin.h
 delete mode 100644 arch/blackfin/include/asm/blackfin_defs.h
 delete mode 100644 arch/blackfin/include/asm/byteorder.h
 delete mode 100644 arch/blackfin/include/asm/common.h
 delete mode 100644 arch/blackfin/include/asm/cplb.h
 delete mode 100644 arch/blackfin/include/asm/cpu.h
 delete mode 100644 arch/blackfin/include/asm/cpu/cdefBF531.h
 delete mode 100644 arch/blackfin/include/asm/cpu/cdefBF532.h
 delete mode 100644 arch/blackfin/include/asm/cpu/cdefBF533.h
 delete mode 100644 arch/blackfin/include/asm/cpu/cdefBF53x.h
 delete mode 100644 arch/blackfin/include/asm/cpu/cdefBF561.h
 delete mode 100644 arch/blackfin/include/asm/cpu/cdef_LPBlackfin.h
 delete mode 100644 arch/blackfin/include/asm/cpu/defBF531.h
 delete mode 100644 arch/blackfin/include/asm/cpu/defBF532.h
 delete mode 100644 arch/blackfin/include/asm/cpu/defBF533.h
 delete mode 100644 arch/blackfin/include/asm/cpu/defBF533_extn.h
 delete mode 100644 arch/blackfin/include/asm/cpu/defBF561.h
 delete mode 100644 arch/blackfin/include/asm/cpu/defBF561_extn.h
 delete mode 100644 arch/blackfin/include/asm/cpu/def_LPBlackfin.h
 delete mode 100644 arch/blackfin/include/asm/current.h
 delete mode 100644 arch/blackfin/include/asm/dma.h
 delete mode 100644 arch/blackfin/include/asm/elf.h
 delete mode 100644 arch/blackfin/include/asm/entry.h
 delete mode 100644 arch/blackfin/include/asm/hw_irq.h
 delete mode 100644 arch/blackfin/include/asm/io.h
 delete mode 100644 arch/blackfin/include/asm/irq.h
 delete mode 100644 arch/blackfin/include/asm/linkage.h
 delete mode 100644 arch/blackfin/include/asm/mem_init.h
 delete mode 100644 arch/blackfin/include/asm/mmu.h
 delete mode 100644 arch/blackfin/include/asm/module.h
 delete mode 100644 arch/blackfin/include/asm/page.h
 delete mode 100644 arch/blackfin/include/asm/page_offset.h
 delete mode 100644 arch/blackfin/include/asm/posix_types.h
 delete mode 100644 arch/blackfin/include/asm/processor.h
 delete mode 100644 arch/blackfin/include/asm/ptrace.h
 delete mode 100644 arch/blackfin/include/asm/sections.h
 delete mode 100644 arch/blackfin/include/asm/segment.h
 delete mode 100644 arch/blackfin/include/asm/setup.h
 delete mode 100644 arch/blackfin/include/asm/string.h
 delete mode 100644 arch/blackfin/include/asm/swab.h
 delete mode 100644 arch/blackfin/include/asm/system.h
 delete mode 100644 arch/blackfin/include/asm/traps.h
 delete mode 100644 arch/blackfin/include/asm/types.h
 delete mode 100644 arch/blackfin/include/asm/unaligned.h
 delete mode 100644 arch/blackfin/lib/Makefile
 delete mode 100644 arch/blackfin/lib/ashldi3.c
 delete mode 100644 arch/blackfin/lib/ashrdi3.c
 delete mode 100644 arch/blackfin/lib/asm-offsets.c
 delete mode 100644 arch/blackfin/lib/bf533_string.c
 delete mode 100644 arch/blackfin/lib/blackfin_linux.c
 delete mode 100644 arch/blackfin/lib/board.c
 delete mode 100644 arch/blackfin/lib/clock.c
 delete mode 100644 arch/blackfin/lib/cpu.c
 delete mode 100644 arch/blackfin/lib/divsi3.S
 delete mode 100644 arch/blackfin/lib/flush.S
 delete mode 100644 arch/blackfin/lib/gcclib.h
 delete mode 100644 arch/blackfin/lib/interrupt.S
 delete mode 100644 arch/blackfin/lib/lshrdi3.c
 delete mode 100644 arch/blackfin/lib/modsi3.S
 delete mode 100644 arch/blackfin/lib/module.c
 delete mode 100644 arch/blackfin/lib/muldi3.c
 delete mode 100644 arch/blackfin/lib/smulsi3_highpart.S
 delete mode 100644 arch/blackfin/lib/traps.c
 delete mode 100644 arch/blackfin/lib/udivsi3.S
 delete mode 100644 arch/blackfin/lib/umodsi3.S
 delete mode 100644 arch/blackfin/lib/umulsi3_highpart.S

diff --git a/Documentation/user/barebox.rst b/Documentation/user/barebox.rst
index c021a4c743..6bea883115 100644
--- a/Documentation/user/barebox.rst
+++ b/Documentation/user/barebox.rst
@@ -53,7 +53,6 @@ variable and the cross compiler with the ``CROSS_COMPILE`` environment
 variable. Currently, ``ARCH`` must be one of:
 
 * arm
-* blackfin
 * mips
 * nios2
 * openrisc
diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig
deleted file mode 100644
index c9b5512c0a..0000000000
--- a/arch/blackfin/Kconfig
+++ /dev/null
@@ -1,66 +0,0 @@
-
-config BLACKFIN
-	bool
-	select HAS_KALLSYMS
-	select HAS_MODULES
-	select HAVE_CONFIGURABLE_MEMORY_LAYOUT
-	select HAVE_CONFIGURABLE_TEXT_BASE
-	select GENERIC_FIND_NEXT_BIT
-	default y
-
-config BF561
-	bool
-
-config ARCH_TEXT_BASE
-	hex
-	default 0x00000000
-	default 0x03f00000 if MACH_IPE337
-
-choice
-	prompt "Select your board"
-
-config MACH_IPE337
-	bool "PII ipe337"
-	select BF561
-	help
-	  Say Y here if you are using the PII IPE337 board
-
-endchoice
-
-choice
-	prompt "Select your board options"
-	depends on MACH_IPE337
-	default MACH_IPE337_V2
-
-config MACH_IPE337_V1
-	bool "revision 1 (25MHz)"
-	help
-	  Say Y here if you are using the first revision of the PII IPE337 board (Crystal running at 25Mhz)
-
-config MACH_IPE337_V2
-	bool "revision 2 (40MHz)"
-	help
-	  Say Y here if you are using the second revision of the PII IPE337 board (Crystal running at 40Mhz)
-
-endchoice
-
-choice
-	prompt "Boot Mode"
-	default BFIN_BOOT_FLASH16
-
-config BFIN_BOOT_BYPASS
-	bool "bypass"
-	help
-	  blackfin is strapped to boot from parallel flash on CS0
-
-config BFIN_BOOT_FLASH8
-	bool "flash 8 bit"
-	help
-	  blackfin is strapped to boot from 8bit wide flash via boot ROM
-
-config BFIN_BOOT_FLASH16
-	bool "flash 16 bit"
-	help
-	  blackfin is strapped to boot from 16bit wide flash via boot ROM
-
-endchoice
diff --git a/arch/blackfin/Makefile b/arch/blackfin/Makefile
deleted file mode 100644
index 5c43bf7d71..0000000000
--- a/arch/blackfin/Makefile
+++ /dev/null
@@ -1,54 +0,0 @@
-KBUILD_DEFCONFIG := ipe337_defconfig
-
-CPPFLAGS += -fno-strict-aliasing
-
-
-board-$(CONFIG_MACH_IPE337)	:= ipe337
-cpu-$(CONFIG_BF561)		:= bf561
-
-TEXT_BASE = $(CONFIG_TEXT_BASE)
-
-CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)
-CFLAGS += -D__blackfin__
-# -Ttext $(TEXT_BASE)
-KALLSYMS         += --symbol-prefix=_
-
-ifndef CONFIG_BFIN_BOOT_BYPASS
-KBUILD_IMAGE := barebox.ldr
-endif
-
-archprepare: maketools
-
-PHONY += maketools
-
-
-ifneq ($(board-y),)
-BOARD  := arch/blackfin/boards/$(board-y)/
-else
-BOARD  :=
-endif
-
-ifneq ($(cpu-y),)
-CPU  := arch/blackfin/cpu-$(cpu-y)/
-else
-CPU  :=
-endif
-
-common-y += $(BOARD)
-common-y += arch/blackfin/lib/ $(CPU)
-
-lds-y += $(BOARD)/barebox.lds
-
-ifdef CONFIG_BFIN_BOOT_FLASH16
-FLASHBITS :=-B 16
-else
-FLASHBITS :=
-endif
-
-ifneq ($(cpu-y),)
-ifndef CONFIG_BFIN_BOOT_BYPASS
-barebox.ldr: barebox
-	rm -f $@
-	$(CROSS_COMPILE)ldr -T $(cpu-y) -c $(FLASHBITS) -i $(CPU)/init_sdram.o $@ $<
-endif
-endif
diff --git a/arch/blackfin/boards/ipe337/.gitignore b/arch/blackfin/boards/ipe337/.gitignore
deleted file mode 100644
index d1165788c9..0000000000
--- a/arch/blackfin/boards/ipe337/.gitignore
+++ /dev/null
@@ -1 +0,0 @@
-barebox.lds
diff --git a/arch/blackfin/boards/ipe337/Makefile b/arch/blackfin/boards/ipe337/Makefile
deleted file mode 100644
index 172dfb688c..0000000000
--- a/arch/blackfin/boards/ipe337/Makefile
+++ /dev/null
@@ -1,4 +0,0 @@
-obj-y += ipe337.o
-obj-y += cmd_alternate.o
-
-extra-y += barebox.lds
diff --git a/arch/blackfin/boards/ipe337/barebox.lds.S b/arch/blackfin/boards/ipe337/barebox.lds.S
deleted file mode 100644
index 7e82a1bd74..0000000000
--- a/arch/blackfin/boards/ipe337/barebox.lds.S
+++ /dev/null
@@ -1,97 +0,0 @@
-/*
- * barebox - barebox.lds.S
- *
- * Copyright (c) 2005-2007 Analog Device Inc.
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@xxxxxxx.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <config.h>
-#include <asm-generic/barebox.lds.h>
-
-OUTPUT_ARCH("bfin")
-SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
-/* Do we need any of these for elf?
-   __DYNAMIC = 0;    */
-/*
-MEMORY
-{
-	ram : 	   ORIGIN = (0x2000000), LENGTH = (256 * 1024)
-	l1_code : ORIGIN = 0xFFA00000, LENGTH = 0xC000
-	l1_data : ORIGIN = 0xFF900000, LENGTH = 0x4000
-}
-*/
-
-SECTIONS
-{
-	. = TEXT_BASE;
-
-	. = ALIGN(4);
-	.text      :
-	{
-		__stext = .;
-		__text = .;
-		_text = .;
-		*(.text_entry)
-		*(.text)
-	}
-
-	. = ALIGN(4);
-	.rodata : { *(.rodata) }
-
-	__etext = .;			/* End of text and rodata section */
-	__sdata = .;
-
-	. = ALIGN(4);
-	.data : { *(.data) }
-
-	. = ALIGN(4);
-	.got : { *(.got) }
-
-	. = .;
-	___barebox_cmd_start = .;
-	.barebox_cmd : { BAREBOX_CMDS }
-	___barebox_cmd_end = .;
-
-	___barebox_ratp_cmd_start = .;
-	.barebox_ratp_cmd : { BAREBOX_RATP_CMDS }
-	___barebox_ratp_cmd_end = .;
-
-	___barebox_magicvar_start = .;
-	.barebox_magicvar : { BAREBOX_MAGICVARS }
-	___barebox_magicvar_end = .;
-
-	___barebox_initcalls_start = .;
-	.barebox_initcalls : { INITCALLS }
-	___barebox_initcalls_end = .;
-
-	___barebox_exitcalls_start = .;
-	.barebox_exitcalls : { EXITCALLS }
-	___barebox_exitcalls_end = .;
-
-	___usymtab_start = .;
-	__usymtab : { BAREBOX_SYMS }
-	___usymtab_end = .;
-
-	__edata = .;
-	. = ALIGN(4);
-	___bss_start = .;
-	.bss : { *(.bss) }
-	___bss_stop = .;
-	_end = .;
-}
diff --git a/arch/blackfin/boards/ipe337/cmd_alternate.c b/arch/blackfin/boards/ipe337/cmd_alternate.c
deleted file mode 100644
index b332cfb059..0000000000
--- a/arch/blackfin/boards/ipe337/cmd_alternate.c
+++ /dev/null
@@ -1,53 +0,0 @@
-#include <common.h>
-#include <command.h>
-#include <libfile.h>
-#include <linux/stat.h>
-#include <malloc.h>
-#include <fs.h>
-
-#define MAGIC		0x19691228
-
-static int do_alternate(int argc, char *argv[])
-{
-	void *buf;
-	size_t size;
-	ulong *ptr, val = 0, bitcount = 0;
-
-	if (argc != 2)
-		return COMMAND_ERROR_USAGE;
-
-	buf = read_file(argv[1], &size);
-	if (!buf)
-		return 1;
-
-	ptr = buf;
-	if ((*ptr) != MAGIC) {
-		printf("Wrong magic! Expected 0x%08x, got 0x%08lx.\n", MAGIC, *ptr);
-		return 1;
-	}
-
-	ptr++;
-
-	while ((ulong)ptr <= (ulong)buf + size && !(val = *ptr++))
-		bitcount += 32;
-
-	if (val) {
-		do {
-			if (val & 1)
-				break;
-			bitcount++;
-		} while (val >>= 1);
-	}
-
-	printf("Bitcount : %ld\n", bitcount);
-
-	free(buf);
-	return (bitcount & 1) ? 3 : 2;
-}
-
-BAREBOX_CMD_START(alternate)
-	.cmd		= do_alternate,
-	BAREBOX_CMD_DESC("count zero bits in a file")
-	BAREBOX_CMD_OPTS("FILE")
-	BAREBOX_CMD_GROUP(CMD_GRP_FILE)
-BAREBOX_CMD_END
diff --git a/arch/blackfin/boards/ipe337/config.h b/arch/blackfin/boards/ipe337/config.h
deleted file mode 100644
index aa25d0792d..0000000000
--- a/arch/blackfin/boards/ipe337/config.h
+++ /dev/null
@@ -1,46 +0,0 @@
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * Clock settings
- */
-
-/* CONFIG_CLKIN_HZ is any value in Hz                            */
-#if   defined(CONFIG_MACH_IPE337_V1)
-#define CONFIG_CLKIN_HZ          25000000
-#elif defined(CONFIG_MACH_IPE337_V2)
-#define CONFIG_CLKIN_HZ          40000000
-#else
-#error "Unknown IPE337 revision"
-#endif
-
-/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN      */
-/*                                                  1=CLKIN/2    */
-#define CONFIG_CLKIN_HALF               0
-/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass  */
-/*                                               1=bypass PLL    */
-#define CONFIG_PLL_BYPASS               0
-/* CONFIG_VCO_MULT controls what the multiplier of the PLL is.   */
-/* Values can range from 1-64                                    */
-#define CONFIG_VCO_MULT		       10         /* POR default */
-/* CONFIG_CCLK_DIV controls what the core clock divider is       */
-/* Values can be 1, 2, 4, or 8 ONLY                              */
-#define CONFIG_CCLK_DIV			1         /* POR default */
-/* CONFIG_SCLK_DIV controls what the peripheral clock divider is */
-/* Values can range from 1-15                                    */
-#define CONFIG_SCLK_DIV			5         /* POR default */
-
-/* Frequencies selected: 400MHz CCLK / 80MHz SCLK ^= 12.5ns cycle time*/
-
-#define AMGCTLVAL               0x1F
-
-/* no need for speed, currently, leave at defaults */
-#define AMBCTL0VAL              0xFFC2FFC2
-#define AMBCTL1VAL              0xFFC2FFC2
-
-#define CONFIG_MEM_MT48LC16M16A2TG_75    1
-#define CONFIG_MEM_ADD_WDTH              9           /* 8, 9, 10, 11    */
-#define CONFIG_MEM_SIZE                 64           /* 128, 64, 32, 16 */
-
-#endif	/* __CONFIG_H */
diff --git a/arch/blackfin/boards/ipe337/env/bin/_alternate b/arch/blackfin/boards/ipe337/env/bin/_alternate
deleted file mode 100644
index 10ae2134c0..0000000000
--- a/arch/blackfin/boards/ipe337/env/bin/_alternate
+++ /dev/null
@@ -1,9 +0,0 @@
-#!/bin/sh
-
-. /env/config
-
-alternate $ageing
-if [ $? -lt 2 ]; then
-	echo "Error when accesing ageing-partition!"
-	exit 1
-fi
diff --git a/arch/blackfin/boards/ipe337/env/bin/_update b/arch/blackfin/boards/ipe337/env/bin/_update
deleted file mode 100644
index 5419ece6a7..0000000000
--- a/arch/blackfin/boards/ipe337/env/bin/_update
+++ /dev/null
@@ -1,37 +0,0 @@
-#!/bin/sh
-
-if [ $# = 1 ]; then
-	image=$1
-fi
-
-if [ -z "$part" -o -z "$image" ]; then
-	echo "define \$part and \$image"
-	exit 1
-fi
-
-if [ ! -e "$part" ]; then
-	echo "Partition $part does not exist"
-	exit 1
-fi
-
-if [ x$ip = xdhcp ]; then
-	dhcp
-fi
-
-ping $eth0.serverip
-if [ $? -ne 0 ] ; then
-	echo "update aborted"
-	exit 1
-fi
-
-unprotect $part
-
-echo
-echo "Erasing partition $part"
-erase $part
-
-echo
-echo "Flashing $image to $part"
-tftp $image $part
-
-protect $part
diff --git a/arch/blackfin/boards/ipe337/env/bin/boot b/arch/blackfin/boards/ipe337/env/bin/boot
deleted file mode 100644
index 62807d211f..0000000000
--- a/arch/blackfin/boards/ipe337/env/bin/boot
+++ /dev/null
@@ -1,54 +0,0 @@
-#!/bin/sh
-
-. /env/config
-
-alternate $ageing
-ret=$?
-
-if [ $ret = 0 ]; then
-	echo "Error when accesing ageing-partition!"
-	exit 1
-elif [ $ret = 2 ]; then
-	act_kernel=/dev/nor0.kernel0
-	act_rootfs=/dev/mtdblock5
-else
-	act_kernel=/dev/nor0.kernel1
-	act_rootfs=/dev/mtdblock6
-fi
-echo "-> Active kernel: $act_kernel"
-echo "-> Active system: $act_rootfs"
-echo
-
-if [ x$1 = xflash ]; then
-	root=flash
-	kernel=flash
-fi
-
-if [ x$1 = xnet ]; then
-	root=net
-	kernel=net
-fi
-
-if [ x$ip = xdhcp ]; then
-	bootargs="$bootargs ip=dhcp"
-else
-	bootargs="$bootargs ip=$eth0.ipaddr:$eth0.serverip:$eth0.gateway:$eth0.netmask:::"
-fi
-
-if [ x$root = xflash ]; then
-	bootargs="$bootargs root=$act_rootfs rootfstype=jffs2"
-else
-	bootargs="$bootargs root=/dev/nfs nfsroot=$eth0.serverip:$nfsroot,v3,tcp"
-fi
-
-bootargs="$bootargs mtdparts=physmap-flash.0:$mtdparts"
-
-if [ $kernel = net ]; then
-	if [ x$ip = xdhcp ]; then
-		dhcp
-	fi
-	tftp $uimage uImage || exit 1
-	bootm uImage
-else
-	bootm $act_kernel
-fi
diff --git a/arch/blackfin/boards/ipe337/env/bin/init b/arch/blackfin/boards/ipe337/env/bin/init
deleted file mode 100644
index e864dc5a42..0000000000
--- a/arch/blackfin/boards/ipe337/env/bin/init
+++ /dev/null
@@ -1,24 +0,0 @@
-#!/bin/sh
-
-PATH=/env/bin
-export PATH
-
-. /env/config
-addpart /dev/nor0 $mtdparts
-
-echo
-echo -n "Hit any key to stop autoboot: "
-timeout -a $autoboot_timeout
-if [ $? != 0 ]; then
-	echo
-	echo "Type update_kernel [<imagename>] to update kernel into flash."
-	echo "Type update_system [<imagename>] to update rootfs into flash."
-	echo "Type update_application [<imagename>] to update applications into flash."
-	echo "Type update_persistent [<imagename>] to update persistent into flash."
-	echo "Type update_bareboxenv [<imagename>] to update bareboxenv into flash (use with care!)."
-	echo "Type reset_ageing to initialize the ageing partittion (use with care!)."
-	echo
-	exit
-fi
-
-boot
diff --git a/arch/blackfin/boards/ipe337/env/bin/magic.bin b/arch/blackfin/boards/ipe337/env/bin/magic.bin
deleted file mode 100644
index f8bff393cf3d9fccea0fd366d9939a60c94f17c4..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 4
LcmdN8%9I2E0mT5l

diff --git a/arch/blackfin/boards/ipe337/env/bin/reset_ageing b/arch/blackfin/boards/ipe337/env/bin/reset_ageing
deleted file mode 100644
index 2c95ae762e..0000000000
--- a/arch/blackfin/boards/ipe337/env/bin/reset_ageing
+++ /dev/null
@@ -1,27 +0,0 @@
-#!/bin/sh
-
-. /env/config
-
-image=/env/bin/magic.bin
-part=$ageing
-
-if [ \! -e "$part" ]; then
-	echo "Partition $part does not exist"
-	exit 1
-fi
-
-unprotect $part
-
-echo
-echo "Erasing partition $part"
-erase $part
-
-echo
-echo "Creating magic"
-cp $image $part
-
-echo
-echo "Testing partition"
-. /env/bin/_alternate
-
-protect $part
diff --git a/arch/blackfin/boards/ipe337/env/bin/update_application b/arch/blackfin/boards/ipe337/env/bin/update_application
deleted file mode 100644
index 46ad210e36..0000000000
--- a/arch/blackfin/boards/ipe337/env/bin/update_application
+++ /dev/null
@@ -1,8 +0,0 @@
-#!/bin/sh
-
-. /env/config
-
-image=$appimage
-part=/dev/nor0.application
-
-. /env/bin/_update $1
diff --git a/arch/blackfin/boards/ipe337/env/bin/update_bareboxenv b/arch/blackfin/boards/ipe337/env/bin/update_bareboxenv
deleted file mode 100644
index b0a32c626b..0000000000
--- a/arch/blackfin/boards/ipe337/env/bin/update_bareboxenv
+++ /dev/null
@@ -1,8 +0,0 @@
-#!/bin/sh
-
-. /env/config
-
-image=$envimage
-part=/dev/nor0.bareboxenv
-
-. /env/bin/_update $1
diff --git a/arch/blackfin/boards/ipe337/env/bin/update_kernel b/arch/blackfin/boards/ipe337/env/bin/update_kernel
deleted file mode 100644
index d5c210eb2b..0000000000
--- a/arch/blackfin/boards/ipe337/env/bin/update_kernel
+++ /dev/null
@@ -1,19 +0,0 @@
-#!/bin/sh
-
-. /env/config
-
-image=$uimage
-
-alternate $ageing
-ret=$?
-
-if [ $ret = 0 ]; then
-	echo "Error when accesing ageing-partition!"
-	exit 1
-elif [ $ret = 2 ]; then
-	part=/dev/nor0.kernel0
-else
-	part=/dev/nor0.kernel1
-fi
-
-. /env/bin/_update $1
diff --git a/arch/blackfin/boards/ipe337/env/bin/update_persistent b/arch/blackfin/boards/ipe337/env/bin/update_persistent
deleted file mode 100644
index a869b2218d..0000000000
--- a/arch/blackfin/boards/ipe337/env/bin/update_persistent
+++ /dev/null
@@ -1,8 +0,0 @@
-#!/bin/sh
-
-. /env/config
-
-image=$perimage
-part=/dev/nor0.persistent
-
-. /env/bin/_update $1
diff --git a/arch/blackfin/boards/ipe337/env/bin/update_system b/arch/blackfin/boards/ipe337/env/bin/update_system
deleted file mode 100644
index 598fc10e81..0000000000
--- a/arch/blackfin/boards/ipe337/env/bin/update_system
+++ /dev/null
@@ -1,19 +0,0 @@
-#!/bin/sh
-
-. /env/config
-
-image=$jffs2
-
-alternate $ageing
-ret=$?
-
-if [ $ret = 0 ]; then
-	echo "Error when accesing ageing-partition!"
-	exit 1
-elif [ $ret = 2 ]; then
-	part=/dev/nor0.system0
-else
-	part=/dev/nor0.system1
-fi
-
-. /env/bin/_update $1
diff --git a/arch/blackfin/boards/ipe337/env/config b/arch/blackfin/boards/ipe337/env/config
deleted file mode 100644
index 7c5ee76e30..0000000000
--- a/arch/blackfin/boards/ipe337/env/config
+++ /dev/null
@@ -1,27 +0,0 @@
-#!/bin/sh
-
-# can be either 'net' or 'flash'
-kernel=net
-root=net
-
-# use 'dhcp' todo dhcp in barebox and in kernel
-#ip=dhcp
-
-eth0.ipaddr=192.168.23.164
-eth0.netmask=255.255.255.0
-eth0.gateway=192.168.23.2
-eth0.serverip=192.168.23.2
-
-uimage=uImage-bfin
-jffs2=root-bfin.jffs2
-appimage=apps-bfin
-perimage=pers-bfin
-envimage=uEnv-bfin
-
-autoboot_timeout=1
-
-nfsroot="/ptx/work/octopus/wsa/svn/OSELAS.BSP-Pipetronix-ipe337-trunk/root"
-bootargs="console=ttyBF0,115200"
-
-mtdparts="128k(barebox)ro,128k(bareboxenv),128k(ageing),1280k(kernel0),1280k(kernel1),8704k(system0),8704k(system1),8320k(application),4096k(persistent)"
-ageing=/dev/nor0.ageing
diff --git a/arch/blackfin/boards/ipe337/ipe337.c b/arch/blackfin/boards/ipe337/ipe337.c
deleted file mode 100644
index 604062a54b..0000000000
--- a/arch/blackfin/boards/ipe337/ipe337.c
+++ /dev/null
@@ -1,48 +0,0 @@
-#include <common.h>
-#include <init.h>
-#include <driver.h>
-#include <asm/cpu/cdefBF561.h>
-#include <partition.h>
-#include <fs.h>
-#include <platform_data/eth-smc911x.h>
-
-struct smc911x_plat smcplat = {
-	.shift = 1,
-};
-
-static int ipe337_devices_init(void) {
-	add_cfi_flash_device(DEVICE_ID_DYNAMIC, 0x20000000, 32 * 1024 * 1024, 0);
-	add_mem_device("ram0", 0x0, 128 * 1024 * 1024,
-		       IORESOURCE_MEM_WRITEABLE);
-
-	/* Reset smc911x */
-	*pFIO0_DIR = (1<<12);
-	*pFIO0_FLAG_C = (1<<12);
-	mdelay(100);
-	*pFIO0_FLAG_S = (1<<12);
-
-	add_generic_device("smc911x", DEVICE_ID_DYNAMIC, NULL, 0x24000000, 4096,
-			   IORESOURCE_MEM, &smcplat);
-
-	devfs_add_partition("nor0", 0x00000, 0x20000, DEVFS_PARTITION_FIXED, "self0");
-	devfs_add_partition("nor0", 0x20000, 0x20000, DEVFS_PARTITION_FIXED, "env0");
-
-	protect_file("/dev/env0", 1);
-
-	return 0;
-}
-
-device_initcall(ipe337_devices_init);
-
-static int blackfin_console_init(void)
-{
-	barebox_set_model("PII ipe337");
-	barebox_set_hostname("ipe337");
-
-	add_generic_device("blackfin_serial", DEVICE_ID_DYNAMIC, NULL, 0, 4096,
-			   IORESOURCE_MEM, NULL);
-
-	return 0;
-}
-
-console_initcall(blackfin_console_init);
diff --git a/arch/blackfin/configs/ipe337_defconfig b/arch/blackfin/configs/ipe337_defconfig
deleted file mode 100644
index 032bdadbdb..0000000000
--- a/arch/blackfin/configs/ipe337_defconfig
+++ /dev/null
@@ -1,29 +0,0 @@
-CONFIG_TEXT_BASE=0x03f00000
-CONFIG_CMDLINE_EDITING=y
-CONFIG_BOOTM_SHOW_TYPE=y
-CONFIG_PARTITION=y
-CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/blackfin/boards/ipe337/env"
-CONFIG_LONGHELP=y
-CONFIG_CMD_MEMINFO=y
-CONFIG_CMD_GO=y
-CONFIG_CMD_RESET=y
-CONFIG_CMD_PARTITION=y
-CONFIG_CMD_EXPORT=y
-CONFIG_CMD_LOADENV=y
-CONFIG_CMD_PRINTENV=y
-CONFIG_CMD_SAVEENV=y
-CONFIG_CMD_SLEEP=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_TFTP=y
-CONFIG_CMD_EDIT=y
-CONFIG_CMD_READLINE=y
-CONFIG_CMD_TIMEOUT=y
-CONFIG_CMD_CRC=y
-CONFIG_CMD_FLASH=y
-CONFIG_NET=y
-CONFIG_DRIVER_NET_SMC911X=y
-CONFIG_MTD=y
-CONFIG_DRIVER_CFI=y
-CONFIG_CFI_BUFFER_WRITE=y
-CONFIG_FS_TFTP=y
diff --git a/arch/blackfin/cpu-bf561/Makefile b/arch/blackfin/cpu-bf561/Makefile
deleted file mode 100644
index 1348febb45..0000000000
--- a/arch/blackfin/cpu-bf561/Makefile
+++ /dev/null
@@ -1,2 +0,0 @@
-obj-y += start.o
-obj-y += init_sdram.o
diff --git a/arch/blackfin/cpu-bf561/init_sdram.S b/arch/blackfin/cpu-bf561/init_sdram.S
deleted file mode 100644
index 88e592a574..0000000000
--- a/arch/blackfin/cpu-bf561/init_sdram.S
+++ /dev/null
@@ -1,230 +0,0 @@
-#define ASSEMBLY
-
-#include <config.h>
-#include <asm/blackfin.h>
-#include <asm/mem_init.h>
-.global init_sdram;
-
-init_sdram:
-	[--SP] = ASTAT;
-	[--SP] = RETS;
-	[--SP] = (R7:0);
-	[--SP] = (P5:0);
-
-#ifndef BF537_UART_BOOT
-
-#ifdef CONFIG_BF537
-	/* Enable PHY CLK buffer output */
-	p0.h = hi(VR_CTL);
-	p0.l = lo(VR_CTL);
-	r0.l = w[p0];
-	bitset(r0, 14);
-	w[p0] = r0.l;
-	ssync;
-#endif
-	/*
-         * PLL_LOCKCNT - how many SCLK Cycles to delay while PLL becomes stable
-         */
-	p0.h = hi(PLL_LOCKCNT);
-	p0.l = lo(PLL_LOCKCNT);
-	r0 = 0x640(Z);
-	w[p0] = r0.l;
-	ssync;
-
-	/*
-         * Put SDRAM in self-refresh, incase anything is running
-         */
-        P2.H = hi(EBIU_SDGCTL);
-        P2.L = lo(EBIU_SDGCTL);
-        R0 = [P2];
-        BITSET (R0, 24);
-        [P2] = R0;
-        SSYNC;
-
-	/* Make sure PLL wakeup is enabled as BOOT ROM seems to disable
-	 * it. (R7 and R6 used to store original value!)
-	 */
-	p0.h = hi(SIC_IWR);
-	p0.l = lo(SIC_IWR);
-	r7 = [p0];
-	r0 = 1;
-	[p0] = r0;
-#ifdef SICA_IWR1
-	p0.h = hi(SICA_IWR1);
-	p0.l = lo(SICA_IWR1);
-	r6 = [p0];
-	r0 = 0;
-	[p0] = r0;
-#endif
-	ssync;
-
-#ifdef CONFIG_VSEL
-	/*
-	 *
-	 * Set Voltage Regulator.
-	 */
-
-	p2.h = hi(VR_CTL);
-	p2.l = lo(VR_CTL);
-	r0 = w[p2];
-	r1 = ~0xf0;
-	r0 = r0 & r1;
-	r1 = CONFIG_VSEL & 0x0f;
-	r1 = r1 << 4;
-	r0 = r0 | r1;
-	cli r2;
-	ssync;
-	w[p2] = r0.l;
-	idle;
-	sti r2;
-#endif
-
-        /*
-         *  Set PLL_CTL with the value that we calculate in R0
-         *   - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
-         *   - [8]     = BYPASS    : BYPASS the PLL, run CLKIN into CCLK/SCLK
-         *   - [7]     = output delay (add 200ps of delay to mem signals)
-         *   - [6]     = input delay (add 200ps of input delay to mem signals)
-         *   - [5]     = PDWN      : 1=All Clocks off
-         *   - [3]     = STOPCK    : 1=Core Clock off
-         *   - [1]     = PLL_OFF   : 1=Disable Power to PLL
-         *   - [0]     = DF        : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
-         *   all other bits set to zero
-         */
-
-	/* first, explicitly enable DF, due to anomaly 05000242 */
-	p0.h = hi(PLL_CTL);
-	p0.l = lo(PLL_CTL);             /* Load the address                */
-	r0.l = w[p0];
-	r1 = 1;
-	r0 = r0 | r1;
-	cli r2;
-	ssync;
-	w[p0] = r0.l;
-	idle;
-	sti r2;
-
-        r0 = CONFIG_VCO_MULT & 63;      /* Load the VCO multiplier         */
-        r0 = r0 << 9;                   /* Shift it over,                  */
-        r1 = CONFIG_CLKIN_HALF;        /* Do we need to divide CLKIN by 2?*/
-        r0 = r1 | r0;
-        r1 = CONFIG_PLL_BYPASS;         /* Bypass the PLL?                 */
-        r1 = r1 << 8;                   /* Shift it over                   */
-        r0 = r1 | r0;                   /* add them all together           */
-
-        p0.h = hi(PLL_CTL);
-        p0.l = lo(PLL_CTL);             /* Load the address                */
-        cli r2;                         /* Disable interrupts              */
-	ssync;
-        w[p0] = r0.l;                   /* Set the value                   */
-        idle;                           /* Wait for the PLL to stablize    */
-        sti r2;                         /* Enable interrupts               */
-
-check_again:
-	p0.h = hi(PLL_STAT);
-	p0.l = lo(PLL_STAT);
-	R0 = W[P0](Z);
-	CC = BITTST(R0,5);
-	if ! CC jump check_again;
-
-	/* Configure SCLK & CCLK Dividers */
-       	r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
-        p0.h = hi(PLL_DIV);
-        p0.l = lo(PLL_DIV);
-        w[p0] = r0.l;
-        ssync;
-#endif
-
-	/*
-         * We now are running at speed, time to set the Async mem bank wait states
-	 * This will speed up execution, since we are normally running from FLASH.
-	 */
-
-        p2.h = (EBIU_AMBCTL1 >> 16);
-        p2.l = (EBIU_AMBCTL1 & 0xFFFF);
-        r0.h = (AMBCTL1VAL >> 16);
-        r0.l = (AMBCTL1VAL & 0xFFFF);
-        [p2] = r0;
-        ssync;
-
-        p2.h = (EBIU_AMBCTL0 >> 16);
-        p2.l = (EBIU_AMBCTL0 & 0xFFFF);
-        r0.h = (AMBCTL0VAL >> 16);
-        r0.l = (AMBCTL0VAL & 0xFFFF);
-        [p2] = r0;
-        ssync;
-
-        p2.h = (EBIU_AMGCTL >> 16);
-        p2.l = (EBIU_AMGCTL & 0xffff);
-        r0 = AMGCTLVAL;
-        w[p2] = r0;
-        ssync;
-
-	/*
-	 * Now, Initialize the SDRAM,
-	 * start with the SDRAM Refresh Rate Control Register
-         */
-	p0.l = lo(EBIU_SDRRC);
-        p0.h = hi(EBIU_SDRRC);
-        r0 = mem_SDRRC;
-        w[p0] = r0.l;
-        ssync;
-
-	/*
-	 * SDRAM Memory Bank Control Register - bank specific parameters
-	 */
-	p0.l = (EBIU_SDBCTL & 0xFFFF);
-	p0.h = (EBIU_SDBCTL >> 16);
-	r0 = mem_SDBCTL;
-	w[p0] = r0.l;
-	ssync;
-
-	/*
-	 * SDRAM Global Control Register - global programmable parameters
-	 * Disable self-refresh
-	 */
-	P2.H = hi(EBIU_SDGCTL);
-        P2.L = lo(EBIU_SDGCTL);
-        R0 = [P2];
-        BITCLR (R0, 24);
-
-	/*
-         * Check if SDRAM is already powered up, if it is, enable self-refresh
-         */
-	p0.h = hi(EBIU_SDSTAT);
-	p0.l = lo(EBIU_SDSTAT);
-	r2.l = w[p0];
-	cc = bittst(r2,3);
-	if !cc jump skip;
-    	NOP;
-	BITSET (R0, 23);
-skip:
-	[P2] = R0;
-        SSYNC;
-
-	/* Write in the new value in the register */
-        R0.L = lo(mem_SDGCTL);
-        R0.H = hi(mem_SDGCTL);
-	[P2] = R0;
-        SSYNC;
-	nop;
-
-	/*
-	 * Restore wakeup
-	 */
-	p0.h = hi(SIC_IWR);
-	p0.l = lo(SIC_IWR);
-	[p0] = r7;
-#ifdef SICA_IWR1
-	p0.h = hi(SICA_IWR1);
-	p0.l = lo(SICA_IWR1);
-	[p0] = r6;
-#endif
-	ssync;
-
-	(P5:0) = [SP++];
-	(R7:0) = [SP++];
-	RETS   = [SP++];
-	ASTAT  = [SP++];
-	RTS;
-
diff --git a/arch/blackfin/cpu-bf561/start.S b/arch/blackfin/cpu-bf561/start.S
deleted file mode 100644
index 56c5e8455d..0000000000
--- a/arch/blackfin/cpu-bf561/start.S
+++ /dev/null
@@ -1,354 +0,0 @@
-/*
- * barebox - start.S Startup file of barebox for BF533/BF561
- *
- * Copyright (c) 2005 blackfin.uclinux.org
- *
- * This file is based on head.S
- * Copyright (c) 2003  Metrowerks/Motorola
- * Copyright (C) 1998  D. Jeff Dionne <jeff@xxxxxxxxxxxxxxxxxxxx>,
- *                     Kenneth Albanowski <kjahds@xxxxxxxxxx>,
- *                     The Silver Hammer Group, Ltd.
- * (c) 1995, Dionne & Associates
- * (c) 1995, DKG Display Tech.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <config.h>
-#include <asm/blackfin.h>
-#include <asm/cpu/defBF561_extn.h>
-#include <asm/cpu/defBF561.h>
-#include <asm-generic/memory_layout.h>
-
-.section ".text_entry","ax"
-
-.macro checker
-	p0.h = FIO0_DIR >> 16;
-	p0.l = FIO0_DIR & 0xFFFF;
-	r0 = (1 << 9);
-	w[p0] = r0;
-	p0.h = FIO0_FLAG_S >> 16;
-	p0.l = FIO0_FLAG_S & 0xFFFF;
-	r0 = (1 << 9);
-	w[p0] = r0;
-1:
-	jump 1b
-.endm
-
-_start:
-start:
-_stext:
-
-	R0 = 0x32;
-	SYSCFG = R0;
-	SSYNC;
-
-	/* As per HW reference manual DAG registers,
-	 * DATA and Address resgister shall be zero'd
-	 * in initialization, after a reset state
-	 */
-	r1 = 0;	/* Data registers zero'd */
-	r2 = 0;
-	r3 = 0;
-	r4 = 0;
-	r5 = 0;
-	r6 = 0;
-	r7 = 0;
-
-	p0 = 0; /* Address registers zero'd */
-	p1 = 0;
-	p2 = 0;
-	p3 = 0;
-	p4 = 0;
-	p5 = 0;
-
-	i0 = 0; /* DAG Registers zero'd */
-	i1 = 0;
-	i2 = 0;
-	i3 = 0;
-	m0 = 0;
-	m1 = 0;
-	m3 = 0;
-	m3 = 0;
-	l0 = 0;
-	l1 = 0;
-	l2 = 0;
-	l3 = 0;
-	b0 = 0;
-	b1 = 0;
-	b2 = 0;
-	b3 = 0;
-
-	/* Set loop counters to zero, to make sure that
-	 * hw loops are disabled.
-	 */
-	r0  = 0;
-	lc0 = r0;
-	lc1 = r0;
-
-	SSYNC;
-
-	/* Check soft reset status */
-	p0.h = SWRST >> 16;
-	p0.l = SWRST & 0xFFFF;
-	r0.l = w[p0];
-
-	cc = bittst(r0, 15);
-	if !cc jump no_soft_reset;
-
-	/* Clear Soft reset */
-	r0 = 0x0000;
-	w[p0] = r0;
-	ssync;
-
-no_soft_reset:
-	nop;
-
-	/* Clear EVT registers */
-	p0.h = hi(EVT_EMULATION_ADDR)
-	p0.l = lo(EVT_EMULATION_ADDR);
-	p0 += 8;
-	p1 = 14;
-	r1 = 0;
-	LSETUP(4,4) lc0 = p1;
-	[ p0 ++ ] = r1;
-
-	p0.h = hi(SIC_IWR);
-        p0.l = lo(SIC_IWR);
-        r0.l = 0x1;
-        w[p0] = r0.l;
-        SSYNC;
-
-	sp.l = lo(0xffb01000);
-	sp.h = hi(0xffb01000);
-
-	/* Check if the code is in SDRAM */
-	/* If the code is in SDRAM, skip SDRAM initializaiton */
-	call get_pc;
-	r3.l = 0x0;
-	r3.h = 0x2000;
-	cc = r0 < r3 (iu);
-	if cc jump sdram_initialized;
-	call init_sdram;
-	/* relocate into to RAM */
-sdram_initialized:
-	call get_pc;
-offset:
-	r2.l = offset;
-	r2.h = offset;
-	r3.l = start;
-	r3.h = start;
-	r1 = r2 - r3;
-
-	r0 = r0 - r1;
-	p1 = r0;
-
-	p2.l = lo(TEXT_BASE);
-	p2.h = hi(TEXT_BASE);
-
-	p3 = 0x04;
-	p4.l = ___bss_start;
-	p4.h = ___bss_start;
-loop1:
-	r1 = [p1 ++ p3];
-	[p2 ++ p3] = r1;
-	cc=p2==p4;
-	if !cc jump loop1;
-
-	/*
-	 * configure STACK
-	 */
-
-	r0.h = hi(STACK_BASE);
-	r0.l = lo(STACK_BASE);
-	sp = r0;
-	fp = sp;
-
-	/*
-	 * This next section keeps the processor in supervisor mode
-	 * during kernel boot.  Switches to user mode at end of boot.
-	 * See page 3-9 of Hardware Reference manual for documentation.
-	 */
-
-	/* To keep ourselves in the supervisor mode */
-	p0.l = lo(EVT_IVG15_ADDR);
-	p0.h = hi(EVT_IVG15_ADDR);
-
-	p1.l = _real_start;
-	p1.h = _real_start;
-	[p0] = p1;
-
-	p0.l = lo(IMASK);
-	p0.h = hi(IMASK);
-	r0.l = lo(IVG15_POS);
-	r0.h = hi(IVG15_POS);
-	[p0] = r0;
-	raise 15;
-	p0.l = WAIT_HERE;
-	p0.h = WAIT_HERE;
-	reti = p0;
-	rti;
-
-WAIT_HERE:
-	jump WAIT_HERE;
-
-.global _real_start;
-_real_start:
-	[ -- sp ] = reti;
-
-#if defined(CONFIG_EZKIT533) || defined(CONFIG_EZKIT561)
-	p0.l = lo(WDOG_CTL);
-	p0.h = hi(WDOG_CTL);
-	r0 = WATCHDOG_DISABLE(z);
-	w[p0] = r0;
-#endif
-
-
-#ifdef CONFIG_BF537
-/* Initialise General-Purpose I/O Modules on BF537
- * Rev 0.0 Anomaly 05000212 - PORTx_FER,
- * PORT_MUX Registers Do Not accept "writes" correctly
- */
-        p0.h = hi(PORTF_FER);
-        p0.l = lo(PORTF_FER);
-        R0.L = W[P0]; /* Read */
-	nop;
-	nop;
-	nop;
-        ssync;
-        R0 = 0x000F(Z);
-        W[P0] = R0.L; /* Write */
-	nop;
-	nop;
-	nop;
-        ssync;
-        W[P0] = R0.L; /* Enable peripheral function of PORTF for UART0 and UART1 */
-	nop;
-	nop;
-	nop;
-        ssync;
-
- 	p0.h = hi(PORTH_FER);
-        p0.l = lo(PORTH_FER);
-        R0.L = W[P0]; /* Read */
-        nop;
-        nop;
-        nop;
-        ssync;
-        R0 = 0xFFFF(Z);
-        W[P0] = R0.L; /* Write */
-        nop;
-        nop;
-        nop;
-        ssync;
-        W[P0] = R0.L; /* Enable peripheral function of PORTH for MAC */
-        nop;
-        nop;
-        nop;
-        ssync;
-
-#endif
-
-	/* DMA reset code to Hi of L1 SRAM */
-copy:
-	P1.H = hi(SYSMMR_BASE);	/* P1 Points to the beginning of SYSTEM MMR Space */
-	P1.L = lo(SYSMMR_BASE);
-
-	R0.H = reset_start;	/* Source Address (high) */
-	R0.L = reset_start;	/* Source Address (low) */
-	R1.H = reset_end;
-	R1.L = reset_end;
-	R2 = R1 - R0;		/* Count */
-	R1.H = hi(L1_ISRAM);	/* Destination Address (high) */
-	R1.L = lo(L1_ISRAM);	/* Destination Address (low) */
-	R3.L = DMAEN;		/* Source DMAConfig Value (8-bit words) */
-	R4.L = (DI_EN | WNR | DMAEN);	/* Destination DMAConfig Value (8-bit words) */
-
-DMA:
-	R6 = 0x1 (Z);
-	W[P1+OFFSET_(MDMA_S0_X_MODIFY)] = R6;	/* Source Modify = 1 */
-	W[P1+OFFSET_(MDMA_D0_X_MODIFY)] = R6;	/* Destination Modify = 1 */
-
-	[P1+OFFSET_(MDMA_S0_START_ADDR)] = R0;	/* Set Source Base Address */
-	W[P1+OFFSET_(MDMA_S0_X_COUNT)] = R2;	/* Set Source Count */
-	/* Set Source  DMAConfig = DMA Enable,
-	Memory Read,  8-Bit Transfers, 1-D DMA, Flow - Stop */
-	W[P1+OFFSET_(MDMA_S0_CONFIG)] = R3;
-
-	[P1+OFFSET_(MDMA_D0_START_ADDR)] = R1;	/* Set Destination Base Address */
-	W[P1+OFFSET_(MDMA_D0_X_COUNT)] = R2;	/* Set Destination Count */
-	/* Set Destination DMAConfig = DMA Enable,
-	Memory Write, 8-Bit Transfers, 1-D DMA, Flow - Stop, IOC */
-	W[P1+OFFSET_(MDMA_D0_CONFIG)] = R4;
-
-WAIT_DMA_DONE:
-	p0.h = hi(MDMA_D0_IRQ_STATUS);
-	p0.l = lo(MDMA_D0_IRQ_STATUS);
-	R0 = W[P0](Z);
-	CC = BITTST(R0, 0);
-	if ! CC jump WAIT_DMA_DONE
-
-	R0 = 0x1;
-	W[P1+OFFSET_(MDMA_D0_IRQ_STATUS)] = R0;	/* Write 1 to clear DMA interrupt */
-
-	/* Initialize BSS Section with 0 s */
-	p1.l = ___bss_start;
-	p1.h = ___bss_start;
-	p2.l = _end;
-	p2.h = _end;
-	r1 = p1;
-	r2 = p2;
-	r3 = r2 - r1;
-	r3 = r3 >> 2;
-	p3 = r3;
-	lsetup (_clear_bss, _clear_bss_end ) lc1 = p3;
-	CC = p2<=p1;
-	if CC jump _clear_bss_skip;
-	r0 = 0;
-_clear_bss:
-_clear_bss_end:
- 	[p1++] = r0;
-_clear_bss_skip:
-
-#if defined(CONFIG_BF537)&&defined(CONFIG_POST)
-        p0.l = post_flag;
-        p0.h = post_flag;
-        r0   = r7;
-        [p0] = r0;
-#endif
-
-	p0.l = _blackfin_start_barebox;
-	p0.h = _blackfin_start_barebox;
-	jump (p0);
-
-reset_start:
-	p0.h = hi(WDOG_CNT);
-	p0.l = lo(WDOG_CNT);
-	r0 = 0x0010;
-	w[p0] = r0;
-	p0.h = hi(WDOG_CTL);
-	p0.l = lo(WDOG_CTL);
-	r0 = 0x0000;
-	w[p0] = r0;
-reset_wait:
-	jump reset_wait;
-
-reset_end: nop;
-
-_exit:
-	jump.s	_exit;
-get_pc:
-	r0 = rets;
-	rts;
diff --git a/arch/blackfin/include/asm/bitops.h b/arch/blackfin/include/asm/bitops.h
deleted file mode 100644
index e77ab83202..0000000000
--- a/arch/blackfin/include/asm/bitops.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- *
- */
-
-#ifndef _ASM_BITOPS_H_
-#define _ASM_BITOPS_H_
-
-#include <asm-generic/bitops/__ffs.h>
-#include <asm-generic/bitops/__fls.h>
-#include <asm-generic/bitops/ffs.h>
-#include <asm-generic/bitops/fls.h>
-#include <asm-generic/bitops/ffz.h>
-#include <asm-generic/bitops/hweight.h>
-#include <asm-generic/bitops/fls64.h>
-#include <asm-generic/bitops/find.h>
-#include <asm-generic/bitops/ops.h>
-
-#define set_bit(x, y)			__set_bit(x, y)
-#define clear_bit(x, y)			__clear_bit(x, y)
-#define change_bit(x, y)		__change_bit(x, y)
-#define test_and_set_bit(x, y)		__test_and_set_bit(x, y)
-#define test_and_clear_bit(x, y)	__test_and_clear_bit(x, y)
-#define test_and_change_bit(x, y)	__test_and_change_bit(x, y)
-
-#endif /* _ASM_BITOPS_H_ */
diff --git a/arch/blackfin/include/asm/bitsperlong.h b/arch/blackfin/include/asm/bitsperlong.h
deleted file mode 100644
index 6dc0bb0c13..0000000000
--- a/arch/blackfin/include/asm/bitsperlong.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/bitsperlong.h>
diff --git a/arch/blackfin/include/asm/blackfin.h b/arch/blackfin/include/asm/blackfin.h
deleted file mode 100644
index 5f3285fd05..0000000000
--- a/arch/blackfin/include/asm/blackfin.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * barebox - blackfin.h
- *
- * Copyright (c) 2005 blackfin.uclinux.org
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef _BLACKFIN_H_
-#define _BLACKFIN_H_
-
-#define lo(con32)		((con32) & 0xFFFF)
-#define hi(con32)		(((con32) >> 16) & 0xFFFF)
-
-#ifdef CONFIG_BF561
-
-#include <asm/cpu/defBF561.h>
-#include <asm/cpu/defBF561_extn.h>
-#ifndef __ASSEMBLY__
-#include <asm/cpu/cdef_LPBlackfin.h>
-#include <asm/cpu/cdefBF561.h>
-#endif
-
-#endif
-
-#ifndef __ASSEMBLY__
-/* Get the System clock */
-ulong get_sclk(void);
-#endif
-
-#if ( CONFIG_CLKIN_HALF == 0 )
-#define CONFIG_VCO_HZ           ( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT )
-#else
-#define CONFIG_VCO_HZ           (( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 )
-#endif
-
-#if (CONFIG_PLL_BYPASS == 0)
-#define CONFIG_CCLK_HZ          ( CONFIG_VCO_HZ / CONFIG_CCLK_DIV )
-#define CONFIG_SCLK_HZ          ( CONFIG_VCO_HZ / CONFIG_SCLK_DIV )
-#else
-#define CONFIG_CCLK_HZ          CONFIG_CLKIN_HZ
-#define CONFIG_SCLK_HZ          CONFIG_CLKIN_HZ
-#endif
-
-#if (CONFIG_CCLK_DIV == 1)
-#define CONFIG_CCLK_ACT_DIV   CCLK_DIV1
-#endif
-#if (CONFIG_CCLK_DIV == 2)
-#define CONFIG_CCLK_ACT_DIV   CCLK_DIV2
-#endif
-#if (CONFIG_CCLK_DIV == 4)
-#define CONFIG_CCLK_ACT_DIV   CCLK_DIV4
-#endif
-#if (CONFIG_CCLK_DIV == 8)
-#define CONFIG_CCLK_ACT_DIV   CCLK_DIV8
-#endif
-#ifndef CONFIG_CCLK_ACT_DIV
-#define CONFIG_CCLK_ACT_DIV   CONFIG_CCLK_DIV_not_defined_properly
-#endif
-
-#endif
-
diff --git a/arch/blackfin/include/asm/blackfin_defs.h b/arch/blackfin/include/asm/blackfin_defs.h
deleted file mode 100644
index c69722cb07..0000000000
--- a/arch/blackfin/include/asm/blackfin_defs.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * barebox - blackfin_defs.h
- *
- * Copyright (c) 2005 blackfin.uclinux.org
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __BLACKFIN_DEFS_H__
-#define __BLACKFIN_DEFS_H__
-
-#define TS_MAGICKEY		0x5a5a5a5a
-#define TASK_STATE		0
-#define TASK_FLAGS		4
-#define TASK_PTRACE		24
-#define TASK_BLOCKED		636
-#define TASK_COUNTER		32
-#define TASK_SIGPENDING		8
-#define TASK_NEEDRESCHED	20
-#define TASK_THREAD		600
-#define TASK_MM			44
-#define TASK_ACTIVE_MM		80
-#define THREAD_KSP		0
-#define THREAD_USP		4
-#define THREAD_SR		8
-#define THREAD_ESP0		12
-#define THREAD_PC		16
-#define PT_ORIG_R0		208
-#define PT_R0			204
-#define PT_R1			200
-#define PT_R2			196
-#define PT_R3			192
-#define PT_R4			188
-#define PT_R5			184
-#define PT_R6			180
-#define PT_R7			176
-#define PT_P0			172
-#define PT_P1			168
-#define PT_P2			164
-#define PT_P3			160
-#define PT_P4			156
-#define PT_P5			152
-#define PT_A0w			72
-#define PT_A1w			64
-#define PT_A0x			76
-#define PT_A1x			68
-#define PT_RETS			28
-#define PT_RESERVED		32
-#define PT_ASTAT		36
-#define PT_SEQSTAT		8
-#define PT_PC			24
-#define PT_IPEND		0
-#define PT_USP			144
-#define PT_FP			148
-#define PT_SYSCFG		4
-#define IRQ_HANDLER		0
-#define IRQ_DEVID		8
-#define IRQ_NEXT		16
-#define STAT_IRQ		5148
-#define SIGSEGV			11
-#define SEGV_MAPERR		196609
-#define SIGTRAP			5
-#define PT_PTRACED		1
-#define PT_TRACESYS		2
-#define PT_DTRACE		4
-
-#endif
diff --git a/arch/blackfin/include/asm/byteorder.h b/arch/blackfin/include/asm/byteorder.h
deleted file mode 100644
index 6aa888ba45..0000000000
--- a/arch/blackfin/include/asm/byteorder.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * barebox -  byteorder.h
- *
- * Copyright (c) 2005 blackfin.uclinux.org
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@xxxxxxx.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef _BLACKFIN_BYTEORDER_H
-#define _BLACKFIN_BYTEORDER_H
-
-#include <asm/types.h>
-
-#if defined(__GNUC__) && !defined(__STRICT_ANSI__) || defined(__KERNEL__)
-#  define __BYTEORDER_HAS_U64__
-#  define __SWAB_64_THRU_32__
-#endif
-
-#include <linux/byteorder/little_endian.h>
-
-#endif
diff --git a/arch/blackfin/include/asm/common.h b/arch/blackfin/include/asm/common.h
deleted file mode 100644
index 443adf7270..0000000000
--- a/arch/blackfin/include/asm/common.h
+++ /dev/null
@@ -1 +0,0 @@
-/* nothing special */
diff --git a/arch/blackfin/include/asm/cplb.h b/arch/blackfin/include/asm/cplb.h
deleted file mode 100644
index 7715f645de..0000000000
--- a/arch/blackfin/include/asm/cplb.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/************************************************************************
- *
- * cplb.h
- *
- * (c) Copyright 2002-2003 Analog Devices, Inc.  All rights reserved.
- *
- ************************************************************************/
-
-/* Defines necessary for cplb initialisation routines. */
-
-#ifndef _CPLB_H
-#define _CPLB_H
-
-#define CPLB_ENABLE_ICACHE_P	0
-#define CPLB_ENABLE_DCACHE_P	1
-#define CPLB_ENABLE_DCACHE2_P	2
-#define CPLB_ENABLE_CPLBS_P	3	/* Deprecated!*/
-#define CPLB_ENABLE_ICPLBS_P	4
-#define CPLB_ENABLE_DCPLBS_P	5
-
-#define CPLB_ENABLE_ICACHE	(1<<CPLB_ENABLE_ICACHE_P)
-#define CPLB_ENABLE_DCACHE	(1<<CPLB_ENABLE_DCACHE_P)
-#define CPLB_ENABLE_DCACHE2	(1<<CPLB_ENABLE_DCACHE2_P)
-#define CPLB_ENABLE_CPLBS	(1<<CPLB_ENABLE_CPLBS_P)
-#define CPLB_ENABLE_ICPLBS	(1<<CPLB_ENABLE_ICPLBS_P)
-#define CPLB_ENABLE_DCPLBS	(1<<CPLB_ENABLE_DCPLBS_P)
-#define CPLB_ENABLE_ANY_CPLBS	CPLB_ENABLE_CPLBS | \
-				CPLB_ENABLE_ICPLBS | \
-				CPLB_ENABLE_DCPLBS
-
-#define CPLB_RELOADED		0x0000
-#define CPLB_NO_UNLOCKED	0x0001
-#define CPLB_NO_ADDR_MATCH	0x0002
-#define CPLB_PROT_VIOL		0x0003
-
-#define CPLB_DEF_CACHE		CPLB_L1_CHBL | CPLB_WT
-#define CPLB_CACHE_ENABLED	CPLB_L1_CHBL | CPLB_DIRTY
-
-#define CPLB_ALL_ACCESS	CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR
-
-#define CPLB_I_PAGE_MGMT	CPLB_LOCK | CPLB_VALID
-#define CPLB_D_PAGE_MGMT	CPLB_LOCK | CPLB_ALL_ACCESS | CPLB_VALID
-#define CPLB_DNOCACHE		CPLB_ALL_ACCESS | CPLB_VALID
-#define CPLB_DDOCACHE		CPLB_DNOCACHE | CPLB_DEF_CACHE
-#define CPLB_INOCACHE   	CPLB_USER_RD | CPLB_VALID
-#define CPLB_IDOCACHE   	CPLB_INOCACHE | CPLB_L1_CHBL
-
-#endif /* _CPLB_H */
diff --git a/arch/blackfin/include/asm/cpu.h b/arch/blackfin/include/asm/cpu.h
deleted file mode 100644
index 56ec8b9efd..0000000000
--- a/arch/blackfin/include/asm/cpu.h
+++ /dev/null
@@ -1,70 +0,0 @@
-
-/*
- *  barebox - cpu.h
- *
- *  Copyright (c) 2005 blackfin.uclinux.org
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef _CPU_H_
-#define _CPU_H_
-
-#include <asm/ptrace.h>
-
-#if defined(CONFIG_BF561)
-#define page_descriptor_table_size (CONFIG_MEM_SIZE/4 + 1 + 4) /* SDRAM +L1 + ASYNC_Memory */
-#else
-#define page_descriptor_table_size (CONFIG_MEM_SIZE/4 + 2) /* SDRAM + L1 + ASYNC_Memory */
-#endif
-
-/* we cover everything with 4 meg pages, and need an extra for L1 */
-extern unsigned int icplb_table[page_descriptor_table_size][2] ;
-extern unsigned int dcplb_table[page_descriptor_table_size][2] ;
-
-#define INTERNAL_IRQS (32)
-#define NUM_IRQ_NODES 16
-#define DEF_INTERRUPT_FLAGS 1
-#define MAX_TIM_LOAD	0xFFFFFFFF
-
-void blackfin_irq_panic(int reason, struct pt_regs *reg);
-extern void dump_regs(struct pt_regs *regs);
-void display_excp(void);
-void evt_nmi(void);
-void evt_exception(void);
-void trap(void);
-void evt_ivhw(void);
-void evt_rst(void);
-void evt_timer(void);
-void evt_evt7(void);
-void evt_evt8(void);
-void evt_evt9(void);
-void evt_evt10(void);
-void evt_evt11(void);
-void evt_evt12(void);
-void evt_evt13(void);
-void evt_soft_int1(void);
-void evt_system_call(void);
-
-void flush_data_cache(void);
-void flush_instruction_cache(void);
-void dcache_disable(void);
-void icache_enable(void);
-void dcache_enable(void);
-int icache_status(void);
-void icache_disable (void);
-int dcache_status(void);
-
-#endif
diff --git a/arch/blackfin/include/asm/cpu/cdefBF531.h b/arch/blackfin/include/asm/cpu/cdefBF531.h
deleted file mode 100644
index 68d841d185..0000000000
--- a/arch/blackfin/include/asm/cpu/cdefBF531.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * cdefBF531.h
- *
- * This file is subject to the terms and conditions of the GNU Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Non-GPL License also available as part of VisualDSP++
- *
- * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html
- *
- * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved
- *
- * This file under source code control, please send bugs or changes to:
- * dsptools.support@xxxxxxxxxx
- *
- */
-
-#ifndef _CDEFBF531_H
-#define _CDEFBF531_H
-
-#include <cdefBF532.h>
-
-#endif	/* _CDEFBF531_H */
diff --git a/arch/blackfin/include/asm/cpu/cdefBF532.h b/arch/blackfin/include/asm/cpu/cdefBF532.h
deleted file mode 100644
index a4d422f765..0000000000
--- a/arch/blackfin/include/asm/cpu/cdefBF532.h
+++ /dev/null
@@ -1,398 +0,0 @@
-/*
- * cdefBF532.h
- *
- * This file is subject to the terms and conditions of the GNU Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Non-GPL License also available as part of VisualDSP++
- *
- * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html
- *
- * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved
- *
- * This file under source code control, please send bugs or changes to:
- * dsptools.support@xxxxxxxxxx
- *
- */
-
-#ifndef _CDEF_BF532_H
-#define _CDEF_BF532_H
-
-/*
- * #if !defined(__ADSPLPBLACKFIN__)
- * #warning cdefBF532.h should only be included for 532 compatible chips.
- * #endif
- */
-
-/* include all Core registers and bit definitions */
-#include <asm/cpu/defBF532.h>
-
-/* include core specific register pointer definitions */
-#include <asm/cpu/cdef_LPBlackfin.h>
-
-/* Clock and System Control (0xFFC0 0400-0xFFC0 07FF) */
-#define pPLL_CTL ((volatile unsigned short *)PLL_CTL)
-#define pPLL_STAT ((volatile unsigned short *)PLL_STAT)
-#define pPLL_LOCKCNT ((volatile unsigned short *)PLL_LOCKCNT)
-#define pCHIPID ((volatile unsigned long *)CHIPID)
-#define pSWRST ((volatile unsigned short *)SWRST)
-#define pSYSCR ((volatile unsigned short *)SYSCR)
-#define pPLL_DIV ((volatile unsigned short *)PLL_DIV)
-#define pVR_CTL ((volatile unsigned short *)VR_CTL)
-
-/* System Interrupt Controller (0xFFC0 0C00-0xFFC0 0FFF) */
-#define pSIC_IAR0 ((volatile unsigned long *)SIC_IAR0)
-#define pSIC_IAR1 ((volatile unsigned long *)SIC_IAR1)
-#define pSIC_IAR2 ((volatile unsigned long *)SIC_IAR2)
-#define pSIC_IAR3 ((volatile unsigned long *)SIC_IAR3)
-#define pSIC_IMASK ((volatile unsigned long *)SIC_IMASK)
-#define pSIC_ISR ((volatile unsigned long *)SIC_ISR)
-#define pSIC_IWR ((volatile unsigned long *)SIC_IWR)
-
-/* Watchdog Timer (0xFFC0 1000-0xFFC0 13FF) */
-#define pWDOG_CTL ((volatile unsigned short *)WDOG_CTL)
-#define pWDOG_CNT ((volatile unsigned long *)WDOG_CNT)
-#define pWDOG_STAT ((volatile unsigned long *)WDOG_STAT)
-
-/* Real Time Clock (0xFFC0 1400-0xFFC0 17FF) */
-#define pRTC_STAT ((volatile unsigned long *)RTC_STAT)
-#define pRTC_ICTL ((volatile unsigned short *)RTC_ICTL)
-#define pRTC_ISTAT ((volatile unsigned short *)RTC_ISTAT)
-#define pRTC_SWCNT ((volatile unsigned short *)RTC_SWCNT)
-#define pRTC_ALARM ((volatile unsigned long *)RTC_ALARM)
-#define pRTC_FAST ((volatile unsigned short *)RTC_FAST)
-#define pRTC_PREN ((volatile unsigned short *)RTC_PREN)
-
-/* General Purpose IO (0xFFC0 2400-0xFFC0 27FF) */
-#define pFIO_DIR ((volatile unsigned short *)FIO_DIR)
-#define pFIO_FLAG_C ((volatile unsigned short *)FIO_FLAG_C)
-#define pFIO_FLAG_S ((volatile unsigned short *)FIO_FLAG_S)
-#define pFIO_MASKA_C ((volatile unsigned short *)FIO_MASKA_C)
-#define pFIO_MASKA_S ((volatile unsigned short *)FIO_MASKA_S)
-#define pFIO_MASKB_C ((volatile unsigned short *)FIO_MASKB_C)
-#define pFIO_MASKB_S ((volatile unsigned short *)FIO_MASKB_S)
-#define pFIO_POLAR ((volatile unsigned short *)FIO_POLAR)
-#define pFIO_EDGE ((volatile unsigned short *)FIO_EDGE)
-#define pFIO_BOTH ((volatile unsigned short *)FIO_BOTH)
-#define pFIO_INEN ((volatile unsigned short *)FIO_INEN)
-#define pFIO_FLAG_D ((volatile unsigned short *)FIO_FLAG_D)
-#define pFIO_FLAG_T ((volatile unsigned short *)FIO_FLAG_T)
-#define pFIO_MASKA_D ((volatile unsigned short *)FIO_MASKA_D)
-#define pFIO_MASKA_T ((volatile unsigned short *)FIO_MASKA_T)
-#define pFIO_MASKB_D ((volatile unsigned short *)FIO_MASKB_D)
-#define pFIO_MASKB_T ((volatile unsigned short *)FIO_MASKB_T)
-
-/* DMA Test Registers */
-#define pDMA_CCOMP	((volatile unsigned long *)DMA_CCOMP)
-#define	pDMA_ACOMP	((volatile unsigned long *)DMA_ACOMP)
-#define	pDMA_MISR	((volatile unsigned long *)DMA_MISR)
-#define	pDMA_TCPER	((volatile unsigned short *)DMA_TCPER)
-#define	pDMA_TCCNT	((volatile unsigned short *)DMA_TCCNT)
-#define	pDMA_TMODE	((volatile unsigned short *)DMA_TMODE)
-#define	pDMA_TMCHAN	((volatile unsigned short *)DMA_TMCHAN)
-#define	pDMA_TMSTAT	((volatile unsigned short *)DMA_TMSTAT)
-#define	pDMA_TMBD	((volatile unsigned short *)DMA_TMBD)
-#define	pDMA_TMM0D	((volatile unsigned short *)DMA_TMM0D)
-#define	pDMA_TMM1D	((volatile unsigned short *)DMA_TMM1D)
-#define pDMA_TMMA	((volatile void **)DMA_TMMA)
-
-/* DMA Controller */
-#define pDMA0_CONFIG ((volatile unsigned short *)DMA0_CONFIG)
-#define pDMA0_NEXT_DESC_PTR ((volatile void **)DMA0_NEXT_DESC_PTR)
-#define pDMA0_START_ADDR ((volatile void **)DMA0_START_ADDR)
-#define pDMA0_X_COUNT ((volatile unsigned short *)DMA0_X_COUNT)
-#define pDMA0_Y_COUNT ((volatile unsigned short *)DMA0_Y_COUNT)
-#define pDMA0_X_MODIFY ((volatile signed short *)DMA0_X_MODIFY)
-#define pDMA0_Y_MODIFY ((volatile signed short *)DMA0_Y_MODIFY)
-#define pDMA0_CURR_DESC_PTR ((volatile void **)DMA0_CURR_DESC_PTR)
-#define pDMA0_CURR_ADDR ((volatile void **)DMA0_CURR_ADDR)
-#define pDMA0_CURR_X_COUNT ((volatile unsigned short *)DMA0_CURR_X_COUNT)
-#define pDMA0_CURR_Y_COUNT ((volatile unsigned short *)DMA0_CURR_Y_COUNT)
-#define pDMA0_IRQ_STATUS ((volatile unsigned short *)DMA0_IRQ_STATUS)
-#define pDMA0_PERIPHERAL_MAP ((volatile unsigned short *)DMA0_PERIPHERAL_MAP)
-
-#define pDMA1_CONFIG ((volatile unsigned short *)DMA1_CONFIG)
-#define pDMA1_NEXT_DESC_PTR ((volatile void **)DMA1_NEXT_DESC_PTR)
-#define pDMA1_START_ADDR ((volatile void **)DMA1_START_ADDR)
-#define pDMA1_X_COUNT ((volatile unsigned short *)DMA1_X_COUNT)
-#define pDMA1_Y_COUNT ((volatile unsigned short *)DMA1_Y_COUNT)
-#define pDMA1_X_MODIFY ((volatile signed short *)DMA1_X_MODIFY)
-#define pDMA1_Y_MODIFY ((volatile signed short *)DMA1_Y_MODIFY)
-#define pDMA1_CURR_DESC_PTR ((volatile void **)DMA1_CURR_DESC_PTR)
-#define pDMA1_CURR_ADDR ((volatile void **)DMA1_CURR_ADDR)
-#define pDMA1_CURR_X_COUNT ((volatile unsigned short *)DMA1_CURR_X_COUNT)
-#define pDMA1_CURR_Y_COUNT ((volatile unsigned short *)DMA1_CURR_Y_COUNT)
-#define pDMA1_IRQ_STATUS ((volatile unsigned short *)DMA1_IRQ_STATUS)
-#define pDMA1_PERIPHERAL_MAP ((volatile unsigned short *)DMA1_PERIPHERAL_MAP)
-
-#define pDMA2_CONFIG ((volatile unsigned short *)DMA2_CONFIG)
-#define pDMA2_NEXT_DESC_PTR ((volatile void **)DMA2_NEXT_DESC_PTR)
-#define pDMA2_START_ADDR ((volatile void **)DMA2_START_ADDR)
-#define pDMA2_X_COUNT ((volatile unsigned short *)DMA2_X_COUNT)
-#define pDMA2_Y_COUNT ((volatile unsigned short *)DMA2_Y_COUNT)
-#define pDMA2_X_MODIFY ((volatile signed short *)DMA2_X_MODIFY)
-#define pDMA2_Y_MODIFY ((volatile signed short *)DMA2_Y_MODIFY)
-#define pDMA2_CURR_DESC_PTR ((volatile void **)DMA2_CURR_DESC_PTR)
-#define pDMA2_CURR_ADDR ((volatile void **)DMA2_CURR_ADDR)
-#define pDMA2_CURR_X_COUNT ((volatile unsigned short *)DMA2_CURR_X_COUNT)
-#define pDMA2_CURR_Y_COUNT ((volatile unsigned short *)DMA2_CURR_Y_COUNT)
-#define pDMA2_IRQ_STATUS ((volatile unsigned short *)DMA2_IRQ_STATUS)
-#define pDMA2_PERIPHERAL_MAP ((volatile unsigned short *)DMA2_PERIPHERAL_MAP)
-
-#define pDMA3_CONFIG ((volatile unsigned short *)DMA3_CONFIG)
-#define pDMA3_NEXT_DESC_PTR ((volatile void **)DMA3_NEXT_DESC_PTR)
-#define pDMA3_START_ADDR ((volatile void **)DMA3_START_ADDR)
-#define pDMA3_X_COUNT ((volatile unsigned short *)DMA3_X_COUNT)
-#define pDMA3_Y_COUNT ((volatile unsigned short *)DMA3_Y_COUNT)
-#define pDMA3_X_MODIFY ((volatile signed short *)DMA3_X_MODIFY)
-#define pDMA3_Y_MODIFY ((volatile signed short *)DMA3_Y_MODIFY)
-#define pDMA3_CURR_DESC_PTR ((volatile void **)DMA3_CURR_DESC_PTR)
-#define pDMA3_CURR_ADDR ((volatile void **)DMA3_CURR_ADDR)
-#define pDMA3_CURR_X_COUNT ((volatile unsigned short *)DMA3_CURR_X_COUNT)
-#define pDMA3_CURR_Y_COUNT ((volatile unsigned short *)DMA3_CURR_Y_COUNT)
-#define pDMA3_IRQ_STATUS ((volatile unsigned short *)DMA3_IRQ_STATUS)
-#define pDMA3_PERIPHERAL_MAP ((volatile unsigned short *)DMA3_PERIPHERAL_MAP)
-
-#define pDMA4_CONFIG ((volatile unsigned short *)DMA4_CONFIG)
-#define pDMA4_NEXT_DESC_PTR ((volatile void **)DMA4_NEXT_DESC_PTR)
-#define pDMA4_START_ADDR ((volatile void **)DMA4_START_ADDR)
-#define pDMA4_X_COUNT ((volatile unsigned short *)DMA4_X_COUNT)
-#define pDMA4_Y_COUNT ((volatile unsigned short *)DMA4_Y_COUNT)
-#define pDMA4_X_MODIFY ((volatile signed short *)DMA4_X_MODIFY)
-#define pDMA4_Y_MODIFY ((volatile signed short *)DMA4_Y_MODIFY)
-#define pDMA4_CURR_DESC_PTR ((volatile void **)DMA4_CURR_DESC_PTR)
-#define pDMA4_CURR_ADDR ((volatile void **)DMA4_CURR_ADDR)
-#define pDMA4_CURR_X_COUNT ((volatile unsigned short *)DMA4_CURR_X_COUNT)
-#define pDMA4_CURR_Y_COUNT ((volatile unsigned short *)DMA4_CURR_Y_COUNT)
-#define pDMA4_IRQ_STATUS ((volatile unsigned short *)DMA4_IRQ_STATUS)
-#define pDMA4_PERIPHERAL_MAP ((volatile unsigned short *)DMA4_PERIPHERAL_MAP)
-
-#define pDMA5_CONFIG ((volatile unsigned short *)DMA5_CONFIG)
-#define pDMA5_NEXT_DESC_PTR ((volatile void **)DMA5_NEXT_DESC_PTR)
-#define pDMA5_START_ADDR ((volatile void **)DMA5_START_ADDR)
-#define pDMA5_X_COUNT ((volatile unsigned short *)DMA5_X_COUNT)
-#define pDMA5_Y_COUNT ((volatile unsigned short *)DMA5_Y_COUNT)
-#define pDMA5_X_MODIFY ((volatile signed short *)DMA5_X_MODIFY)
-#define pDMA5_Y_MODIFY ((volatile signed short *)DMA5_Y_MODIFY)
-#define pDMA5_CURR_DESC_PTR ((volatile void **)DMA5_CURR_DESC_PTR)
-#define pDMA5_CURR_ADDR ((volatile void **)DMA5_CURR_ADDR)
-#define pDMA5_CURR_X_COUNT ((volatile unsigned short *)DMA5_CURR_X_COUNT)
-#define pDMA5_CURR_Y_COUNT ((volatile unsigned short *)DMA5_CURR_Y_COUNT)
-#define pDMA5_IRQ_STATUS ((volatile unsigned short *)DMA5_IRQ_STATUS)
-#define pDMA5_PERIPHERAL_MAP ((volatile unsigned short *)DMA5_PERIPHERAL_MAP)
-
-#define pDMA6_CONFIG ((volatile unsigned short *)DMA6_CONFIG)
-#define pDMA6_NEXT_DESC_PTR ((volatile void **)DMA6_NEXT_DESC_PTR)
-#define pDMA6_START_ADDR ((volatile void **)DMA6_START_ADDR)
-#define pDMA6_X_COUNT ((volatile unsigned short *)DMA6_X_COUNT)
-#define pDMA6_Y_COUNT ((volatile unsigned short *)DMA6_Y_COUNT)
-#define pDMA6_X_MODIFY ((volatile signed short *)DMA6_X_MODIFY)
-#define pDMA6_Y_MODIFY ((volatile signed short *)DMA6_Y_MODIFY)
-#define pDMA6_CURR_DESC_PTR ((volatile void **)DMA6_CURR_DESC_PTR)
-#define pDMA6_CURR_ADDR ((volatile void **)DMA6_CURR_ADDR)
-#define pDMA6_CURR_X_COUNT ((volatile unsigned short *)DMA6_CURR_X_COUNT)
-#define pDMA6_CURR_Y_COUNT ((volatile unsigned short *)DMA6_CURR_Y_COUNT)
-#define pDMA6_IRQ_STATUS ((volatile unsigned short *)DMA6_IRQ_STATUS)
-#define pDMA6_PERIPHERAL_MAP ((volatile unsigned short *)DMA6_PERIPHERAL_MAP)
-
-#define pDMA7_CONFIG ((volatile unsigned short *)DMA7_CONFIG)
-#define pDMA7_NEXT_DESC_PTR ((volatile void **)DMA7_NEXT_DESC_PTR)
-#define pDMA7_START_ADDR ((volatile void **)DMA7_START_ADDR)
-#define pDMA7_X_COUNT ((volatile unsigned short *)DMA7_X_COUNT)
-#define pDMA7_Y_COUNT ((volatile unsigned short *)DMA7_Y_COUNT)
-#define pDMA7_X_MODIFY ((volatile signed short *)DMA7_X_MODIFY)
-#define pDMA7_Y_MODIFY ((volatile signed short *)DMA7_Y_MODIFY)
-#define pDMA7_CURR_DESC_PTR ((volatile void **)DMA7_CURR_DESC_PTR)
-#define pDMA7_CURR_ADDR ((volatile void **)DMA7_CURR_ADDR)
-#define pDMA7_CURR_X_COUNT ((volatile unsigned short *)DMA7_CURR_X_COUNT)
-#define pDMA7_CURR_Y_COUNT ((volatile unsigned short *)DMA7_CURR_Y_COUNT)
-#define pDMA7_IRQ_STATUS ((volatile unsigned short *)DMA7_IRQ_STATUS)
-#define pDMA7_PERIPHERAL_MAP ((volatile unsigned short *)DMA7_PERIPHERAL_MAP)
-
-#define pMDMA_D1_CONFIG ((volatile unsigned short *)MDMA_D1_CONFIG)
-#define pMDMA_D1_NEXT_DESC_PTR ((volatile void **)MDMA_D1_NEXT_DESC_PTR)
-#define pMDMA_D1_START_ADDR ((volatile void **)MDMA_D1_START_ADDR)
-#define pMDMA_D1_X_COUNT ((volatile unsigned short *)MDMA_D1_X_COUNT)
-#define pMDMA_D1_Y_COUNT ((volatile unsigned short *)MDMA_D1_Y_COUNT)
-#define pMDMA_D1_X_MODIFY ((volatile signed short *)MDMA_D1_X_MODIFY)
-#define pMDMA_D1_Y_MODIFY ((volatile signed short *)MDMA_D1_Y_MODIFY)
-#define pMDMA_D1_CURR_DESC_PTR ((volatile void **)MDMA_D1_CURR_DESC_PTR)
-#define pMDMA_D1_CURR_ADDR ((volatile void **)MDMA_D1_CURR_ADDR)
-#define pMDMA_D1_CURR_X_COUNT ((volatile unsigned short *)MDMA_D1_CURR_X_COUNT)
-#define pMDMA_D1_CURR_Y_COUNT ((volatile unsigned short *)MDMA_D1_CURR_Y_COUNT)
-#define pMDMA_D1_IRQ_STATUS ((volatile unsigned short *)MDMA_D1_IRQ_STATUS)
-#define pMDMA_D1_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_D1_PERIPHERAL_MAP)
-
-#define pMDMA_S1_CONFIG ((volatile unsigned short *)MDMA_S1_CONFIG)
-#define pMDMA_S1_NEXT_DESC_PTR ((volatile void **)MDMA_S1_NEXT_DESC_PTR)
-#define pMDMA_S1_START_ADDR ((volatile void **)MDMA_S1_START_ADDR)
-#define pMDMA_S1_X_COUNT ((volatile unsigned short *)MDMA_S1_X_COUNT)
-#define pMDMA_S1_Y_COUNT ((volatile unsigned short *)MDMA_S1_Y_COUNT)
-#define pMDMA_S1_X_MODIFY ((volatile signed short *)MDMA_S1_X_MODIFY)
-#define pMDMA_S1_Y_MODIFY ((volatile signed short *)MDMA_S1_Y_MODIFY)
-#define pMDMA_S1_CURR_DESC_PTR ((volatile void **)MDMA_S1_CURR_DESC_PTR)
-#define pMDMA_S1_CURR_ADDR ((volatile void **)MDMA_S1_CURR_ADDR)
-#define pMDMA_S1_CURR_X_COUNT ((volatile unsigned short *)MDMA_S1_CURR_X_COUNT)
-#define pMDMA_S1_CURR_Y_COUNT ((volatile unsigned short *)MDMA_S1_CURR_Y_COUNT)
-#define pMDMA_S1_IRQ_STATUS ((volatile unsigned short *)MDMA_S1_IRQ_STATUS)
-#define pMDMA_S1_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_S1_PERIPHERAL_MAP)
-
-#define pMDMA_D0_CONFIG ((volatile unsigned short *)MDMA_D0_CONFIG)
-#define pMDMA_D0_NEXT_DESC_PTR ((volatile void **)MDMA_D0_NEXT_DESC_PTR)
-#define pMDMA_D0_START_ADDR ((volatile void **)MDMA_D0_START_ADDR)
-#define pMDMA_D0_X_COUNT ((volatile unsigned short *)MDMA_D0_X_COUNT)
-#define pMDMA_D0_Y_COUNT ((volatile unsigned short *)MDMA_D0_Y_COUNT)
-#define pMDMA_D0_X_MODIFY ((volatile signed short *)MDMA_D0_X_MODIFY)
-#define pMDMA_D0_Y_MODIFY ((volatile signed short *)MDMA_D0_Y_MODIFY)
-#define pMDMA_D0_CURR_DESC_PTR ((volatile void **)MDMA_D0_CURR_DESC_PTR)
-#define pMDMA_D0_CURR_ADDR ((volatile void **)MDMA_D0_CURR_ADDR)
-#define pMDMA_D0_CURR_X_COUNT ((volatile unsigned short *)MDMA_D0_CURR_X_COUNT)
-#define pMDMA_D0_CURR_Y_COUNT ((volatile unsigned short *)MDMA_D0_CURR_Y_COUNT)
-#define pMDMA_D0_IRQ_STATUS ((volatile unsigned short *)MDMA_D0_IRQ_STATUS)
-#define pMDMA_D0_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_D0_PERIPHERAL_MAP)
-
-#define pMDMA_S0_CONFIG ((volatile unsigned short *)MDMA_S0_CONFIG)
-#define pMDMA_S0_NEXT_DESC_PTR ((volatile void **)MDMA_S0_NEXT_DESC_PTR)
-#define pMDMA_S0_START_ADDR ((volatile void **)MDMA_S0_START_ADDR)
-#define pMDMA_S0_X_COUNT ((volatile unsigned short *)MDMA_S0_X_COUNT)
-#define pMDMA_S0_Y_COUNT ((volatile unsigned short *)MDMA_S0_Y_COUNT)
-#define pMDMA_S0_X_MODIFY ((volatile signed short *)MDMA_S0_X_MODIFY)
-#define pMDMA_S0_Y_MODIFY ((volatile signed short *)MDMA_S0_Y_MODIFY)
-#define pMDMA_S0_CURR_DESC_PTR ((volatile void **)MDMA_S0_CURR_DESC_PTR)
-#define pMDMA_S0_CURR_ADDR ((volatile void **)MDMA_S0_CURR_ADDR)
-#define pMDMA_S0_CURR_X_COUNT ((volatile unsigned short *)MDMA_S0_CURR_X_COUNT)
-#define pMDMA_S0_CURR_Y_COUNT ((volatile unsigned short *)MDMA_S0_CURR_Y_COUNT)
-#define pMDMA_S0_IRQ_STATUS ((volatile unsigned short *)MDMA_S0_IRQ_STATUS)
-#define pMDMA_S0_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_S0_PERIPHERAL_MAP)
-
-/* Aysnchronous Memory Controller - External Bus Interface Unit (0xFFC0 3C00-0xFFC0 3FFF) */
-#define pEBIU_AMGCTL ((volatile unsigned short *)EBIU_AMGCTL)
-#define pEBIU_AMBCTL0 ((volatile unsigned long *)EBIU_AMBCTL0)
-#define pEBIU_AMBCTL1 ((volatile unsigned long *)EBIU_AMBCTL1)
-
-/* System Bus Interface Unit (0xFFC0 4800-0xFFC0 4FFF) */
-/* #define L1SBAR 0xFFC04840 */	/* L1 SRAM Base Address Register */
-/* #define L1CSR  0xFFC04844 */	/* L1 SRAM Control Initialization Register */
-
-/*
- * #define pDB_ACOMP ((volatile void **)DB_ACOMP)
- * #define pDB_CCOMP ((volatile unsigned long *)DB_CCOMP)
- */
-
-/* SDRAM Controller External Bus Interface Unit (0xFFC0 4C00-0xFFC0 4FFF) */
-#define pEBIU_SDGCTL ((volatile unsigned long *)EBIU_SDGCTL)
-#define pEBIU_SDRRC ((volatile unsigned short *)EBIU_SDRRC)
-#define pEBIU_SDSTAT ((volatile unsigned short *)EBIU_SDSTAT)
-#define pEBIU_SDBCTL ((volatile unsigned short *)EBIU_SDBCTL)
-
-/* UART Controller */
-#define pUART_THR ((volatile unsigned short *)UART_THR)
-#define pUART_RBR ((volatile unsigned short *)UART_RBR)
-#define pUART_DLL ((volatile unsigned short *)UART_DLL)
-#define pUART_IER ((volatile unsigned short *)UART_IER)
-#define pUART_DLH ((volatile unsigned short *)UART_DLH)
-#define pUART_IIR ((volatile unsigned short *)UART_IIR)
-#define pUART_LCR ((volatile unsigned short *)UART_LCR)
-#define pUART_MCR ((volatile unsigned short *)UART_MCR)
-#define pUART_LSR ((volatile unsigned short *)UART_LSR)
-
-/*
- * #define UART_MSR
- */
-#define pUART_SCR ((volatile unsigned short *)UART_SCR)
-#define pUART_GCTL ((volatile unsigned short *)UART_GCTL)
-
-/* SPI Controller */
-#define pSPI_CTL ((volatile unsigned short *)SPI_CTL)
-#define pSPI_FLG ((volatile unsigned short *)SPI_FLG)
-#define pSPI_STAT ((volatile unsigned short *)SPI_STAT)
-#define pSPI_TDBR ((volatile unsigned short *)SPI_TDBR)
-#define pSPI_RDBR ((volatile unsigned short *)SPI_RDBR)
-#define pSPI_BAUD ((volatile unsigned short *)SPI_BAUD)
-#define pSPI_SHADOW ((volatile unsigned short *)SPI_SHADOW)
-
-/* TIMER 0, 1, 2 Registers */
-#define pTIMER0_CONFIG ((volatile unsigned short *)TIMER0_CONFIG)
-#define pTIMER0_COUNTER ((volatile unsigned long *)TIMER0_COUNTER)
-#define pTIMER0_PERIOD ((volatile unsigned long *)TIMER0_PERIOD)
-#define pTIMER0_WIDTH ((volatile unsigned long *)TIMER0_WIDTH)
-
-#define pTIMER1_CONFIG ((volatile unsigned short *)TIMER1_CONFIG)
-#define pTIMER1_COUNTER ((volatile unsigned long *)TIMER1_COUNTER)
-#define pTIMER1_PERIOD ((volatile unsigned long *)TIMER1_PERIOD)
-#define pTIMER1_WIDTH ((volatile unsigned long *)TIMER1_WIDTH)
-
-#define pTIMER2_CONFIG ((volatile unsigned short *)TIMER2_CONFIG)
-#define pTIMER2_COUNTER ((volatile unsigned long *)TIMER2_COUNTER)
-#define pTIMER2_PERIOD ((volatile unsigned long *)TIMER2_PERIOD)
-#define pTIMER2_WIDTH ((volatile unsigned long *)TIMER2_WIDTH)
-
-#define pTIMER_ENABLE ((volatile unsigned short *)TIMER_ENABLE)
-#define pTIMER_DISABLE ((volatile unsigned short *)TIMER_DISABLE)
-#define pTIMER_STATUS ((volatile unsigned short *)TIMER_STATUS)
-
-/* SPORT0 Controller */
-#define pSPORT0_TCR1 ((volatile unsigned short *)SPORT0_TCR1)
-#define pSPORT0_TCR2 ((volatile unsigned short *)SPORT0_TCR2)
-#define pSPORT0_TCLKDIV ((volatile unsigned short *)SPORT0_TCLKDIV)
-#define pSPORT0_TFSDIV ((volatile unsigned short *)SPORT0_TFSDIV)
-#define pSPORT0_TX ((volatile long *)SPORT0_TX)
-#define pSPORT0_RX ((volatile long *)SPORT0_RX)
-#define pSPORT0_TX32 ((volatile long *)SPORT0_TX)
-#define pSPORT0_RX32 ((volatile long *)SPORT0_RX)
-#define pSPORT0_TX16 ((volatile unsigned short *)SPORT0_TX)
-#define pSPORT0_RX16 ((volatile unsigned short *)SPORT0_RX)
-#define pSPORT0_RCR1 ((volatile unsigned short *)SPORT0_RCR1)
-#define pSPORT0_RCR2 ((volatile unsigned short *)SPORT0_RCR2)
-#define pSPORT0_RCLKDIV ((volatile unsigned short *)SPORT0_RCLKDIV)
-#define pSPORT0_RFSDIV ((volatile unsigned short *)SPORT0_RFSDIV)
-#define pSPORT0_STAT ((volatile unsigned short *)SPORT0_STAT)
-#define pSPORT0_CHNL ((volatile unsigned short *)SPORT0_CHNL)
-#define pSPORT0_MCMC1 ((volatile unsigned short *)SPORT0_MCMC1)
-#define pSPORT0_MCMC2 ((volatile unsigned short *)SPORT0_MCMC2)
-#define pSPORT0_MTCS0 ((volatile unsigned long *)SPORT0_MTCS0)
-#define pSPORT0_MTCS1 ((volatile unsigned long *)SPORT0_MTCS1)
-#define pSPORT0_MTCS2 ((volatile unsigned long *)SPORT0_MTCS2)
-#define pSPORT0_MTCS3 ((volatile unsigned long *)SPORT0_MTCS3)
-#define pSPORT0_MRCS0 ((volatile unsigned long *)SPORT0_MRCS0)
-#define pSPORT0_MRCS1 ((volatile unsigned long *)SPORT0_MRCS1)
-#define pSPORT0_MRCS2 ((volatile unsigned long *)SPORT0_MRCS2)
-#define pSPORT0_MRCS3 ((volatile unsigned long *)SPORT0_MRCS3)
-
-/* SPORT1 Controller */
-#define pSPORT1_TCR1 ((volatile unsigned short *)SPORT1_TCR1)
-#define pSPORT1_TCR2 ((volatile unsigned short *)SPORT1_TCR2)
-#define pSPORT1_TCLKDIV ((volatile unsigned short *)SPORT1_TCLKDIV)
-#define pSPORT1_TFSDIV ((volatile unsigned short *)SPORT1_TFSDIV)
-#define pSPORT1_TX ((volatile long *)SPORT1_TX)
-#define pSPORT1_RX ((volatile long *)SPORT1_RX)
-#define pSPORT1_TX32 ((volatile long *)SPORT1_TX)
-#define pSPORT1_RX32 ((volatile long *)SPORT1_RX)
-#define pSPORT1_TX16 ((volatile unsigned short *)SPORT1_TX)
-#define pSPORT1_RX16 ((volatile unsigned short *)SPORT1_RX)
-#define pSPORT1_RCR1 ((volatile unsigned short *)SPORT1_RCR1)
-#define pSPORT1_RCR2 ((volatile unsigned short *)SPORT1_RCR2)
-#define pSPORT1_RCLKDIV ((volatile unsigned short *)SPORT1_RCLKDIV)
-#define pSPORT1_RFSDIV ((volatile unsigned short *)SPORT1_RFSDIV)
-#define pSPORT1_STAT ((volatile unsigned short *)SPORT1_STAT)
-#define pSPORT1_CHNL ((volatile unsigned short *)SPORT1_CHNL)
-#define pSPORT1_MCMC1 ((volatile unsigned short *)SPORT1_MCMC1)
-#define pSPORT1_MCMC2 ((volatile unsigned short *)SPORT1_MCMC2)
-#define pSPORT1_MTCS0 ((volatile unsigned long *)SPORT1_MTCS0)
-#define pSPORT1_MTCS1 ((volatile unsigned long *)SPORT1_MTCS1)
-#define pSPORT1_MTCS2 ((volatile unsigned long *)SPORT1_MTCS2)
-#define pSPORT1_MTCS3 ((volatile unsigned long *)SPORT1_MTCS3)
-#define pSPORT1_MRCS0 ((volatile unsigned long *)SPORT1_MRCS0)
-#define pSPORT1_MRCS1 ((volatile unsigned long *)SPORT1_MRCS1)
-#define pSPORT1_MRCS2 ((volatile unsigned long *)SPORT1_MRCS2)
-#define pSPORT1_MRCS3 ((volatile unsigned long *)SPORT1_MRCS3)
-
-/* Parallel Peripheral Interface (PPI) */
-#define pPPI_CONTROL ((volatile unsigned short *)PPI_CONTROL)
-#define pPPI_STATUS ((volatile unsigned short *)PPI_STATUS)
-#define pPPI_DELAY ((volatile unsigned short *)PPI_DELAY)
-#define pPPI_COUNT ((volatile unsigned short *)PPI_COUNT)
-#define pPPI_FRAME ((volatile unsigned short *)PPI_FRAME)
-
-#endif	/* _CDEF_BF532_H */
diff --git a/arch/blackfin/include/asm/cpu/cdefBF533.h b/arch/blackfin/include/asm/cpu/cdefBF533.h
deleted file mode 100644
index 8c751e6073..0000000000
--- a/arch/blackfin/include/asm/cpu/cdefBF533.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * cdefBF533.h
- *
- * This file is subject to the terms and conditions of the GNU Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Non-GPL License also available as part of VisualDSP++
- *
- * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html
- *
- * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved
- *
- * This file under source code control, please send bugs or changes to:
- * dsptools.support@xxxxxxxxxx
- *
- */
-
-#ifndef _CDEFBF533_H
-#define _CDEFBF533_H
-
-#include <asm/cpu/cdefBF532.h>
-
-#endif	/* _CDEFBF533_H */
diff --git a/arch/blackfin/include/asm/cpu/cdefBF53x.h b/arch/blackfin/include/asm/cpu/cdefBF53x.h
deleted file mode 100644
index db4eaa9cf2..0000000000
--- a/arch/blackfin/include/asm/cpu/cdefBF53x.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/************************************************************************
- *
- * cdefBF53x.h
- *
- * (c) Copyright 2002-2003 Analog Devices, Inc.  All rights reserved.
- *
- ************************************************************************/
-
-#ifndef _CDEFBF53x_H
-#define _CDEFBF53x_H
-
-#if defined(__ADSPBF531__)
-	#include <asm/cpu/cdefBF531.h>
-#elif defined(__ADSPBF532__)
-	#include <asm/cpu/cdefBF532.h>
-#elif defined(__ADSPBF533__)
-	#include <asm/cpu/cdefBF533.h>
-#elif defined(__ADSPBF561__)
-	#include <asm/cpu/cdefBF561.h>
-#elif defined(__ADSPBF535__)
-	#include <asm/cpu/cdefBF535.h>
-#elif defined(__AD6532__)
-	#include <sam/cpu/cdefAD6532.h>
-#else
-	#if defined(__ADSPLPBLACKFIN__)
-		#include <asm/cpu/cdefBF532.h>
-	#else
-		#include <asm/cpu/cdefBF535.h>
-	#endif
-#endif
-
-#endif	/* _CDEFBF53x_H */
diff --git a/arch/blackfin/include/asm/cpu/cdefBF561.h b/arch/blackfin/include/asm/cpu/cdefBF561.h
deleted file mode 100644
index 9a763df04f..0000000000
--- a/arch/blackfin/include/asm/cpu/cdefBF561.h
+++ /dev/null
@@ -1,1001 +0,0 @@
-/************************************************************************
- *
- * cdefBF561.h
- *
- * (c) Copyright 2001-2004 Analog Devices, Inc.  All rights reserved.
- *
- ************************************************************************/
-
-/* C POINTERS TO SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF561 */
-
-#ifndef _CDEF_BF561_H
-#define _CDEF_BF561_H
-
-/*
- * #if !defined(__ADSPBF561__)
- * #warning cdefBF561.h should only be included for BF561 chip.
- * #endif
- */
-
-// include all Core registers and bit definitions
-#include <asm/cpu/defBF561.h>
-//#include <asm/arch-common/cdef_LPBlackfin.h>
-
-/*
- * System MMR Register Map
- */
-
-/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
-#define pPLL_CTL		(volatile unsigned short *)PLL_CTL
-#define pPLL_DIV		(volatile unsigned short *)PLL_DIV
-#define pVR_CTL			(volatile unsigned short *)VR_CTL
-#define pPLL_STAT		(volatile unsigned short *)PLL_STAT
-#define pPLL_LOCKCNT		(volatile unsigned short *)PLL_LOCKCNT
-
-/*
- * System Reset and Interrupt Controller registers for
- * core A (0xFFC0 0100-0xFFC0 01FF)
- */
-#define pSICA_SWRST		(volatile unsigned short *)SICA_SWRST
-#define pSICA_SYSCR		(volatile unsigned short *)SICA_SYSCR
-#define pSICA_RVECT		(volatile unsigned short *)SICA_RVECT
-#define pSICA_IMASK		(volatile unsigned long *)SICA_IMASK
-#define pSICA_IMASK0		(volatile unsigned long *)SICA_IMASK0
-#define pSICA_IMASK1		(volatile unsigned long *)SICA_IMASK1
-#define pSICA_IAR0		(volatile unsigned long *)SICA_IAR0
-#define pSICA_IAR1		(volatile unsigned long *)SICA_IAR1
-#define pSICA_IAR2		(volatile unsigned long *)SICA_IAR2
-#define pSICA_IAR3		(volatile unsigned long *)SICA_IAR3
-#define pSICA_IAR4		(volatile unsigned long *)SICA_IAR4
-#define pSICA_IAR5		(volatile unsigned long *)SICA_IAR5
-#define pSICA_IAR6		(volatile unsigned long *)SICA_IAR6
-#define pSICA_IAR7		(volatile unsigned long *)SICA_IAR7
-#define pSICA_ISR0		(volatile unsigned long *)SICA_ISR0
-#define pSICA_ISR1		(volatile unsigned long *)SICA_ISR1
-#define pSICA_IWR0		(volatile unsigned long *)SICA_IWR0
-#define pSICA_IWR1		(volatile unsigned long *)SICA_IWR1
-
-/*
- * System Reset and Interrupt Controller registers for
- * Core B (0xFFC0 1100-0xFFC0 11FF)
- */
-#define pSICB_SWRST		(volatile unsigned short *)SICB_SWRST
-#define pSICB_SYSCR		(volatile unsigned short *)SICB_SYSCR
-#define pSICB_RVECT		(volatile unsigned short *)SICB_RVECT
-#define pSICB_IMASK0		(volatile unsigned long *)SICB_IMASK0
-#define pSICB_IMASK1		(volatile unsigned long *)SICB_IMASK1
-#define pSICB_IAR0		(volatile unsigned long *)SICB_IAR0
-#define pSICB_IAR1		(volatile unsigned long *)SICB_IAR1
-#define pSICB_IAR2		(volatile unsigned long *)SICB_IAR2
-#define pSICB_IAR3		(volatile unsigned long *)SICB_IAR3
-#define pSICB_IAR4		(volatile unsigned long *)SICB_IAR4
-#define pSICB_IAR5		(volatile unsigned long *)SICB_IAR5
-#define pSICB_IAR6		(volatile unsigned long *)SICB_IAR6
-#define pSICB_IAR7		(volatile unsigned long *)SICB_IAR7
-#define pSICB_ISR0		(volatile unsigned long *)SICB_ISR0
-#define pSICB_ISR1		(volatile unsigned long *)SICB_ISR1
-#define pSICB_IWR0		(volatile unsigned long *)SICB_IWR0
-#define pSICB_IWR1		(volatile unsigned long *)SICB_IWR1
-
-/* Watchdog Timer registers for Core A (0xFFC0 0200-0xFFC0 02FF) */
-#define pWDOGA_CTL		(volatile unsigned short *)WDOGA_CTL
-#define pWDOGA_CNT		(volatile unsigned long *)WDOGA_CNT
-#define pWDOGA_STAT		(volatile unsigned long *)WDOGA_STAT
-
-/* Watchdog Timer registers for Core B (0xFFC0 1200-0xFFC0 12FF) */
-#define pWDOGB_CTL		(volatile unsigned short *)WDOGB_CTL
-#define pWDOGB_CNT		(volatile unsigned long *)WDOGB_CNT
-#define pWDOGB_STAT		(volatile unsigned long *)WDOGB_STAT
-
-/* UART Controller (0xFFC00400 - 0xFFC004FF) */
-#define pUART_THR		(volatile unsigned short *)UART_THR
-#define pUART_RBR		(volatile unsigned short *)UART_RBR
-#define pUART_DLL		(volatile unsigned short *)UART_DLL
-#define pUART_IER		(volatile unsigned short *)UART_IER
-#define pUART_DLH		(volatile unsigned short *)UART_DLH
-#define pUART_IIR		(volatile unsigned short *)UART_IIR
-#define pUART_LCR		(volatile unsigned short *)UART_LCR
-#define pUART_MCR		(volatile unsigned short *)UART_MCR
-#define pUART_LSR		(volatile unsigned short *)UART_LSR
-#define pUART_MSR		(volatile unsigned short *)UART_MSR
-#define pUART_SCR		(volatile unsigned short *)UART_SCR
-#define pUART_GCTL		(volatile unsigned short *)UART_GCTL
-
-/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
-#define pSPI_CTL		(volatile unsigned short *)SPI_CTL
-#define pSPI_FLG		(volatile unsigned short *)SPI_FLG
-#define pSPI_STAT		(volatile unsigned short *)SPI_STAT
-#define pSPI_TDBR		(volatile unsigned short *)SPI_TDBR
-#define pSPI_RDBR		(volatile unsigned short *)SPI_RDBR
-#define pSPI_BAUD		(volatile unsigned short *)SPI_BAUD
-#define pSPI_SHADOW		(volatile unsigned short *)SPI_SHADOW
-
-/* Timer 0-7 registers (0xFFC0 0600-0xFFC0 06FF) */
-#define pTIMER0_CONFIG		(volatile unsigned short *)TIMER0_CONFIG
-#define pTIMER0_COUNTER		(volatile unsigned long *)TIMER0_COUNTER
-#define pTIMER0_PERIOD		(volatile unsigned long *)TIMER0_PERIOD
-#define pTIMER0_WIDTH		(volatile unsigned long *)TIMER0_WIDTH
-#define pTIMER1_CONFIG		(volatile unsigned short *)TIMER1_CONFIG
-#define pTIMER1_COUNTER		(volatile unsigned long *)TIMER1_COUNTER
-#define pTIMER1_PERIOD		(volatile unsigned long *)TIMER1_PERIOD
-#define pTIMER1_WIDTH		(volatile unsigned long *)TIMER1_WIDTH
-#define pTIMER2_CONFIG		(volatile unsigned short *)TIMER2_CONFIG
-#define pTIMER2_COUNTER		(volatile unsigned long *)TIMER2_COUNTER
-#define pTIMER2_PERIOD		(volatile unsigned long *)TIMER2_PERIOD
-#define pTIMER2_WIDTH		(volatile unsigned long *)TIMER2_WIDTH
-#define pTIMER3_CONFIG		(volatile unsigned short *)TIMER3_CONFIG
-#define pTIMER3_COUNTER		(volatile unsigned long *)TIMER3_COUNTER
-#define pTIMER3_PERIOD		(volatile unsigned long *)TIMER3_PERIOD
-#define pTIMER3_WIDTH		(volatile unsigned long *)TIMER3_WIDTH
-#define pTIMER4_CONFIG		(volatile unsigned short *)TIMER4_CONFIG
-#define pTIMER4_COUNTER		(volatile unsigned long *)TIMER4_COUNTER
-#define pTIMER4_PERIOD		(volatile unsigned long *)TIMER4_PERIOD
-#define pTIMER4_WIDTH		(volatile unsigned long *)TIMER4_WIDTH
-#define pTIMER5_CONFIG		(volatile unsigned short *)TIMER5_CONFIG
-#define pTIMER5_COUNTER		(volatile unsigned long *)TIMER5_COUNTER
-#define pTIMER5_PERIOD		(volatile unsigned long *)TIMER5_PERIOD
-#define pTIMER5_WIDTH		(volatile unsigned long *)TIMER5_WIDTH
-#define pTIMER6_CONFIG		(volatile unsigned short *)TIMER6_CONFIG
-#define pTIMER6_COUNTER		(volatile unsigned long *)TIMER6_COUNTER
-#define pTIMER6_PERIOD		(volatile unsigned long *)TIMER6_PERIOD
-#define pTIMER6_WIDTH		(volatile unsigned long *)TIMER6_WIDTH
-#define pTIMER7_CONFIG		(volatile unsigned short *)TIMER7_CONFIG
-#define pTIMER7_COUNTER		(volatile unsigned long *)TIMER7_COUNTER
-#define pTIMER7_PERIOD		(volatile unsigned long *)TIMER7_PERIOD
-#define pTIMER7_WIDTH		(volatile unsigned long *)TIMER7_WIDTH
-
-/* Timer registers 8-11 (0xFFC0 1600-0xFFC0 16FF) */
-#define pTMRS8_ENABLE		(volatile unsigned short *)TMRS8_ENABLE
-#define pTMRS8_DISABLE		(volatile unsigned short *)TMRS8_DISABLE
-#define pTMRS8_STATUS		(volatile unsigned long *)TMRS8_STATUS
-#define pTIMER8_CONFIG		(volatile unsigned short *)TIMER8_CONFIG
-#define pTIMER8_COUNTER		(volatile unsigned long *)TIMER8_COUNTER
-#define pTIMER8_PERIOD		(volatile unsigned long *)TIMER8_PERIOD
-#define pTIMER8_WIDTH		(volatile unsigned long *)TIMER8_WIDTH
-#define pTIMER9_CONFIG		(volatile unsigned short *)TIMER9_CONFIG
-#define pTIMER9_COUNTER		(volatile unsigned long *)TIMER9_COUNTER
-#define pTIMER9_PERIOD		(volatile unsigned long *)TIMER9_PERIOD
-#define pTIMER9_WIDTH		(volatile unsigned long *)TIMER9_WIDTH
-#define pTIMER10_CONFIG		(volatile unsigned short *)TIMER10_CONFIG
-#define pTIMER10_COUNTER	(volatile unsigned long *)TIMER10_COUNTER
-#define pTIMER10_PERIOD		(volatile unsigned long *)TIMER10_PERIOD
-#define pTIMER10_WIDTH		(volatile unsigned long *)TIMER10_WIDTH
-#define pTIMER11_CONFIG		(volatile unsigned short *)TIMER11_CONFIG
-#define pTIMER11_COUNTER	(volatile unsigned long *)TIMER11_COUNTER
-#define pTIMER11_PERIOD		(volatile unsigned long *)TIMER11_PERIOD
-#define pTIMER11_WIDTH		(volatile unsigned long *)TIMER11_WIDTH
-#define pTMRS4_ENABLE		(volatile unsigned short *)TMRS4_ENABLE
-#define pTMRS4_DISABLE		(volatile unsigned short *)TMRS4_DISABLE
-#define pTMRS4_STATUS		(volatile unsigned long *)TMRS4_STATUS
-
-/* Programmable Flag 0 registers (0xFFC0 0700-0xFFC0 07FF) */
-#define pFIO0_FLAG_D		(volatile unsigned short *)FIO0_FLAG_D
-#define pFIO0_FLAG_C		(volatile unsigned short *)FIO0_FLAG_C
-#define pFIO0_FLAG_S		(volatile unsigned short *)FIO0_FLAG_S
-#define pFIO0_FLAG_T		(volatile unsigned short *)FIO0_FLAG_T
-#define pFIO0_MASKA_D		(volatile unsigned short *)FIO0_MASKA_D
-#define pFIO0_MASKA_C		(volatile unsigned short *)FIO0_MASKA_C
-#define pFIO0_MASKA_S		(volatile unsigned short *)FIO0_MASKA_S
-#define pFIO0_MASKA_T		(volatile unsigned short *)FIO0_MASKA_T
-#define pFIO0_MASKB_D		(volatile unsigned short *)FIO0_MASKB_D
-#define pFIO0_MASKB_C		(volatile unsigned short *)FIO0_MASKB_C
-#define pFIO0_MASKB_S		(volatile unsigned short *)FIO0_MASKB_S
-#define pFIO0_MASKB_T		(volatile unsigned short *)FIO0_MASKB_T
-#define pFIO0_DIR		(volatile unsigned short *)FIO0_DIR
-#define pFIO0_POLAR		(volatile unsigned short *)FIO0_POLAR
-#define pFIO0_EDGE		(volatile unsigned short *)FIO0_EDGE
-#define pFIO0_BOTH		(volatile unsigned short *)FIO0_BOTH
-#define pFIO0_INEN		(volatile unsigned short *)FIO0_INEN
-
-/* Programmable Flag 1 registers (0xFFC0 1500-0xFFC0 15FF) */
-#define pFIO1_FLAG_D		(volatile unsigned short *)FIO1_FLAG_D
-#define pFIO1_FLAG_C		(volatile unsigned short *)FIO1_FLAG_C
-#define pFIO1_FLAG_S		(volatile unsigned short *)FIO1_FLAG_S
-#define pFIO1_FLAG_T		(volatile unsigned short *)FIO1_FLAG_T
-#define pFIO1_MASKA_D		(volatile unsigned short *)FIO1_MASKA_D
-#define pFIO1_MASKA_C		(volatile unsigned short *)FIO1_MASKA_C
-#define pFIO1_MASKA_S		(volatile unsigned short *)FIO1_MASKA_S
-#define pFIO1_MASKA_T		(volatile unsigned short *)FIO1_MASKA_T
-#define pFIO1_MASKB_D		(volatile unsigned short *)FIO1_MASKB_D
-#define pFIO1_MASKB_C		(volatile unsigned short *)FIO1_MASKB_C
-#define pFIO1_MASKB_S		(volatile unsigned short *)FIO1_MASKB_S
-#define pFIO1_MASKB_T		(volatile unsigned short *)FIO1_MASKB_T
-#define pFIO1_DIR		(volatile unsigned short *)FIO1_DIR
-#define pFIO1_POLAR		(volatile unsigned short *)FIO1_POLAR
-#define pFIO1_EDGE		(volatile unsigned short *)FIO1_EDGE
-#define pFIO1_BOTH		(volatile unsigned short *)FIO1_BOTH
-#define pFIO1_INEN		(volatile unsigned short *)FIO1_INEN
-
-/* Programmable Flag registers (0xFFC0 1700-0xFFC0 17FF) */
-#define pFIO2_FLAG_D		(volatile unsigned short *)FIO2_FLAG_D
-#define pFIO2_FLAG_C		(volatile unsigned short *)FIO2_FLAG_C
-#define pFIO2_FLAG_S		(volatile unsigned short *)FIO2_FLAG_S
-#define pFIO2_FLAG_T		(volatile unsigned short *)FIO2_FLAG_T
-#define pFIO2_MASKA_D		(volatile unsigned short *)FIO2_MASKA_D
-#define pFIO2_MASKA_C		(volatile unsigned short *)FIO2_MASKA_C
-#define pFIO2_MASKA_S		(volatile unsigned short *)FIO2_MASKA_S
-#define pFIO2_MASKA_T		(volatile unsigned short *)FIO2_MASKA_T
-#define pFIO2_MASKB_D		(volatile unsigned short *)FIO2_MASKB_D
-#define pFIO2_MASKB_C		(volatile unsigned short *)FIO2_MASKB_C
-#define pFIO2_MASKB_S		(volatile unsigned short *)FIO2_MASKB_S
-#define pFIO2_MASKB_T		(volatile unsigned short *)FIO2_MASKB_T
-#define pFIO2_DIR		(volatile unsigned short *)FIO2_DIR
-#define pFIO2_POLAR		(volatile unsigned short *)FIO2_POLAR
-#define pFIO2_EDGE		(volatile unsigned short *)FIO2_EDGE
-#define pFIO2_BOTH		(volatile unsigned short *)FIO2_BOTH
-#define pFIO2_INEN		(volatile unsigned short *)FIO2_INEN
-
-/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
-#define pSPORT0_TCR1		(volatile unsigned short *)SPORT0_TCR1
-#define pSPORT0_TCR2		(volatile unsigned short *)SPORT0_TCR2
-#define pSPORT0_TCLKDIV		(volatile unsigned short *)SPORT0_TCLKDIV
-#define pSPORT0_TFSDIV		(volatile unsigned short *)SPORT0_TFSDIV
-#define pSPORT0_TX		(volatile unsigned long *)SPORT0_TX
-#define pSPORT0_RX		(volatile unsigned long *)SPORT0_RX
-#define pSPORT0_TX32		((volatile long *)SPORT0_TX)
-#define pSPORT0_RX32		((volatile long *)SPORT0_RX)
-#define pSPORT0_TX16		((volatile unsigned short *)SPORT0_TX)
-#define pSPORT0_RX16		((volatile unsigned short *)SPORT0_RX)
-#define pSPORT0_RCR1		(volatile unsigned short *)SPORT0_RCR1
-#define pSPORT0_RCR2		(volatile unsigned short *)SPORT0_RCR2
-#define pSPORT0_RCLKDIV		(volatile unsigned short *)SPORT0_RCLKDIV
-#define pSPORT0_RFSDIV		(volatile unsigned short *)SPORT0_RFSDIV
-#define pSPORT0_STAT		(volatile unsigned short *)SPORT0_STAT
-#define pSPORT0_CHNL		(volatile unsigned short *)SPORT0_CHNL
-#define pSPORT0_MCMC1		(volatile unsigned short *)SPORT0_MCMC1
-#define pSPORT0_MCMC2		(volatile unsigned short *)SPORT0_MCMC2
-#define pSPORT0_MTCS0		(volatile unsigned long *)SPORT0_MTCS0
-#define pSPORT0_MTCS1		(volatile unsigned long *)SPORT0_MTCS1
-#define pSPORT0_MTCS2		(volatile unsigned long *)SPORT0_MTCS2
-#define pSPORT0_MTCS3		(volatile unsigned long *)SPORT0_MTCS3
-#define pSPORT0_MRCS0		(volatile unsigned long *)SPORT0_MRCS0
-#define pSPORT0_MRCS1		(volatile unsigned long *)SPORT0_MRCS1
-#define pSPORT0_MRCS2		(volatile unsigned long *)SPORT0_MRCS2
-#define pSPORT0_MRCS3		(volatile unsigned long *)SPORT0_MRCS3
-
-/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
-#define pSPORT1_TCR1		(volatile unsigned short *)SPORT1_TCR1
-#define pSPORT1_TCR2		(volatile unsigned short *)SPORT1_TCR2
-#define pSPORT1_TCLKDIV		(volatile unsigned short *)SPORT1_TCLKDIV
-#define pSPORT1_TFSDIV		(volatile unsigned short *)SPORT1_TFSDIV
-#define pSPORT1_TX		(volatile unsigned long *)SPORT1_TX
-#define pSPORT1_RX		(volatile unsigned long *)SPORT1_RX
-#define pSPORT1_TX32		((volatile long *)SPORT1_TX)
-#define pSPORT1_RX32		((volatile long *)SPORT1_RX)
-#define pSPORT1_TX16		((volatile unsigned short *)SPORT1_TX)
-#define pSPORT1_RX16		((volatile unsigned short *)SPORT1_RX)
-#define pSPORT1_RCR1		(volatile unsigned short *)SPORT1_RCR1
-#define pSPORT1_RCR2		(volatile unsigned short *)SPORT1_RCR2
-#define pSPORT1_RCLKDIV		(volatile unsigned short *)SPORT1_RCLKDIV
-#define pSPORT1_RFSDIV		(volatile unsigned short *)SPORT1_RFSDIV
-#define pSPORT1_STAT		(volatile unsigned short *)SPORT1_STAT
-#define pSPORT1_CHNL		(volatile unsigned short *)SPORT1_CHNL
-#define pSPORT1_MCMC1		(volatile unsigned short *)SPORT1_MCMC1
-#define pSPORT1_MCMC2		(volatile unsigned short *)SPORT1_MCMC2
-#define pSPORT1_MTCS0		(volatile unsigned long *)SPORT1_MTCS0
-#define pSPORT1_MTCS1		(volatile unsigned long *)SPORT1_MTCS1
-#define pSPORT1_MTCS2		(volatile unsigned long *)SPORT1_MTCS2
-#define pSPORT1_MTCS3		(volatile unsigned long *)SPORT1_MTCS3
-#define pSPORT1_MRCS0		(volatile unsigned long *)SPORT1_MRCS0
-#define pSPORT1_MRCS1		(volatile unsigned long *)SPORT1_MRCS1
-#define pSPORT1_MRCS2		(volatile unsigned long *)SPORT1_MRCS2
-#define pSPORT1_MRCS3		(volatile unsigned long *)SPORT1_MRCS3
-
-/* Asynchronous Memory Controller - External Bus Interface Unit */
-#define pEBIU_AMGCTL		(volatile unsigned short *)EBIU_AMGCTL
-#define pEBIU_AMBCTL0		(volatile unsigned long *)EBIU_AMBCTL0
-#define pEBIU_AMBCTL1		(volatile unsigned long *)EBIU_AMBCTL1
-
-/* SDRAM Controller External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
-#define pEBIU_SDGCTL		(volatile unsigned long *)EBIU_SDGCTL
-#define pEBIU_SDBCTL		(volatile unsigned long *)EBIU_SDBCTL
-#define pEBIU_SDRRC		(volatile unsigned short *)EBIU_SDRRC
-#define pEBIU_SDSTAT		(volatile unsigned short *)EBIU_SDSTAT
-
-/* Parallel Peripheral Interface (PPI) 0 registers (0xFFC0 1000-0xFFC0 10FF)*/
-#define pPPI0_CONTROL		(volatile unsigned short *)PPI0_CONTROL
-#define pPPI0_STATUS		(volatile unsigned short *)PPI0_STATUS
-#define pPPI0_COUNT		(volatile unsigned short *)PPI0_COUNT
-#define pPPI0_DELAY		(volatile unsigned short *)PPI0_DELAY
-#define pPPI0_FRAME		(volatile unsigned short *)PPI0_FRAME
-
-/* Parallel Peripheral Interface (PPI) 1 registers (0xFFC0 1300-0xFFC0 13FF)*/
-#define pPPI1_CONTROL		(volatile unsigned short *)PPI1_CONTROL
-#define pPPI1_STATUS		(volatile unsigned short *)PPI1_STATUS
-#define pPPI1_COUNT		(volatile unsigned short *)PPI1_COUNT
-#define pPPI1_DELAY		(volatile unsigned short *)PPI1_DELAY
-#define pPPI1_FRAME		(volatile unsigned short *)PPI1_FRAME
-
-/*DMA Traffic controls*/
-#define pDMA_TCPER		((volatile unsigned short *)DMA_TCPER)
-#define pDMA_TCCNT		((volatile unsigned short *)DMA_TCCNT)
-#define pDMA_TC_PER		((volatile unsigned short *)DMA_TC_PER)
-#define pDMA_TC_CNT		((volatile unsigned short *)DMA_TC_CNT)
-
-/* DMA1 Controller registers (0xFFC0 1C00-0xFFC0 1FFF) */
-#define pDMA1_0_CONFIG		(volatile unsigned short *)DMA1_0_CONFIG
-#define pDMA1_0_NEXT_DESC_PTR	(volatile void **)DMA1_0_NEXT_DESC_PTR
-#define pDMA1_0_START_ADDR	(volatile void **)DMA1_0_START_ADDR
-#define pDMA1_0_X_COUNT		(volatile unsigned short *)DMA1_0_X_COUNT
-#define pDMA1_0_Y_COUNT		(volatile unsigned short *)DMA1_0_Y_COUNT
-#define pDMA1_0_X_MODIFY	(volatile unsigned short *)DMA1_0_X_MODIFY
-#define pDMA1_0_Y_MODIFY	(volatile unsigned short *)DMA1_0_Y_MODIFY
-#define pDMA1_0_CURR_DESC_PTR	(volatile void **)DMA1_0_CURR_DESC_PTR
-#define pDMA1_0_CURR_ADDR	(volatile void **)DMA1_0_CURR_ADDR
-#define pDMA1_0_CURR_X_COUNT	(volatile unsigned short *)DMA1_0_CURR_X_COUNT
-#define pDMA1_0_CURR_Y_COUNT	(volatile unsigned short *)DMA1_0_CURR_Y_COUNT
-#define pDMA1_0_IRQ_STATUS	(volatile unsigned short *)DMA1_0_IRQ_STATUS
-#define pDMA1_0_PERIPHERAL_MAP	(volatile unsigned short *)DMA1_0_PERIPHERAL_MAP
-#define pDMA1_1_CONFIG		(volatile unsigned short *)DMA1_1_CONFIG
-#define pDMA1_1_NEXT_DESC_PTR	(volatile void **)DMA1_1_NEXT_DESC_PTR
-#define pDMA1_1_START_ADDR	(volatile void **)DMA1_1_START_ADDR
-#define pDMA1_1_X_COUNT		(volatile unsigned short *)DMA1_1_X_COUNT
-#define pDMA1_1_Y_COUNT		(volatile unsigned short *)DMA1_1_Y_COUNT
-#define pDMA1_1_X_MODIFY	(volatile unsigned short *)DMA1_1_X_MODIFY
-#define pDMA1_1_Y_MODIFY	(volatile unsigned short *)DMA1_1_Y_MODIFY
-#define pDMA1_1_CURR_DESC_PTR	(volatile void **)DMA1_1_CURR_DESC_PTR
-#define pDMA1_1_CURR_ADDR	(volatile void **)DMA1_1_CURR_ADDR
-#define pDMA1_1_CURR_X_COUNT	(volatile unsigned short *)DMA1_1_CURR_X_COUNT
-#define pDMA1_1_CURR_Y_COUNT	(volatile unsigned short *)DMA1_1_CURR_Y_COUNT
-#define pDMA1_1_IRQ_STATUS	(volatile unsigned short *)DMA1_1_IRQ_STATUS
-#define pDMA1_1_PERIPHERAL_MAP	(volatile unsigned short *)DMA1_1_PERIPHERAL_MAP
-#define pDMA1_2_CONFIG		(volatile unsigned short *)DMA1_2_CONFIG
-#define pDMA1_2_NEXT_DESC_PTR	(volatile void **)DMA1_2_NEXT_DESC_PTR
-#define pDMA1_2_START_ADDR	(volatile void **)DMA1_2_START_ADDR
-#define pDMA1_2_X_COUNT		(volatile unsigned short *)DMA1_2_X_COUNT
-#define pDMA1_2_Y_COUNT		(volatile unsigned short *)DMA1_2_Y_COUNT
-#define pDMA1_2_X_MODIFY	(volatile unsigned short *)DMA1_2_X_MODIFY
-#define pDMA1_2_Y_MODIFY	(volatile unsigned short *)DMA1_2_Y_MODIFY
-#define pDMA1_2_CURR_DESC_PTR	(volatile void **)DMA1_2_CURR_DESC_PTR
-#define pDMA1_2_CURR_ADDR	(volatile void **)DMA1_2_CURR_ADDR
-#define pDMA1_2_CURR_X_COUNT	(volatile unsigned short *)DMA1_2_CURR_X_COUNT
-#define pDMA1_2_CURR_Y_COUNT	(volatile unsigned short *)DMA1_2_CURR_Y_COUNT
-#define pDMA1_2_IRQ_STATUS	(volatile unsigned short *)DMA1_2_IRQ_STATUS
-#define pDMA1_2_PERIPHERAL_MAP	(volatile unsigned short *)DMA1_2_PERIPHERAL_MAP
-#define pDMA1_3_CONFIG		(volatile unsigned short *)DMA1_3_CONFIG
-#define pDMA1_3_NEXT_DESC_PTR	(volatile void **)DMA1_3_NEXT_DESC_PTR
-#define pDMA1_3_START_ADDR	(volatile void **)DMA1_3_START_ADDR
-#define pDMA1_3_X_COUNT		(volatile unsigned short *)DMA1_3_X_COUNT
-#define pDMA1_3_Y_COUNT		(volatile unsigned short *)DMA1_3_Y_COUNT
-#define pDMA1_3_X_MODIFY	(volatile unsigned short *)DMA1_3_X_MODIFY
-#define pDMA1_3_Y_MODIFY	(volatile unsigned short *)DMA1_3_Y_MODIFY
-#define pDMA1_3_CURR_DESC_PTR	(volatile void **)DMA1_3_CURR_DESC_PTR
-#define pDMA1_3_CURR_ADDR	(volatile void **)DMA1_3_CURR_ADDR
-#define pDMA1_3_CURR_X_COUNT	(volatile unsigned short *)DMA1_3_CURR_X_COUNT
-#define pDMA1_3_CURR_Y_COUNT	(volatile unsigned short *)DMA1_3_CURR_Y_COUNT
-#define pDMA1_3_IRQ_STATUS	(volatile unsigned short *)DMA1_3_IRQ_STATUS
-#define pDMA1_3_PERIPHERAL_MAP	(volatile unsigned short *)DMA1_3_PERIPHERAL_MAP
-#define pDMA1_4_CONFIG		(volatile unsigned short *)DMA1_4_CONFIG
-#define pDMA1_4_NEXT_DESC_PTR	(volatile void **)DMA1_4_NEXT_DESC_PTR
-#define pDMA1_4_START_ADDR	(volatile void **)DMA1_4_START_ADDR
-#define pDMA1_4_X_COUNT		(volatile unsigned short *)DMA1_4_X_COUNT
-#define pDMA1_4_Y_COUNT		(volatile unsigned short *)DMA1_4_Y_COUNT
-#define pDMA1_4_X_MODIFY	(volatile unsigned short *)DMA1_4_X_MODIFY
-#define pDMA1_4_Y_MODIFY	(volatile unsigned short *)DMA1_4_Y_MODIFY
-#define pDMA1_4_CURR_DESC_PTR	(volatile void **)DMA1_4_CURR_DESC_PTR
-#define pDMA1_4_CURR_ADDR	(volatile void **)DMA1_4_CURR_ADDR
-#define pDMA1_4_CURR_X_COUNT	(volatile unsigned short *)DMA1_4_CURR_X_COUNT
-#define pDMA1_4_CURR_Y_COUNT	(volatile unsigned short *)DMA1_4_CURR_Y_COUNT
-#define pDMA1_4_IRQ_STATUS	(volatile unsigned short *)DMA1_4_IRQ_STATUS
-#define pDMA1_4_PERIPHERAL_MAP	(volatile unsigned short *)DMA1_4_PERIPHERAL_MAP
-#define pDMA1_5_CONFIG		(volatile unsigned short *)DMA1_5_CONFIG
-#define pDMA1_5_NEXT_DESC_PTR	(volatile void **)DMA1_5_NEXT_DESC_PTR
-#define pDMA1_5_START_ADDR	(volatile void **)DMA1_5_START_ADDR
-#define pDMA1_5_X_COUNT		(volatile unsigned short *)DMA1_5_X_COUNT
-#define pDMA1_5_Y_COUNT		(volatile unsigned short *)DMA1_5_Y_COUNT
-#define pDMA1_5_X_MODIFY	(volatile unsigned short *)DMA1_5_X_MODIFY
-#define pDMA1_5_Y_MODIFY	(volatile unsigned short *)DMA1_5_Y_MODIFY
-#define pDMA1_5_CURR_DESC_PTR	(volatile void **)DMA1_5_CURR_DESC_PTR
-#define pDMA1_5_CURR_ADDR	(volatile void **)DMA1_5_CURR_ADDR
-#define pDMA1_5_CURR_X_COUNT	(volatile unsigned short *)DMA1_5_CURR_X_COUNT
-#define pDMA1_5_CURR_Y_COUNT	(volatile unsigned short *)DMA1_5_CURR_Y_COUNT
-#define pDMA1_5_IRQ_STATUS	(volatile unsigned short *)DMA1_5_IRQ_STATUS
-#define pDMA1_5_PERIPHERAL_MAP	(volatile unsigned short *)DMA1_5_PERIPHERAL_MAP
-#define pDMA1_6_CONFIG		(volatile unsigned short *)DMA1_6_CONFIG
-#define pDMA1_6_NEXT_DESC_PTR	(volatile void **)DMA1_6_NEXT_DESC_PTR
-#define pDMA1_6_START_ADDR	(volatile void **)DMA1_6_START_ADDR
-#define pDMA1_6_X_COUNT		(volatile unsigned short *)DMA1_6_X_COUNT
-#define pDMA1_6_Y_COUNT		(volatile unsigned short *)DMA1_6_Y_COUNT
-#define pDMA1_6_X_MODIFY	(volatile unsigned short *)DMA1_6_X_MODIFY
-#define pDMA1_6_Y_MODIFY	(volatile unsigned short *)DMA1_6_Y_MODIFY
-#define pDMA1_6_CURR_DESC_PTR	(volatile void **)DMA1_6_CURR_DESC_PTR
-#define pDMA1_6_CURR_ADDR	(volatile void **)DMA1_6_CURR_ADDR
-#define pDMA1_6_CURR_X_COUNT	(volatile unsigned short *)DMA1_6_CURR_X_COUNT
-#define pDMA1_6_CURR_Y_COUNT	(volatile unsigned short *)DMA1_6_CURR_Y_COUNT
-#define pDMA1_6_IRQ_STATUS	(volatile unsigned short *)DMA1_6_IRQ_STATUS
-#define pDMA1_6_PERIPHERAL_MAP	(volatile unsigned short *)DMA1_6_PERIPHERAL_MAP
-#define pDMA1_7_CONFIG		(volatile unsigned short *)DMA1_7_CONFIG
-#define pDMA1_7_NEXT_DESC_PTR	(volatile void **)DMA1_7_NEXT_DESC_PTR
-#define pDMA1_7_START_ADDR	(volatile void **)DMA1_7_START_ADDR
-#define pDMA1_7_X_COUNT		(volatile unsigned short *)DMA1_7_X_COUNT
-#define pDMA1_7_Y_COUNT		(volatile unsigned short *)DMA1_7_Y_COUNT
-#define pDMA1_7_X_MODIFY	(volatile unsigned short *)DMA1_7_X_MODIFY
-#define pDMA1_7_Y_MODIFY	(volatile unsigned short *)DMA1_7_Y_MODIFY
-#define pDMA1_7_CURR_DESC_PTR	(volatile void **)DMA1_7_CURR_DESC_PTR
-#define pDMA1_7_CURR_ADDR	(volatile void **)DMA1_7_CURR_ADDR
-#define pDMA1_7_CURR_X_COUNT	(volatile unsigned short *)DMA1_7_CURR_X_COUNT
-#define pDMA1_7_CURR_Y_COUNT	(volatile unsigned short *)DMA1_7_CURR_Y_COUNT
-#define pDMA1_7_IRQ_STATUS	(volatile unsigned short *)DMA1_7_IRQ_STATUS
-#define pDMA1_7_PERIPHERAL_MAP	(volatile unsigned short *)DMA1_7_PERIPHERAL_MAP
-#define pDMA1_8_CONFIG		(volatile unsigned short *)DMA1_8_CONFIG
-#define pDMA1_8_NEXT_DESC_PTR	(volatile void **)DMA1_8_NEXT_DESC_PTR
-#define pDMA1_8_START_ADDR	(volatile void **)DMA1_8_START_ADDR
-#define pDMA1_8_X_COUNT		(volatile unsigned short *)DMA1_8_X_COUNT
-#define pDMA1_8_Y_COUNT		(volatile unsigned short *)DMA1_8_Y_COUNT
-#define pDMA1_8_X_MODIFY	(volatile unsigned short *)DMA1_8_X_MODIFY
-#define pDMA1_8_Y_MODIFY	(volatile unsigned short *)DMA1_8_Y_MODIFY
-#define pDMA1_8_CURR_DESC_PTR	(volatile void **)DMA1_8_CURR_DESC_PTR
-#define pDMA1_8_CURR_ADDR	(volatile void **)DMA1_8_CURR_ADDR
-#define pDMA1_8_CURR_X_COUNT	(volatile unsigned short *)DMA1_8_CURR_X_COUNT
-#define pDMA1_8_CURR_Y_COUNT	(volatile unsigned short *)DMA1_8_CURR_Y_COUNT
-#define pDMA1_8_IRQ_STATUS	(volatile unsigned short *)DMA1_8_IRQ_STATUS
-#define pDMA1_8_PERIPHERAL_MAP	(volatile unsigned short *)DMA1_8_PERIPHERAL_MAP
-#define pDMA1_9_CONFIG		(volatile unsigned short *)DMA1_9_CONFIG
-#define pDMA1_9_NEXT_DESC_PTR	(volatile void **)DMA1_9_NEXT_DESC_PTR
-#define pDMA1_9_START_ADDR	(volatile void **)DMA1_9_START_ADDR
-#define pDMA1_9_X_COUNT		(volatile unsigned short *)DMA1_9_X_COUNT
-#define pDMA1_9_Y_COUNT		(volatile unsigned short *)DMA1_9_Y_COUNT
-#define pDMA1_9_X_MODIFY	(volatile unsigned short *)DMA1_9_X_MODIFY
-#define pDMA1_9_Y_MODIFY	(volatile unsigned short *)DMA1_9_Y_MODIFY
-#define pDMA1_9_CURR_DESC_PTR	(volatile void **)DMA1_9_CURR_DESC_PTR
-#define pDMA1_9_CURR_ADDR	(volatile void **)DMA1_9_CURR_ADDR
-#define pDMA1_9_CURR_X_COUNT	(volatile unsigned short *)DMA1_9_CURR_X_COUNT
-#define pDMA1_9_CURR_Y_COUNT	(volatile unsigned short *)DMA1_9_CURR_Y_COUNT
-#define pDMA1_9_IRQ_STATUS	(volatile unsigned short *)DMA1_9_IRQ_STATUS
-#define pDMA1_9_PERIPHERAL_MAP	(volatile unsigned short *)DMA1_9_PERIPHERAL_MAP
-#define pDMA1_10_CONFIG		(volatile unsigned short *)DMA1_10_CONFIG
-#define pDMA1_10_NEXT_DESC_PTR	(volatile void **)DMA1_10_NEXT_DESC_PTR
-#define pDMA1_10_START_ADDR	(volatile void **)DMA1_10_START_ADDR
-#define pDMA1_10_X_COUNT	(volatile unsigned short *)DMA1_10_X_COUNT
-#define pDMA1_10_Y_COUNT	(volatile unsigned short *)DMA1_10_Y_COUNT
-#define pDMA1_10_X_MODIFY	(volatile unsigned short *)DMA1_10_X_MODIFY
-#define pDMA1_10_Y_MODIFY	(volatile unsigned short *)DMA1_10_Y_MODIFY
-#define pDMA1_10_CURR_DESC_PTR	(volatile void **)DMA1_10_CURR_DESC_PTR
-#define pDMA1_10_CURR_ADDR	(volatile void **)DMA1_10_CURR_ADDR
-#define pDMA1_10_CURR_X_COUNT	(volatile unsigned short *)DMA1_10_CURR_X_COUNT
-#define pDMA1_10_CURR_Y_COUNT	(volatile unsigned short *)DMA1_10_CURR_Y_COUNT
-#define pDMA1_10_IRQ_STATUS	(volatile unsigned short *)DMA1_10_IRQ_STATUS
-#define pDMA1_10_PERIPHERAL_MAP (volatile unsigned short *)DMA1_10_PERIPHERAL_MAP
-#define pDMA1_11_CONFIG		(volatile unsigned short *)DMA1_11_CONFIG
-#define pDMA1_11_NEXT_DESC_PTR	(volatile void **)DMA1_11_NEXT_DESC_PTR
-#define pDMA1_11_START_ADDR	(volatile void **)DMA1_11_START_ADDR
-#define pDMA1_11_X_COUNT	(volatile unsigned short *)DMA1_11_X_COUNT
-#define pDMA1_11_Y_COUNT	(volatile unsigned short *)DMA1_11_Y_COUNT
-#define pDMA1_11_X_MODIFY	(volatile signed short *)DMA1_11_X_MODIFY
-#define pDMA1_11_Y_MODIFY	(volatile signed short *)DMA1_11_Y_MODIFY
-#define pDMA1_11_CURR_DESC_PTR	(volatile void **)DMA1_11_CURR_DESC_PTR
-#define pDMA1_11_CURR_ADDR	(volatile void **)DMA1_11_CURR_ADDR
-#define pDMA1_11_CURR_X_COUNT	(volatile unsigned short *)DMA1_11_CURR_X_COUNT
-#define pDMA1_11_CURR_Y_COUNT	(volatile unsigned short *)DMA1_11_CURR_Y_COUNT
-#define pDMA1_11_IRQ_STATUS	(volatile unsigned short *)DMA1_11_IRQ_STATUS
-#define pDMA1_11_PERIPHERAL_MAP (volatile unsigned short *)DMA1_11_PERIPHERAL_MAP
-
-/* Memory DMA1 Controller registers (0xFFC0 1E80-0xFFC0 1FFF)*/
-#define pMDMA1_D0_CONFIG	(volatile unsigned short *)MDMA1_D0_CONFIG
-#define pMDMA1_D0_NEXT_DESC_PTR (volatile void **)MDMA1_D0_NEXT_DESC_PTR
-#define pMDMA1_D0_START_ADDR	(volatile void **)MDMA1_D0_START_ADDR
-#define pMDMA1_D0_X_COUNT	(volatile unsigned short *)MDMA1_D0_X_COUNT
-#define pMDMA1_D0_Y_COUNT	(volatile unsigned short *)MDMA1_D0_Y_COUNT
-#define pMDMA1_D0_X_MODIFY	(volatile signed short *)MDMA1_D0_X_MODIFY
-#define pMDMA1_D0_Y_MODIFY	(volatile signed short *)MDMA1_D0_Y_MODIFY
-#define pMDMA1_D0_CURR_DESC_PTR (volatile void **)MDMA1_D0_CURR_DESC_PTR
-#define pMDMA1_D0_CURR_ADDR	(volatile void **)MDMA1_D0_CURR_ADDR
-#define pMDMA1_D0_CURR_X_COUNT	(volatile unsigned short *)MDMA1_D0_CURR_X_COUNT
-#define pMDMA1_D0_CURR_Y_COUNT	(volatile unsigned short *)MDMA1_D0_CURR_Y_COUNT
-#define pMDMA1_D0_IRQ_STATUS	(volatile unsigned short *)MDMA1_D0_IRQ_STATUS
-#define pMDMA1_D0_PERIPHERAL_MAP (volatile unsigned short *)MDMA1_D0_PERIPHERAL_MAP
-#define pMDMA1_S0_CONFIG	(volatile unsigned short *)MDMA1_S0_CONFIG
-#define pMDMA1_S0_NEXT_DESC_PTR (volatile void **)MDMA1_S0_NEXT_DESC_PTR
-#define pMDMA1_S0_START_ADDR	(volatile void **)MDMA1_S0_START_ADDR
-#define pMDMA1_S0_X_COUNT	(volatile unsigned short *)MDMA1_S0_X_COUNT
-#define pMDMA1_S0_Y_COUNT	(volatile unsigned short *)MDMA1_S0_Y_COUNT
-#define pMDMA1_S0_X_MODIFY	(volatile signed short *)MDMA1_S0_X_MODIFY
-#define pMDMA1_S0_Y_MODIFY	(volatile signed short *)MDMA1_S0_Y_MODIFY
-#define pMDMA1_S0_CURR_DESC_PTR (volatile void **)MDMA1_S0_CURR_DESC_PTR
-#define pMDMA1_S0_CURR_ADDR	(volatile void **)MDMA1_S0_CURR_ADDR
-#define pMDMA1_S0_CURR_X_COUNT	(volatile unsigned short *)MDMA1_S0_CURR_X_COUNT
-#define pMDMA1_S0_CURR_Y_COUNT	(volatile unsigned short *)MDMA1_S0_CURR_Y_COUNT
-#define pMDMA1_S0_IRQ_STATUS	(volatile unsigned short *)MDMA1_S0_IRQ_STATUS
-#define pMDMA1_S0_PERIPHERAL_MAP (volatile unsigned short *)MDMA1_S0_PERIPHERAL_MAP
-#define pMDMA1_D1_CONFIG	(volatile unsigned short *)MDMA1_D1_CONFIG
-#define pMDMA1_D1_NEXT_DESC_PTR (volatile void **)MDMA1_D1_NEXT_DESC_PTR
-#define pMDMA1_D1_START_ADDR	(volatile void **)MDMA1_D1_START_ADDR
-#define pMDMA1_D1_X_COUNT	(volatile unsigned short *)MDMA1_D1_X_COUNT
-#define pMDMA1_D1_Y_COUNT	(volatile unsigned short *)MDMA1_D1_Y_COUNT
-#define pMDMA1_D1_X_MODIFY	(volatile signed short *)MDMA1_D1_X_MODIFY
-#define pMDMA1_D1_Y_MODIFY	(volatile signed short *)MDMA1_D1_Y_MODIFY
-#define pMDMA1_D1_CURR_DESC_PTR (volatile void **)MDMA1_D1_CURR_DESC_PTR
-#define pMDMA1_D1_CURR_ADDR	(volatile void **)MDMA1_D1_CURR_ADDR
-#define pMDMA1_D1_CURR_X_COUNT	(volatile unsigned short *)MDMA1_D1_CURR_X_COUNT
-#define pMDMA1_D1_CURR_Y_COUNT	(volatile unsigned short *)MDMA1_D1_CURR_Y_COUNT
-#define pMDMA1_D1_IRQ_STATUS	(volatile unsigned short *)MDMA1_D1_IRQ_STATUS
-#define pMDMA1_D1_PERIPHERAL_MAP (volatile unsigned short *)MDMA1_D1_PERIPHERAL_MAP
-#define pMDMA1_S1_CONFIG	(volatile unsigned short *)MDMA1_S1_CONFIG
-#define pMDMA1_S1_NEXT_DESC_PTR (volatile void **)MDMA1_S1_NEXT_DESC_PTR
-#define pMDMA1_S1_START_ADDR	(volatile void **)MDMA1_S1_START_ADDR
-#define pMDMA1_S1_X_COUNT	(volatile unsigned short *)MDMA1_S1_X_COUNT
-#define pMDMA1_S1_Y_COUNT	(volatile unsigned short *)MDMA1_S1_Y_COUNT
-#define pMDMA1_S1_X_MODIFY	(volatile signed short *)MDMA1_S1_X_MODIFY
-#define pMDMA1_S1_Y_MODIFY	(volatile signed short *)MDMA1_S1_Y_MODIFY
-#define pMDMA1_S1_CURR_DESC_PTR (volatile void **)MDMA1_S1_CURR_DESC_PTR
-#define pMDMA1_S1_CURR_ADDR	(volatile void **)MDMA1_S1_CURR_ADDR
-#define pMDMA1_S1_CURR_X_COUNT	(volatile unsigned short *)MDMA1_S1_CURR_X_COUNT
-#define pMDMA1_S1_CURR_Y_COUNT	(volatile unsigned short *)MDMA1_S1_CURR_Y_COUNT
-#define pMDMA1_S1_IRQ_STATUS	(volatile unsigned short *)MDMA1_S1_IRQ_STATUS
-#define pMDMA1_S1_PERIPHERAL_MAP (volatile unsigned short *)MDMA1_S1_PERIPHERAL_MAP
-
-/* DMA2 Controller registers (0xFFC0 0C00-0xFFC0 0DFF) */
-#define pDMA2_0_CONFIG		(volatile unsigned short *)DMA2_0_CONFIG
-#define pDMA2_0_NEXT_DESC_PTR	(volatile void **)DMA2_0_NEXT_DESC_PTR
-#define pDMA2_0_START_ADDR	(volatile void **)DMA2_0_START_ADDR
-#define pDMA2_0_X_COUNT		(volatile unsigned short *)DMA2_0_X_COUNT
-#define pDMA2_0_Y_COUNT		(volatile unsigned short *)DMA2_0_Y_COUNT
-#define pDMA2_0_X_MODIFY	(volatile signed short *)DMA2_0_X_MODIFY
-#define pDMA2_0_Y_MODIFY	(volatile signed short *)DMA2_0_Y_MODIFY
-#define pDMA2_0_CURR_DESC_PTR	(volatile void **)DMA2_0_CURR_DESC_PTR
-#define pDMA2_0_CURR_ADDR	(volatile void **)DMA2_0_CURR_ADDR
-#define pDMA2_0_CURR_X_COUNT	(volatile unsigned short *)DMA2_0_CURR_X_COUNT
-#define pDMA2_0_CURR_Y_COUNT	(volatile unsigned short *)DMA2_0_CURR_Y_COUNT
-#define pDMA2_0_IRQ_STATUS	(volatile unsigned short *)DMA2_0_IRQ_STATUS
-#define pDMA2_0_PERIPHERAL_MAP	(volatile unsigned short *)DMA2_0_PERIPHERAL_MAP
-#define pDMA2_1_CONFIG		(volatile unsigned short *)DMA2_1_CONFIG
-#define pDMA2_1_NEXT_DESC_PTR	(volatile void **)DMA2_1_NEXT_DESC_PTR
-#define pDMA2_1_START_ADDR	(volatile void **)DMA2_1_START_ADDR
-#define pDMA2_1_X_COUNT		(volatile unsigned short *)DMA2_1_X_COUNT
-#define pDMA2_1_Y_COUNT		(volatile unsigned short *)DMA2_1_Y_COUNT
-#define pDMA2_1_X_MODIFY	(volatile signed short *)DMA2_1_X_MODIFY
-#define pDMA2_1_Y_MODIFY	(volatile signed short *)DMA2_1_Y_MODIFY
-#define pDMA2_1_CURR_DESC_PTR	(volatile void **)DMA2_1_CURR_DESC_PTR
-#define pDMA2_1_CURR_ADDR	(volatile void **)DMA2_1_CURR_ADDR
-#define pDMA2_1_CURR_X_COUNT	(volatile unsigned short *)DMA2_1_CURR_X_COUNT
-#define pDMA2_1_CURR_Y_COUNT	(volatile unsigned short *)DMA2_1_CURR_Y_COUNT
-#define pDMA2_1_IRQ_STATUS	(volatile unsigned short *)DMA2_1_IRQ_STATUS
-#define pDMA2_1_PERIPHERAL_MAP	(volatile unsigned short *)DMA2_1_PERIPHERAL_MAP
-#define pDMA2_2_CONFIG		(volatile unsigned short *)DMA2_2_CONFIG
-#define pDMA2_2_NEXT_DESC_PTR	(volatile void **)DMA2_2_NEXT_DESC_PTR
-#define pDMA2_2_START_ADDR	(volatile void **)DMA2_2_START_ADDR
-#define pDMA2_2_X_COUNT		(volatile unsigned short *)DMA2_2_X_COUNT
-#define pDMA2_2_Y_COUNT		(volatile unsigned short *)DMA2_2_Y_COUNT
-#define pDMA2_2_X_MODIFY	(volatile signed short *)DMA2_2_X_MODIFY
-#define pDMA2_2_Y_MODIFY	(volatile signed short *)DMA2_2_Y_MODIFY
-#define pDMA2_2_CURR_DESC_PTR	(volatile void **)DMA2_2_CURR_DESC_PTR
-#define pDMA2_2_CURR_ADDR	(volatile void **)DMA2_2_CURR_ADDR
-#define pDMA2_2_CURR_X_COUNT	(volatile unsigned short *)DMA2_2_CURR_X_COUNT
-#define pDMA2_2_CURR_Y_COUNT	(volatile unsigned short *)DMA2_2_CURR_Y_COUNT
-#define pDMA2_2_IRQ_STATUS	(volatile unsigned short *)DMA2_2_IRQ_STATUS
-#define pDMA2_2_PERIPHERAL_MAP	(volatile unsigned short *)DMA2_2_PERIPHERAL_MAP
-#define pDMA2_3_CONFIG		(volatile unsigned short *)DMA2_3_CONFIG
-#define pDMA2_3_NEXT_DESC_PTR	(volatile void **)DMA2_3_NEXT_DESC_PTR
-#define pDMA2_3_START_ADDR	(volatile void **)DMA2_3_START_ADDR
-#define pDMA2_3_X_COUNT		(volatile unsigned short *)DMA2_3_X_COUNT
-#define pDMA2_3_Y_COUNT		(volatile unsigned short *)DMA2_3_Y_COUNT
-#define pDMA2_3_X_MODIFY	(volatile signed short *)DMA2_3_X_MODIFY
-#define pDMA2_3_Y_MODIFY	(volatile signed short *)DMA2_3_Y_MODIFY
-#define pDMA2_3_CURR_DESC_PTR	(volatile void **)DMA2_3_CURR_DESC_PTR
-#define pDMA2_3_CURR_ADDR	(volatile void **)DMA2_3_CURR_ADDR
-#define pDMA2_3_CURR_X_COUNT	(volatile unsigned short *)DMA2_3_CURR_X_COUNT
-#define pDMA2_3_CURR_Y_COUNT	(volatile unsigned short *)DMA2_3_CURR_Y_COUNT
-#define pDMA2_3_IRQ_STATUS	(volatile unsigned short *)DMA2_3_IRQ_STATUS
-#define pDMA2_3_PERIPHERAL_MAP	(volatile unsigned short *)DMA2_3_PERIPHERAL_MAP
-#define pDMA2_4_CONFIG		(volatile unsigned short *)DMA2_4_CONFIG
-#define pDMA2_4_NEXT_DESC_PTR	(volatile void **)DMA2_4_NEXT_DESC_PTR
-#define pDMA2_4_START_ADDR	(volatile void **)DMA2_4_START_ADDR
-#define pDMA2_4_X_COUNT		(volatile unsigned short *)DMA2_4_X_COUNT
-#define pDMA2_4_Y_COUNT		(volatile unsigned short *)DMA2_4_Y_COUNT
-#define pDMA2_4_X_MODIFY	(volatile signed short *)DMA2_4_X_MODIFY
-#define pDMA2_4_Y_MODIFY	(volatile signed short *)DMA2_4_Y_MODIFY
-#define pDMA2_4_CURR_DESC_PTR	(volatile void **)DMA2_4_CURR_DESC_PTR
-#define pDMA2_4_CURR_ADDR	(volatile void **)DMA2_4_CURR_ADDR
-#define pDMA2_4_CURR_X_COUNT	(volatile unsigned short *)DMA2_4_CURR_X_COUNT
-#define pDMA2_4_CURR_Y_COUNT	(volatile unsigned short *)DMA2_4_CURR_Y_COUNT
-#define pDMA2_4_IRQ_STATUS	(volatile unsigned short *)DMA2_4_IRQ_STATUS
-#define pDMA2_4_PERIPHERAL_MAP	(volatile unsigned short *)DMA2_4_PERIPHERAL_MAP
-#define pDMA2_5_CONFIG		(volatile unsigned short *)DMA2_5_CONFIG
-#define pDMA2_5_NEXT_DESC_PTR	(volatile void **)DMA2_5_NEXT_DESC_PTR
-#define pDMA2_5_START_ADDR	(volatile void **)DMA2_5_START_ADDR
-#define pDMA2_5_X_COUNT		(volatile unsigned short *)DMA2_5_X_COUNT
-#define pDMA2_5_Y_COUNT		(volatile unsigned short *)DMA2_5_Y_COUNT
-#define pDMA2_5_X_MODIFY	(volatile signed short *)DMA2_5_X_MODIFY
-#define pDMA2_5_Y_MODIFY	(volatile signed short *)DMA2_5_Y_MODIFY
-#define pDMA2_5_CURR_DESC_PTR	(volatile void **)DMA2_5_CURR_DESC_PTR
-#define pDMA2_5_CURR_ADDR	(volatile void **)DMA2_5_CURR_ADDR
-#define pDMA2_5_CURR_X_COUNT	(volatile unsigned short *)DMA2_5_CURR_X_COUNT
-#define pDMA2_5_CURR_Y_COUNT	(volatile unsigned short *)DMA2_5_CURR_Y_COUNT
-#define pDMA2_5_IRQ_STATUS	(volatile unsigned short *)DMA2_5_IRQ_STATUS
-#define pDMA2_5_PERIPHERAL_MAP	(volatile unsigned short *)DMA2_5_PERIPHERAL_MAP
-#define pDMA2_6_CONFIG		(volatile unsigned short *)DMA2_6_CONFIG
-#define pDMA2_6_NEXT_DESC_PTR	(volatile void **)DMA2_6_NEXT_DESC_PTR
-#define pDMA2_6_START_ADDR	(volatile void **)DMA2_6_START_ADDR
-#define pDMA2_6_X_COUNT		(volatile unsigned short *)DMA2_6_X_COUNT
-#define pDMA2_6_Y_COUNT		(volatile unsigned short *)DMA2_6_Y_COUNT
-#define pDMA2_6_X_MODIFY	(volatile signed short *)DMA2_6_X_MODIFY
-#define pDMA2_6_Y_MODIFY	(volatile signed short *)DMA2_6_Y_MODIFY
-#define pDMA2_6_CURR_DESC_PTR	(volatile void **)DMA2_6_CURR_DESC_PTR
-#define pDMA2_6_CURR_ADDR	(volatile void **)DMA2_6_CURR_ADDR
-#define pDMA2_6_CURR_X_COUNT	(volatile unsigned short *)DMA2_6_CURR_X_COUNT
-#define pDMA2_6_CURR_Y_COUNT	(volatile unsigned short *)DMA2_6_CURR_Y_COUNT
-#define pDMA2_6_IRQ_STATUS	(volatile unsigned short *)DMA2_6_IRQ_STATUS
-#define pDMA2_6_PERIPHERAL_MAP	(volatile unsigned short *)DMA2_6_PERIPHERAL_MAP
-#define pDMA2_7_CONFIG		(volatile unsigned short *)DMA2_7_CONFIG
-#define pDMA2_7_NEXT_DESC_PTR	(volatile void **)DMA2_7_NEXT_DESC_PTR
-#define pDMA2_7_START_ADDR	(volatile void **)DMA2_7_START_ADDR
-#define pDMA2_7_X_COUNT		(volatile unsigned short *)DMA2_7_X_COUNT
-#define pDMA2_7_Y_COUNT		(volatile unsigned short *)DMA2_7_Y_COUNT
-#define pDMA2_7_X_MODIFY	(volatile signed short *)DMA2_7_X_MODIFY
-#define pDMA2_7_Y_MODIFY	(volatile signed short *)DMA2_7_Y_MODIFY
-#define pDMA2_7_CURR_DESC_PTR	(volatile void **)DMA2_7_CURR_DESC_PTR
-#define pDMA2_7_CURR_ADDR	(volatile void **)DMA2_7_CURR_ADDR
-#define pDMA2_7_CURR_X_COUNT	(volatile unsigned short *)DMA2_7_CURR_X_COUNT
-#define pDMA2_7_CURR_Y_COUNT	(volatile unsigned short *)DMA2_7_CURR_Y_COUNT
-#define pDMA2_7_IRQ_STATUS	(volatile unsigned short *)DMA2_7_IRQ_STATUS
-#define pDMA2_7_PERIPHERAL_MAP	(volatile unsigned short *)DMA2_7_PERIPHERAL_MAP
-#define pDMA2_8_CONFIG		(volatile unsigned short *)DMA2_8_CONFIG
-#define pDMA2_8_NEXT_DESC_PTR	(volatile void **)DMA2_8_NEXT_DESC_PTR
-#define pDMA2_8_START_ADDR	(volatile void **)DMA2_8_START_ADDR
-#define pDMA2_8_X_COUNT		(volatile unsigned short *)DMA2_8_X_COUNT
-#define pDMA2_8_Y_COUNT		(volatile unsigned short *)DMA2_8_Y_COUNT
-#define pDMA2_8_X_MODIFY	(volatile signed short *)DMA2_8_X_MODIFY
-#define pDMA2_8_Y_MODIFY	(volatile signed short *)DMA2_8_Y_MODIFY
-#define pDMA2_8_CURR_DESC_PTR	(volatile void **)DMA2_8_CURR_DESC_PTR
-#define pDMA2_8_CURR_ADDR	(volatile void **)DMA2_8_CURR_ADDR
-#define pDMA2_8_CURR_X_COUNT	(volatile unsigned short *)DMA2_8_CURR_X_COUNT
-#define pDMA2_8_CURR_Y_COUNT	(volatile unsigned short *)DMA2_8_CURR_Y_COUNT
-#define pDMA2_8_IRQ_STATUS	(volatile unsigned short *)DMA2_8_IRQ_STATUS
-#define pDMA2_8_PERIPHERAL_MAP	(volatile unsigned short *)DMA2_8_PERIPHERAL_MAP
-#define pDMA2_9_CONFIG		(volatile unsigned short *)DMA2_9_CONFIG
-#define pDMA2_9_NEXT_DESC_PTR	(volatile void **)DMA2_9_NEXT_DESC_PTR
-#define pDMA2_9_START_ADDR	(volatile void **)DMA2_9_START_ADDR
-#define pDMA2_9_X_COUNT		(volatile unsigned short *)DMA2_9_X_COUNT
-#define pDMA2_9_Y_COUNT		(volatile unsigned short *)DMA2_9_Y_COUNT
-#define pDMA2_9_X_MODIFY	(volatile signed short *)DMA2_9_X_MODIFY
-#define pDMA2_9_Y_MODIFY	(volatile signed short *)DMA2_9_Y_MODIFY
-#define pDMA2_9_CURR_DESC_PTR	(volatile void **)DMA2_9_CURR_DESC_PTR
-#define pDMA2_9_CURR_ADDR	(volatile void **)DMA2_9_CURR_ADDR
-#define pDMA2_9_CURR_X_COUNT	(volatile unsigned short *)DMA2_9_CURR_X_COUNT
-#define pDMA2_9_CURR_Y_COUNT	(volatile unsigned short *)DMA2_9_CURR_Y_COUNT
-#define pDMA2_9_IRQ_STATUS	(volatile unsigned short *)DMA2_9_IRQ_STATUS
-#define pDMA2_9_PERIPHERAL_MAP	(volatile unsigned short *)DMA2_9_PERIPHERAL_MAP
-#define pDMA2_10_CONFIG		(volatile unsigned short *)DMA2_10_CONFIG
-#define pDMA2_10_NEXT_DESC_PTR	(volatile void **)DMA2_10_NEXT_DESC_PTR
-#define pDMA2_10_START_ADDR	(volatile void **)DMA2_10_START_ADDR
-#define pDMA2_10_X_COUNT	(volatile unsigned short *)DMA2_10_X_COUNT
-#define pDMA2_10_Y_COUNT	(volatile unsigned short *)DMA2_10_Y_COUNT
-#define pDMA2_10_X_MODIFY	(volatile signed short *)DMA2_10_X_MODIFY
-#define pDMA2_10_Y_MODIFY	(volatile signed short *)DMA2_10_Y_MODIFY
-#define pDMA2_10_CURR_DESC_PTR	(volatile void **)DMA2_10_CURR_DESC_PTR
-#define pDMA2_10_CURR_ADDR	(volatile void **)DMA2_10_CURR_ADDR
-#define pDMA2_10_CURR_X_COUNT	(volatile unsigned short *)DMA2_10_CURR_X_COUNT
-#define pDMA2_10_CURR_Y_COUNT	(volatile unsigned short *)DMA2_10_CURR_Y_COUNT
-#define pDMA2_10_IRQ_STATUS	(volatile unsigned short *)DMA2_10_IRQ_STATUS
-#define pDMA2_10_PERIPHERAL_MAP (volatile unsigned short *)DMA2_10_PERIPHERAL_MAP
-#define pDMA2_11_CONFIG		(volatile unsigned short *)DMA2_11_CONFIG
-#define pDMA2_11_NEXT_DESC_PTR	(volatile void **)DMA2_11_NEXT_DESC_PTR
-#define pDMA2_11_START_ADDR	(volatile void **)DMA2_11_START_ADDR
-#define pDMA2_11_X_COUNT	(volatile unsigned short *)DMA2_11_X_COUNT
-#define pDMA2_11_Y_COUNT	(volatile unsigned short *)DMA2_11_Y_COUNT
-#define pDMA2_11_X_MODIFY	(volatile signed short *)DMA2_11_X_MODIFY
-#define pDMA2_11_Y_MODIFY	(volatile signed short *)DMA2_11_Y_MODIFY
-#define pDMA2_11_CURR_DESC_PTR	(volatile void **)DMA2_11_CURR_DESC_PTR
-#define pDMA2_11_CURR_ADDR	(volatile void **)DMA2_11_CURR_ADDR
-#define pDMA2_11_CURR_X_COUNT	(volatile unsigned short *)DMA2_11_CURR_X_COUNT
-#define pDMA2_11_CURR_Y_COUNT	(volatile unsigned short *)DMA2_11_CURR_Y_COUNT
-#define pDMA2_11_IRQ_STATUS	(volatile unsigned short *)DMA2_11_IRQ_STATUS
-#define pDMA2_11_PERIPHERAL_MAP (volatile unsigned short *)DMA2_11_PERIPHERAL_MAP
-
-/* Memory DMA2 Controller registers (0xFFC0 0E80-0xFFC0 0FFF) */
-#define pMDMA2_D0_CONFIG	(volatile unsigned short *)MDMA2_D0_CONFIG
-#define pMDMA2_D0_NEXT_DESC_PTR (volatile void **)MDMA2_D0_NEXT_DESC_PTR
-#define pMDMA2_D0_START_ADDR	(volatile void **)MDMA2_D0_START_ADDR
-#define pMDMA2_D0_X_COUNT	(volatile unsigned short *)MDMA2_D0_X_COUNT
-#define pMDMA2_D0_Y_COUNT	(volatile unsigned short *)MDMA2_D0_Y_COUNT
-#define pMDMA2_D0_X_MODIFY	(volatile signed short *)MDMA2_D0_X_MODIFY
-#define pMDMA2_D0_Y_MODIFY	(volatile signed short *)MDMA2_D0_Y_MODIFY
-#define pMDMA2_D0_CURR_DESC_PTR (volatile void **)MDMA2_D0_CURR_DESC_PTR
-#define pMDMA2_D0_CURR_ADDR	(volatile void **)MDMA2_D0_CURR_ADDR
-#define pMDMA2_D0_CURR_X_COUNT	(volatile unsigned short *)MDMA2_D0_CURR_X_COUNT
-#define pMDMA2_D0_CURR_Y_COUNT	(volatile unsigned short *)MDMA2_D0_CURR_Y_COUNT
-#define pMDMA2_D0_IRQ_STATUS	(volatile unsigned short *)MDMA2_D0_IRQ_STATUS
-#define pMDMA2_D0_PERIPHERAL_MAP (volatile unsigned short *)MDMA2_D0_PERIPHERAL_MAP
-#define pMDMA2_S0_CONFIG	(volatile unsigned short *)MDMA2_S0_CONFIG
-#define pMDMA2_S0_NEXT_DESC_PTR (volatile void **)MDMA2_S0_NEXT_DESC_PTR
-#define pMDMA2_S0_START_ADDR	(volatile void **)MDMA2_S0_START_ADDR
-#define pMDMA2_S0_X_COUNT	(volatile unsigned short *)MDMA2_S0_X_COUNT
-#define pMDMA2_S0_Y_COUNT	(volatile unsigned short *)MDMA2_S0_Y_COUNT
-#define pMDMA2_S0_X_MODIFY	(volatile signed short *)MDMA2_S0_X_MODIFY
-#define pMDMA2_S0_Y_MODIFY	(volatile signed short *)MDMA2_S0_Y_MODIFY
-#define pMDMA2_S0_CURR_DESC_PTR (volatile void **)MDMA2_S0_CURR_DESC_PTR
-#define pMDMA2_S0_CURR_ADDR	(volatile void **)MDMA2_S0_CURR_ADDR
-#define pMDMA2_S0_CURR_X_COUNT	(volatile unsigned short *)MDMA2_S0_CURR_X_COUNT
-#define pMDMA2_S0_CURR_Y_COUNT	(volatile unsigned short *)MDMA2_S0_CURR_Y_COUNT
-#define pMDMA2_S0_IRQ_STATUS	(volatile unsigned short *)MDMA2_S0_IRQ_STATUS
-#define pMDMA2_S0_PERIPHERAL_MAP (volatile unsigned short *)MDMA2_S0_PERIPHERAL_MAP
-#define pMDMA2_D1_CONFIG	(volatile unsigned short *)MDMA2_D1_CONFIG
-#define pMDMA2_D1_NEXT_DESC_PTR (volatile void **)MDMA2_D1_NEXT_DESC_PTR
-#define pMDMA2_D1_START_ADDR	(volatile void **)MDMA2_D1_START_ADDR
-#define pMDMA2_D1_X_COUNT	(volatile unsigned short *)MDMA2_D1_X_COUNT
-#define pMDMA2_D1_Y_COUNT	(volatile unsigned short *)MDMA2_D1_Y_COUNT
-#define pMDMA2_D1_X_MODIFY	(volatile signed short *)MDMA2_D1_X_MODIFY
-#define pMDMA2_D1_Y_MODIFY	(volatile signed short *)MDMA2_D1_Y_MODIFY
-#define pMDMA2_D1_CURR_DESC_PTR (volatile void **)MDMA2_D1_CURR_DESC_PTR
-#define pMDMA2_D1_CURR_ADDR	(volatile void **)MDMA2_D1_CURR_ADDR
-#define pMDMA2_D1_CURR_X_COUNT	(volatile unsigned short *)MDMA2_D1_CURR_X_COUNT
-#define pMDMA2_D1_CURR_Y_COUNT	(volatile unsigned short *)MDMA2_D1_CURR_Y_COUNT
-#define pMDMA2_D1_IRQ_STATUS	(volatile unsigned short *)MDMA2_D1_IRQ_STATUS
-#define pMDMA2_D1_PERIPHERAL_MAP (volatile unsigned short *)MDMA2_D1_PERIPHERAL_MAP
-#define pMDMA2_S1_CONFIG	(volatile unsigned short *)MDMA2_S1_CONFIG
-#define pMDMA2_S1_NEXT_DESC_PTR (volatile void **)MDMA2_S1_NEXT_DESC_PTR
-#define pMDMA2_S1_START_ADDR	(volatile void **)MDMA2_S1_START_ADDR
-#define pMDMA2_S1_X_COUNT	(volatile unsigned short *)MDMA2_S1_X_COUNT
-#define pMDMA2_S1_Y_COUNT	(volatile unsigned short *)MDMA2_S1_Y_COUNT
-#define pMDMA2_S1_X_MODIFY	(volatile signed short *)MDMA2_S1_X_MODIFY
-#define pMDMA2_S1_Y_MODIFY	(volatile signed short *)MDMA2_S1_Y_MODIFY
-#define pMDMA2_S1_CURR_DESC_PTR (volatile void **)MDMA2_S1_CURR_DESC_PTR
-#define pMDMA2_S1_CURR_ADDR	(volatile void **)MDMA2_S1_CURR_ADDR
-#define pMDMA2_S1_CURR_X_COUNT	(volatile unsigned short *)MDMA2_S1_CURR_X_COUNT
-#define pMDMA2_S1_CURR_Y_COUNT	(volatile unsigned short *)MDMA2_S1_CURR_Y_COUNT
-#define pMDMA2_S1_IRQ_STATUS	(volatile unsigned short *)MDMA2_S1_IRQ_STATUS
-#define pMDMA2_S1_PERIPHERAL_MAP (volatile unsigned short *)MDMA2_S1_PERIPHERAL_MAP
-
-/* Internal Memory DMA Registers (0xFFC0_1800 - 0xFFC0_19FF) */
-#define pIMDMA_D0_CONFIG	(volatile unsigned short *)IMDMA_D0_CONFIG
-#define pIMDMA_D0_NEXT_DESC_PTR (volatile void **)IMDMA_D0_NEXT_DESC_PTR
-#define pIMDMA_D0_START_ADDR	(volatile void **)IMDMA_D0_START_ADDR
-#define pIMDMA_D0_X_COUNT	(volatile unsigned short *)IMDMA_D0_X_COUNT
-#define pIMDMA_D0_Y_COUNT	(volatile unsigned short *)IMDMA_D0_Y_COUNT
-#define pIMDMA_D0_X_MODIFY	(volatile signed short *)IMDMA_D0_X_MODIFY
-#define pIMDMA_D0_Y_MODIFY	(volatile signed short *)IMDMA_D0_Y_MODIFY
-#define pIMDMA_D0_CURR_DESC_PTR (volatile void **)IMDMA_D0_CURR_DESC_PTR
-#define pIMDMA_D0_CURR_ADDR	(volatile void **)IMDMA_D0_CURR_ADDR
-#define pIMDMA_D0_CURR_X_COUNT	(volatile unsigned short *)IMDMA_D0_CURR_X_COUNT
-#define pIMDMA_D0_CURR_Y_COUNT	(volatile unsigned short *)IMDMA_D0_CURR_Y_COUNT
-#define pIMDMA_D0_IRQ_STATUS	(volatile unsigned short *)IMDMA_D0_IRQ_STATUS
-#define pIMDMA_S0_CONFIG	(volatile unsigned short *)IMDMA_S0_CONFIG
-#define pIMDMA_S0_NEXT_DESC_PTR (volatile void **)IMDMA_S0_NEXT_DESC_PTR
-#define pIMDMA_S0_START_ADDR	(volatile void **)IMDMA_S0_START_ADDR
-#define pIMDMA_S0_X_COUNT	(volatile unsigned short *)IMDMA_S0_X_COUNT
-#define pIMDMA_S0_Y_COUNT	(volatile unsigned short *)IMDMA_S0_Y_COUNT
-#define pIMDMA_S0_X_MODIFY	(volatile signed short *)IMDMA_S0_X_MODIFY
-#define pIMDMA_S0_Y_MODIFY	(volatile signed short *)IMDMA_S0_Y_MODIFY
-#define pIMDMA_S0_CURR_DESC_PTR (volatile void **)IMDMA_S0_CURR_DESC_PTR
-#define pIMDMA_S0_CURR_ADDR	(volatile void **)IMDMA_S0_CURR_ADDR
-#define pIMDMA_S0_CURR_X_COUNT	(volatile unsigned short *)IMDMA_S0_CURR_X_COUNT
-#define pIMDMA_S0_CURR_Y_COUNT	(volatile unsigned short *)IMDMA_S0_CURR_Y_COUNT
-#define pIMDMA_S0_IRQ_STATUS	(volatile unsigned short *)IMDMA_S0_IRQ_STATUS
-#define pIMDMA_D1_CONFIG	(volatile unsigned short *)IMDMA_D1_CONFIG
-#define pIMDMA_D1_NEXT_DESC_PTR (volatile void **)IMDMA_D1_NEXT_DESC_PTR
-#define pIMDMA_D1_START_ADDR	(volatile void **)IMDMA_D1_START_ADDR
-#define pIMDMA_D1_X_COUNT	(volatile unsigned short *)IMDMA_D1_X_COUNT
-#define pIMDMA_D1_Y_COUNT	(volatile unsigned short *)IMDMA_D1_Y_COUNT
-#define pIMDMA_D1_X_MODIFY	(volatile signed short *)IMDMA_D1_X_MODIFY
-#define pIMDMA_D1_Y_MODIFY	(volatile signed short *)IMDMA_D1_Y_MODIFY
-#define pIMDMA_D1_CURR_DESC_PTR (volatile void **)IMDMA_D1_CURR_DESC_PTR
-#define pIMDMA_D1_CURR_ADDR	(volatile void **)IMDMA_D1_CURR_ADDR
-#define pIMDMA_D1_CURR_X_COUNT	(volatile unsigned short *)IMDMA_D1_CURR_X_COUNT
-#define pIMDMA_D1_CURR_Y_COUNT	(volatile unsigned short *)IMDMA_D1_CURR_Y_COUNT
-#define pIMDMA_D1_IRQ_STATUS	(volatile unsigned short *)IMDMA_D1_IRQ_STATUS
-#define pIMDMA_S1_CONFIG	(volatile unsigned short *)IMDMA_S1_CONFIG
-#define pIMDMA_S1_NEXT_DESC_PTR (volatile void **)IMDMA_S1_NEXT_DESC_PTR
-#define pIMDMA_S1_START_ADDR	(volatile void **)IMDMA_S1_START_ADDR
-#define pIMDMA_S1_X_COUNT	(volatile unsigned short *)IMDMA_S1_X_COUNT
-#define pIMDMA_S1_Y_COUNT	(volatile unsigned short *)IMDMA_S1_Y_COUNT
-#define pIMDMA_S1_X_MODIFY	(volatile signed short *)IMDMA_S1_X_MODIFY
-#define pIMDMA_S1_Y_MODIFY	(volatile signed short *)IMDMA_S1_Y_MODIFY
-#define pIMDMA_S1_CURR_DESC_PTR (volatile void **)IMDMA_S1_CURR_DESC_PTR
-#define pIMDMA_S1_CURR_ADDR	(volatile void **)IMDMA_S1_CURR_ADDR
-#define pIMDMA_S1_CURR_X_COUNT	(volatile unsigned short *)IMDMA_S1_CURR_X_COUNT
-#define pIMDMA_S1_CURR_Y_COUNT	(volatile unsigned short *)IMDMA_S1_CURR_Y_COUNT
-#define pIMDMA_S1_IRQ_STATUS	(volatile unsigned short *)IMDMA_S1_IRQ_STATUS
-
-#if 1				/* comment by mhfan */
-/*
- * System Reset and Interrupt Controller registers for
- * core A (0xFFC0 0100-0xFFC0 01FF)
- */
-#define pSWRST			(volatile unsigned short *)SICA_SWRST
-#define pSYSCR			(volatile unsigned short *)SICA_SYSCR
-#define pRVECT			(volatile unsigned short *)SICA_RVECT
-#define pSIC_SWRST		(volatile unsigned short *)SICA_SWRST
-#define pSIC_SYSCR		(volatile unsigned short *)SICA_SYSCR
-#define pSIC_RVECT		(volatile unsigned short *)SICA_RVECT
-#define pSIC_IMASK		(volatile unsigned long *)SICA_IMASK
-#define pSIC_IAR0		((volatile unsigned long *)SICA_IAR0)
-#define pSIC_IAR1		(volatile unsigned long *)SICA_IAR1
-#define pSIC_IAR2		(volatile unsigned long *)SICA_IAR2
-#define pSIC_ISR		(volatile unsigned long *)SICA_ISR0
-#define pSIC_IWR		(volatile unsigned long *)SICA_IWR0
-
-/* Watchdog Timer registers for Core A (0xFFC0 0200-0xFFC0 02FF) */
-#define pWDOG_CTL		(volatile unsigned short *)WDOGA_CTL
-#define pWDOG_CNT		(volatile unsigned long *)WDOGA_CNT
-#define pWDOG_STAT		(volatile unsigned long *)WDOGA_STAT
-#endif /* comment by mhfan */
-
-/* Programmable Flag 0 registers (0xFFC0 0700-0xFFC0 07FF) */
-#define pFIO_FLAG_D		(volatile unsigned short *)FIO0_FLAG_D
-#define pFIO_FLAG_C		(volatile unsigned short *)FIO0_FLAG_C
-#define pFIO_FLAG_S		(volatile unsigned short *)FIO0_FLAG_S
-#define pFIO_FLAG_T		(volatile unsigned short *)FIO0_FLAG_T
-#define pFIO_MASKA_D		(volatile unsigned short *)FIO0_MASKA_D
-#define pFIO_MASKA_C		(volatile unsigned short *)FIO0_MASKA_C
-#define pFIO_MASKA_S		(volatile unsigned short *)FIO0_MASKA_S
-#define pFIO_MASKA_T		(volatile unsigned short *)FIO0_MASKA_T
-#define pFIO_MASKB_D		(volatile unsigned short *)FIO0_MASKB_D
-#define pFIO_MASKB_C		(volatile unsigned short *)FIO0_MASKB_C
-#define pFIO_MASKB_S		(volatile unsigned short *)FIO0_MASKB_S
-#define pFIO_MASKB_T		(volatile unsigned short *)FIO0_MASKB_T
-#define pFIO_DIR		(volatile unsigned short *)FIO0_DIR
-#define pFIO_POLAR		(volatile unsigned short *)FIO0_POLAR
-#define pFIO_EDGE		(volatile unsigned short *)FIO0_EDGE
-#define pFIO_BOTH		(volatile unsigned short *)FIO0_BOTH
-#define pFIO_INEN		(volatile unsigned short *)FIO0_INEN
-
-/* Parallel Peripheral Interface (PPI) 0 registers (0xFFC0 1000-0xFFC0 10FF)*/
-#define pPPI_CONTROL		(volatile unsigned short *)PPI0_CONTROL
-#define pPPI_STATUS		(volatile unsigned short *)PPI0_STATUS
-#define pPPI_COUNT		(volatile unsigned short *)PPI0_COUNT
-#define pPPI_DELAY		(volatile unsigned short *)PPI0_DELAY
-#define pPPI_FRAME		(volatile unsigned short *)PPI0_FRAME
-
-/* DMA1 Controller registers (0xFFC0 1C00-0xFFC0 1FFF) */
-#define pDMA0_CONFIG		(volatile unsigned short *)DMA1_0_CONFIG
-#define pDMA0_NEXT_DESC_PTR	(volatile void **)DMA1_0_NEXT_DESC_PTR
-#define pDMA0_START_ADDR	(volatile void **)DMA1_0_START_ADDR
-#define pDMA0_X_COUNT		(volatile unsigned short *)DMA1_0_X_COUNT
-#define pDMA0_Y_COUNT		(volatile unsigned short *)DMA1_0_Y_COUNT
-#define pDMA0_X_MODIFY		(volatile unsigned short *)DMA1_0_X_MODIFY
-#define pDMA0_Y_MODIFY		(volatile unsigned short *)DMA1_0_Y_MODIFY
-#define pDMA0_CURR_DESC_PTR	(volatile void **)DMA1_0_CURR_DESC_PTR
-#define pDMA0_CURR_ADDR		(volatile void **)DMA1_0_CURR_ADDR
-#define pDMA0_CURR_X_COUNT	(volatile unsigned short *)DMA1_0_CURR_X_COUNT
-#define pDMA0_CURR_Y_COUNT	(volatile unsigned short *)DMA1_0_CURR_Y_COUNT
-#define pDMA0_IRQ_STATUS	(volatile unsigned short *)DMA1_0_IRQ_STATUS
-#define pDMA0_PERIPHERAL_MAP	(volatile unsigned short *)DMA1_0_PERIPHERAL_MAP
-
-/* Memory DMA1 Controller registers (0xFFC0 1E80-0xFFC0 1FFF) */
-#define pMDMA_D0_CONFIG		(volatile unsigned short *)MDMA1_D0_CONFIG
-#define pMDMA_D0_NEXT_DESC_PTR	(volatile void **)MDMA1_D0_NEXT_DESC_PTR
-#define pMDMA_D0_START_ADDR	(volatile void **)MDMA1_D0_START_ADDR
-#define pMDMA_D0_X_COUNT	(volatile unsigned short *)MDMA1_D0_X_COUNT
-#define pMDMA_D0_Y_COUNT	(volatile unsigned short *)MDMA1_D0_Y_COUNT
-#define pMDMA_D0_X_MODIFY	(volatile unsigned short *)MDMA1_D0_X_MODIFY
-#define pMDMA_D0_Y_MODIFY	(volatile unsigned short *)MDMA1_D0_Y_MODIFY
-#define pMDMA_D0_CURR_DESC_PTR	(volatile void **)MDMA1_D0_CURR_DESC_PTR
-#define pMDMA_D0_CURR_ADDR	(volatile void **)MDMA1_D0_CURR_ADDR
-#define pMDMA_D0_CURR_X_COUNT	(volatile unsigned short *)MDMA1_D0_CURR_X_COUNT
-#define pMDMA_D0_CURR_Y_COUNT	(volatile unsigned short *)MDMA1_D0_CURR_Y_COUNT
-#define pMDMA_D0_IRQ_STATUS	(volatile unsigned short *)MDMA1_D0_IRQ_STATUS
-#define pMDMA_D0_PERIPHERAL_MAP (volatile unsigned short *)MDMA1_D0_PERIPHERAL_MAP
-#define pMDMA_S0_CONFIG		(volatile unsigned short *)MDMA1_S0_CONFIG
-#define pMDMA_S0_NEXT_DESC_PTR	(volatile void **)MDMA1_S0_NEXT_DESC_PTR
-#define pMDMA_S0_START_ADDR	(volatile void **)MDMA1_S0_START_ADDR
-#define pMDMA_S0_X_COUNT	(volatile unsigned short *)MDMA1_S0_X_COUNT
-#define pMDMA_S0_Y_COUNT	(volatile unsigned short *)MDMA1_S0_Y_COUNT
-#define pMDMA_S0_X_MODIFY	(volatile unsigned short *)MDMA1_S0_X_MODIFY
-#define pMDMA_S0_Y_MODIFY	(volatile unsigned short *)MDMA1_S0_Y_MODIFY
-#define pMDMA_S0_CURR_DESC_PTR	(volatile void **)MDMA1_S0_CURR_DESC_PTR
-#define pMDMA_S0_CURR_ADDR	(volatile void **)MDMA1_S0_CURR_ADDR
-#define pMDMA_S0_CURR_X_COUNT	(volatile unsigned short *)MDMA1_S0_CURR_X_COUNT
-#define pMDMA_S0_CURR_Y_COUNT	(volatile unsigned short *)MDMA1_S0_CURR_Y_COUNT
-#define pMDMA_S0_IRQ_STATUS	(volatile unsigned short *)MDMA1_S0_IRQ_STATUS
-#define pMDMA_S0_PERIPHERAL_MAP (volatile unsigned short *)MDMA1_S0_PERIPHERAL_MAP
-#define pMDMA_D1_CONFIG		(volatile unsigned short *)MDMA1_D1_CONFIG
-#define pMDMA_D1_NEXT_DESC_PTR	(volatile void **)MDMA1_D1_NEXT_DESC_PTR
-#define pMDMA_D1_START_ADDR	(volatile void **)MDMA1_D1_START_ADDR
-#define pMDMA_D1_X_COUNT	(volatile unsigned short *)MDMA1_D1_X_COUNT
-#define pMDMA_D1_Y_COUNT	(volatile unsigned short *)MDMA1_D1_Y_COUNT
-#define pMDMA_D1_X_MODIFY	(volatile unsigned short *)MDMA1_D1_X_MODIFY
-#define pMDMA_D1_Y_MODIFY	(volatile unsigned short *)MDMA1_D1_Y_MODIFY
-#define pMDMA_D1_CURR_DESC_PTR	(volatile void **)MDMA1_D1_CURR_DESC_PTR
-#define pMDMA_D1_CURR_ADDR	(volatile void **)MDMA1_D1_CURR_ADDR
-#define pMDMA_D1_CURR_X_COUNT	(volatile unsigned short *)MDMA1_D1_CURR_X_COUNT
-#define pMDMA_D1_CURR_Y_COUNT	(volatile unsigned short *)MDMA1_D1_CURR_Y_COUNT
-#define pMDMA_D1_IRQ_STATUS	(volatile unsigned short *)MDMA1_D1_IRQ_STATUS
-#define pMDMA_D1_PERIPHERAL_MAP (volatile unsigned short *)MDMA1_D1_PERIPHERAL_MAP
-#define pMDMA_S1_CONFIG		(volatile unsigned short *)MDMA1_S1_CONFIG
-#define pMDMA_S1_NEXT_DESC_PTR	(volatile void **)MDMA1_S1_NEXT_DESC_PTR
-#define pMDMA_S1_START_ADDR	(volatile void **)MDMA1_S1_START_ADDR
-#define pMDMA_S1_X_COUNT	(volatile unsigned short *)MDMA1_S1_X_COUNT
-#define pMDMA_S1_Y_COUNT	(volatile unsigned short *)MDMA1_S1_Y_COUNT
-#define pMDMA_S1_X_MODIFY	(volatile unsigned short *)MDMA1_S1_X_MODIFY
-#define pMDMA_S1_Y_MODIFY	(volatile unsigned short *)MDMA1_S1_Y_MODIFY
-#define pMDMA_S1_CURR_DESC_PTR	(volatile void **)MDMA1_S1_CURR_DESC_PTR
-#define pMDMA_S1_CURR_ADDR	(volatile void **)MDMA1_S1_CURR_ADDR
-#define pMDMA_S1_CURR_X_COUNT	(volatile unsigned short *)MDMA1_S1_CURR_X_COUNT
-#define pMDMA_S1_CURR_Y_COUNT	(volatile unsigned short *)MDMA1_S1_CURR_Y_COUNT
-#define pMDMA_S1_IRQ_STATUS	(volatile unsigned short *)MDMA1_S1_IRQ_STATUS
-#define pMDMA_S1_PERIPHERAL_MAP (volatile unsigned short *)MDMA1_S1_PERIPHERAL_MAP
-
-/* DMA2 Controller registers (0xFFC0 0C00-0xFFC0 0DFF) */
-#define pDMA1_CONFIG		(volatile unsigned short *)DMA2_0_CONFIG
-#define pDMA1_NEXT_DESC_PTR	(volatile void **)DMA2_0_NEXT_DESC_PTR
-#define pDMA1_START_ADDR	(volatile void **)DMA2_0_START_ADDR
-#define pDMA1_X_COUNT		(volatile unsigned short *)DMA2_0_X_COUNT
-#define pDMA1_Y_COUNT		(volatile unsigned short *)DMA2_0_Y_COUNT
-#define pDMA1_X_MODIFY		(volatile unsigned short *)DMA2_0_X_MODIFY
-#define pDMA1_Y_MODIFY		(volatile unsigned short *)DMA2_0_Y_MODIFY
-#define pDMA1_CURR_DESC_PTR	(volatile void **)DMA2_0_CURR_DESC_PTR
-#define pDMA1_CURR_ADDR		(volatile void **)DMA2_0_CURR_ADDR
-#define pDMA1_CURR_X_COUNT	(volatile unsigned short *)DMA2_0_CURR_X_COUNT
-#define pDMA1_CURR_Y_COUNT	(volatile unsigned short *)DMA2_0_CURR_Y_COUNT
-#define pDMA1_IRQ_STATUS	(volatile unsigned short *)DMA2_0_IRQ_STATUS
-#define pDMA1_PERIPHERAL_MAP	(volatile unsigned short *)DMA2_0_PERIPHERAL_MAP
-#define pDMA2_CONFIG		(volatile unsigned short *)DMA2_1_CONFIG
-#define pDMA2_NEXT_DESC_PTR	(volatile void **)DMA2_1_NEXT_DESC_PTR
-#define pDMA2_START_ADDR	(volatile void **)DMA2_1_START_ADDR
-#define pDMA2_X_COUNT		(volatile unsigned short *)DMA2_1_X_COUNT
-#define pDMA2_Y_COUNT		(volatile unsigned short *)DMA2_1_Y_COUNT
-#define pDMA2_X_MODIFY		(volatile unsigned short *)DMA2_1_X_MODIFY
-#define pDMA2_Y_MODIFY		(volatile unsigned short *)DMA2_1_Y_MODIFY
-#define pDMA2_CURR_DESC_PTR	(volatile void **)DMA2_1_CURR_DESC_PTR
-#define pDMA2_CURR_ADDR		(volatile void **)DMA2_1_CURR_ADDR
-#define pDMA2_CURR_X_COUNT	(volatile unsigned short *)DMA2_1_CURR_X_COUNT
-#define pDMA2_CURR_Y_COUNT	(volatile unsigned short *)DMA2_1_CURR_Y_COUNT
-#define pDMA2_IRQ_STATUS	(volatile unsigned short *)DMA2_1_IRQ_STATUS
-#define pDMA2_PERIPHERAL_MAP	(volatile unsigned short *)DMA2_1_PERIPHERAL_MAP
-#define pDMA3_CONFIG		(volatile unsigned short *)DMA2_2_CONFIG
-#define pDMA3_NEXT_DESC_PTR	(volatile void **)DMA2_2_NEXT_DESC_PTR
-#define pDMA3_START_ADDR	(volatile void **)DMA2_2_START_ADDR
-#define pDMA3_X_COUNT		(volatile unsigned short *)DMA2_2_X_COUNT
-#define pDMA3_Y_COUNT		(volatile unsigned short *)DMA2_2_Y_COUNT
-#define pDMA3_X_MODIFY		(volatile unsigned short *)DMA2_2_X_MODIFY
-#define pDMA3_Y_MODIFY		(volatile unsigned short *)DMA2_2_Y_MODIFY
-#define pDMA3_CURR_DESC_PTR	(volatile void **)DMA2_2_CURR_DESC_PTR
-#define pDMA3_CURR_ADDR		(volatile void **)DMA2_2_CURR_ADDR
-#define pDMA3_CURR_X_COUNT	(volatile unsigned short *)DMA2_2_CURR_X_COUNT
-#define pDMA3_CURR_Y_COUNT	(volatile unsigned short *)DMA2_2_CURR_Y_COUNT
-#define pDMA3_IRQ_STATUS	(volatile unsigned short *)DMA2_2_IRQ_STATUS
-#define pDMA3_PERIPHERAL_MAP	(volatile unsigned short *)DMA2_2_PERIPHERAL_MAP
-#define pDMA4_CONFIG		(volatile unsigned short *)DMA2_3_CONFIG
-#define pDMA4_NEXT_DESC_PTR	(volatile void **)DMA2_3_NEXT_DESC_PTR
-#define pDMA4_START_ADDR	(volatile void **)DMA2_3_START_ADDR
-#define pDMA4_X_COUNT		(volatile unsigned short *)DMA2_3_X_COUNT
-#define pDMA4_Y_COUNT		(volatile unsigned short *)DMA2_3_Y_COUNT
-#define pDMA4_X_MODIFY		(volatile unsigned short *)DMA2_3_X_MODIFY
-#define pDMA4_Y_MODIFY		(volatile unsigned short *)DMA2_3_Y_MODIFY
-#define pDMA4_CURR_DESC_PTR	(volatile void **)DMA2_3_CURR_DESC_PTR
-#define pDMA4_CURR_ADDR		(volatile void **)DMA2_3_CURR_ADDR
-#define pDMA4_CURR_X_COUNT	(volatile unsigned short *)DMA2_3_CURR_X_COUNT
-#define pDMA4_CURR_Y_COUNT	(volatile unsigned short *)DMA2_3_CURR_Y_COUNT
-#define pDMA4_IRQ_STATUS	(volatile unsigned short *)DMA2_3_IRQ_STATUS
-#define pDMA4_PERIPHERAL_MAP	(volatile unsigned short *)DMA2_3_PERIPHERAL_MAP
-#define pDMA5_CONFIG		(volatile unsigned short *)DMA2_4_CONFIG
-#define pDMA5_NEXT_DESC_PTR	(volatile void **)DMA2_4_NEXT_DESC_PTR
-#define pDMA5_START_ADDR	(volatile void **)DMA2_4_START_ADDR
-#define pDMA5_X_COUNT		(volatile unsigned short *)DMA2_4_X_COUNT
-#define pDMA5_Y_COUNT		(volatile unsigned short *)DMA2_4_Y_COUNT
-#define pDMA5_X_MODIFY		(volatile unsigned short *)DMA2_4_X_MODIFY
-#define pDMA5_Y_MODIFY		(volatile unsigned short *)DMA2_4_Y_MODIFY
-#define pDMA5_CURR_DESC_PTR	(volatile void **)DMA2_4_CURR_DESC_PTR
-#define pDMA5_CURR_ADDR		(volatile void **)DMA2_4_CURR_ADDR
-#define pDMA5_CURR_X_COUNT	(volatile unsigned short *)DMA2_4_CURR_X_COUNT
-#define pDMA5_CURR_Y_COUNT	(volatile unsigned short *)DMA2_4_CURR_Y_COUNT
-#define pDMA5_IRQ_STATUS	(volatile unsigned short *)DMA2_4_IRQ_STATUS
-#define pDMA5_PERIPHERAL_MAP	(volatile unsigned short *)DMA2_4_PERIPHERAL_MAP
-#define pDMA6_CONFIG		(volatile unsigned short *)DMA2_5_CONFIG
-#define pDMA6_NEXT_DESC_PTR	(volatile void **)DMA2_5_NEXT_DESC_PTR
-#define pDMA6_START_ADDR	(volatile void **)DMA2_5_START_ADDR
-#define pDMA6_X_COUNT		(volatile unsigned short *)DMA2_5_X_COUNT
-#define pDMA6_Y_COUNT		(volatile unsigned short *)DMA2_5_Y_COUNT
-#define pDMA6_X_MODIFY		(volatile unsigned short *)DMA2_5_X_MODIFY
-#define pDMA6_Y_MODIFY		(volatile unsigned short *)DMA2_5_Y_MODIFY
-#define pDMA6_CURR_DESC_PTR	(volatile void **)DMA2_5_CURR_DESC_PTR
-#define pDMA6_CURR_ADDR		(volatile void **)DMA2_5_CURR_ADDR
-#define pDMA6_CURR_X_COUNT	(volatile unsigned short *)DMA2_5_CURR_X_COUNT
-#define pDMA6_CURR_Y_COUNT	(volatile unsigned short *)DMA2_5_CURR_Y_COUNT
-#define pDMA6_IRQ_STATUS	(volatile unsigned short *)DMA2_5_IRQ_STATUS
-#define pDMA6_PERIPHERAL_MAP	(volatile unsigned short *)DMA2_5_PERIPHERAL_MAP
-#define pDMA7_CONFIG		(volatile unsigned short *)DMA2_6_CONFIG
-#define pDMA7_NEXT_DESC_PTR	(volatile void **)DMA2_6_NEXT_DESC_PTR
-#define pDMA7_START_ADDR	(volatile void **)DMA2_6_START_ADDR
-#define pDMA7_X_COUNT		(volatile unsigned short *)DMA2_6_X_COUNT
-#define pDMA7_Y_COUNT		(volatile unsigned short *)DMA2_6_Y_COUNT
-#define pDMA7_X_MODIFY		(volatile unsigned short *)DMA2_6_X_MODIFY
-#define pDMA7_Y_MODIFY		(volatile unsigned short *)DMA2_6_Y_MODIFY
-#define pDMA7_CURR_DESC_PTR	(volatile void **)DMA2_6_CURR_DESC_PTR
-#define pDMA7_CURR_ADDR		(volatile void **)DMA2_6_CURR_ADDR
-#define pDMA7_CURR_X_COUNT	(volatile unsigned short *)DMA2_6_CURR_X_COUNT
-#define pDMA7_CURR_Y_COUNT	(volatile unsigned short *)DMA2_6_CURR_Y_COUNT
-#define pDMA7_IRQ_STATUS	(volatile unsigned short *)DMA2_6_IRQ_STATUS
-#define pDMA7_PERIPHERAL_MAP	(volatile unsigned short *)DMA2_6_PERIPHERAL_MAP
-
-#endif /* _CDEF_BF561_H */
diff --git a/arch/blackfin/include/asm/cpu/cdef_LPBlackfin.h b/arch/blackfin/include/asm/cpu/cdef_LPBlackfin.h
deleted file mode 100644
index e6471cbcb3..0000000000
--- a/arch/blackfin/include/asm/cpu/cdef_LPBlackfin.h
+++ /dev/null
@@ -1,185 +0,0 @@
-/*
- * cdef_LPBlackfin.h
- *
- * This file is subject to the terms and conditions of the GNU Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Non-GPL License also available as part of VisualDSP++
- *
- * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html
- *
- * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved
- *
- * This file under source code control, please send bugs or changes to:
- * dsptools.support@xxxxxxxxxx
- *
- */
-
-#ifndef _CDEF_LPBLACKFIN_H
-#define _CDEF_LPBLACKFIN_H
-
-/*
- * #if !defined(__ADSPLPBLACKFIN__)
- * #warning cdef_LPBlackfin.h should only be included for 532 compatible chips.
- * #endif
- */
-#include <asm/cpu/def_LPBlackfin.h>
-
-/* Cache & SRAM Memory */
-#define pSRAM_BASE_ADDRESS ((volatile void **)SRAM_BASE_ADDRESS)
-#define pDMEM_CONTROL ((volatile unsigned long *)DMEM_CONTROL)
-#define pDCPLB_STATUS ((volatile unsigned long *)DCPLB_STATUS)
-#define pDCPLB_FAULT_ADDR ((volatile void **)DCPLB_FAULT_ADDR)
-
-/* #define MMR_TIMEOUT 0xFFE00010 */	/* Memory-Mapped Register Timeout Register */
-#define pDCPLB_ADDR0 ((volatile void **)DCPLB_ADDR0)
-#define pDCPLB_ADDR1 ((volatile void **)DCPLB_ADDR1)
-#define pDCPLB_ADDR2 ((volatile void **)DCPLB_ADDR2)
-#define pDCPLB_ADDR3 ((volatile void **)DCPLB_ADDR3)
-#define pDCPLB_ADDR4 ((volatile void **)DCPLB_ADDR4)
-#define pDCPLB_ADDR5 ((volatile void **)DCPLB_ADDR5)
-#define pDCPLB_ADDR6 ((volatile void **)DCPLB_ADDR6)
-#define pDCPLB_ADDR7 ((volatile void **)DCPLB_ADDR7)
-#define pDCPLB_ADDR8 ((volatile void **)DCPLB_ADDR8)
-#define pDCPLB_ADDR9 ((volatile void **)DCPLB_ADDR9)
-#define pDCPLB_ADDR10 ((volatile void **)DCPLB_ADDR10)
-#define pDCPLB_ADDR11 ((volatile void **)DCPLB_ADDR11)
-#define pDCPLB_ADDR12 ((volatile void **)DCPLB_ADDR12)
-#define pDCPLB_ADDR13 ((volatile void **)DCPLB_ADDR13)
-#define pDCPLB_ADDR14 ((volatile void **)DCPLB_ADDR14)
-#define pDCPLB_ADDR15 ((volatile void **)DCPLB_ADDR15)
-#define pDCPLB_DATA0 ((volatile unsigned long *)DCPLB_DATA0)
-#define pDCPLB_DATA1 ((volatile unsigned long *)DCPLB_DATA1)
-#define pDCPLB_DATA2 ((volatile unsigned long *)DCPLB_DATA2)
-#define pDCPLB_DATA3 ((volatile unsigned long *)DCPLB_DATA3)
-#define pDCPLB_DATA4 ((volatile unsigned long *)DCPLB_DATA4)
-#define pDCPLB_DATA5 ((volatile unsigned long *)DCPLB_DATA5)
-#define pDCPLB_DATA6 ((volatile unsigned long *)DCPLB_DATA6)
-#define pDCPLB_DATA7 ((volatile unsigned long *)DCPLB_DATA7)
-#define pDCPLB_DATA8 ((volatile unsigned long *)DCPLB_DATA8)
-#define pDCPLB_DATA9 ((volatile unsigned long *)DCPLB_DATA9)
-#define pDCPLB_DATA10 ((volatile unsigned long *)DCPLB_DATA10)
-#define pDCPLB_DATA11 ((volatile unsigned long *)DCPLB_DATA11)
-#define pDCPLB_DATA12 ((volatile unsigned long *)DCPLB_DATA12)
-#define pDCPLB_DATA13 ((volatile unsigned long *)DCPLB_DATA13)
-#define pDCPLB_DATA14 ((volatile unsigned long *)DCPLB_DATA14)
-#define pDCPLB_DATA15 ((volatile unsigned long *)DCPLB_DATA15)
-#define pDTEST_COMMAND ((volatile unsigned long *)DTEST_COMMAND)
-
-/* #define DTEST_INDEX            0xFFE00304 */ 	/* Data Test Index Register */
-#define pDTEST_DATA0 ((volatile unsigned long *)DTEST_DATA0)
-#define pDTEST_DATA1 ((volatile unsigned long *)DTEST_DATA1)
-
-/*
- * # define DTEST_DATA2	0xFFE00408   Data Test Data Register
- * #define DTEST_DATA3	0xFFE0040C   Data Test Data Register
- */
-#define pIMEM_CONTROL ((volatile unsigned long *)IMEM_CONTROL)
-#define pICPLB_STATUS ((volatile unsigned long *)ICPLB_STATUS)
-#define pICPLB_FAULT_ADDR ((volatile void **)ICPLB_FAULT_ADDR)
-#define pICPLB_ADDR0 ((volatile void **)ICPLB_ADDR0)
-#define pICPLB_ADDR1 ((volatile void **)ICPLB_ADDR1)
-#define pICPLB_ADDR2 ((volatile void **)ICPLB_ADDR2)
-#define pICPLB_ADDR3 ((volatile void **)ICPLB_ADDR3)
-#define pICPLB_ADDR4 ((volatile void **)ICPLB_ADDR4)
-#define pICPLB_ADDR5 ((volatile void **)ICPLB_ADDR5)
-#define pICPLB_ADDR6 ((volatile void **)ICPLB_ADDR6)
-#define pICPLB_ADDR7 ((volatile void **)ICPLB_ADDR7)
-#define pICPLB_ADDR8 ((volatile void **)ICPLB_ADDR8)
-#define pICPLB_ADDR9 ((volatile void **)ICPLB_ADDR9)
-#define pICPLB_ADDR10 ((volatile void **)ICPLB_ADDR10)
-#define pICPLB_ADDR11 ((volatile void **)ICPLB_ADDR11)
-#define pICPLB_ADDR12 ((volatile void **)ICPLB_ADDR12)
-#define pICPLB_ADDR13 ((volatile void **)ICPLB_ADDR13)
-#define pICPLB_ADDR14 ((volatile void **)ICPLB_ADDR14)
-#define pICPLB_ADDR15 ((volatile void **)ICPLB_ADDR15)
-#define pICPLB_DATA0 ((volatile unsigned long *)ICPLB_DATA0)
-#define pICPLB_DATA1 ((volatile unsigned long *)ICPLB_DATA1)
-#define pICPLB_DATA2 ((volatile unsigned long *)ICPLB_DATA2)
-#define pICPLB_DATA3 ((volatile unsigned long *)ICPLB_DATA3)
-#define pICPLB_DATA4 ((volatile unsigned long *)ICPLB_DATA4)
-#define pICPLB_DATA5 ((volatile unsigned long *)ICPLB_DATA5)
-#define pICPLB_DATA6 ((volatile unsigned long *)ICPLB_DATA6)
-#define pICPLB_DATA7 ((volatile unsigned long *)ICPLB_DATA7)
-#define pICPLB_DATA8 ((volatile unsigned long *)ICPLB_DATA8)
-#define pICPLB_DATA9 ((volatile unsigned long *)ICPLB_DATA9)
-#define pICPLB_DATA10 ((volatile unsigned long *)ICPLB_DATA10)
-#define pICPLB_DATA11 ((volatile unsigned long *)ICPLB_DATA11)
-#define pICPLB_DATA12 ((volatile unsigned long *)ICPLB_DATA12)
-#define pICPLB_DATA13 ((volatile unsigned long *)ICPLB_DATA13)
-#define pICPLB_DATA14 ((volatile unsigned long *)ICPLB_DATA14)
-#define pICPLB_DATA15 ((volatile unsigned long *)ICPLB_DATA15)
-#define pITEST_COMMAND ((volatile unsigned long *)ITEST_COMMAND)
-
-/* #define ITEST_INDEX 0xFFE01304 */	/* Instruction Test Index Register */
-#define pITEST_DATA0 ((volatile unsigned long *)ITEST_DATA0)
-#define pITEST_DATA1 ((volatile unsigned long *)ITEST_DATA1)
-
-/* Event/Interrupt Registers */
-#define pEVT0 ((volatile void **)EVT0)
-#define pEVT1 ((volatile void **)EVT1)
-#define pEVT2 ((volatile void **)EVT2)
-#define pEVT3 ((volatile void **)EVT3)
-#define pEVT4 ((volatile void **)EVT4)
-#define pEVT5 ((volatile void **)EVT5)
-#define pEVT6 ((volatile void **)EVT6)
-#define pEVT7 ((volatile void **)EVT7)
-#define pEVT8 ((volatile void **)EVT8)
-#define pEVT9 ((volatile void **)EVT9)
-#define pEVT10 ((volatile void **)EVT10)
-#define pEVT11 ((volatile void **)EVT11)
-#define pEVT12 ((volatile void **)EVT12)
-#define pEVT13 ((volatile void **)EVT13)
-#define pEVT14 ((volatile void **)EVT14)
-#define pEVT15 ((volatile void **)EVT15)
-#define pIMASK ((volatile unsigned long *)IMASK)
-#define pIPEND ((volatile unsigned long *)IPEND)
-#define pILAT ((volatile unsigned long *)ILAT)
-
-/* Core Timer Registers */
-#define pTCNTL ((volatile unsigned long *)TCNTL)
-#define pTPERIOD ((volatile unsigned long *)TPERIOD)
-#define pTSCALE ((volatile unsigned long *)TSCALE)
-#define pTCOUNT ((volatile unsigned long *)TCOUNT)
-
-/* Debug/MP/Emulation Registers */
-#define pDSPID ((volatile unsigned long *)DSPID)
-#define pDBGCTL ((volatile unsigned long *)DBGCTL)
-#define pDBGSTAT ((volatile unsigned long *)DBGSTAT)
-#define pEMUDAT ((volatile unsigned long *)EMUDAT)
-
-/* Trace Buffer Registers */
-#define pTBUFCTL ((volatile unsigned long *)TBUFCTL)
-#define pTBUFSTAT ((volatile unsigned long *)TBUFSTAT)
-#define pTBUF ((volatile void **)TBUF)
-
-/* Watch Point Control Registers */
-#define pWPIACTL ((volatile unsigned long *)WPIACTL)
-#define pWPIA0 ((volatile void **)WPIA0)
-#define pWPIA1 ((volatile void **)WPIA1)
-#define pWPIA2 ((volatile void **)WPIA2)
-#define pWPIA3 ((volatile void **)WPIA3)
-#define pWPIA4 ((volatile void **)WPIA4)
-#define pWPIA5 ((volatile void **)WPIA5)
-#define pWPIACNT0 ((volatile unsigned long *)WPIACNT0)
-#define pWPIACNT1 ((volatile unsigned long *)WPIACNT1)
-#define pWPIACNT2 ((volatile unsigned long *)WPIACNT2)
-#define pWPIACNT3 ((volatile unsigned long *)WPIACNT3)
-#define pWPIACNT4 ((volatile unsigned long *)WPIACNT4)
-#define pWPIACNT5 ((volatile unsigned long *)WPIACNT5)
-#define pWPDACTL ((volatile unsigned long *)WPDACTL)
-#define pWPDA0 ((volatile void **)WPDA0)
-#define pWPDA1 ((volatile void **)WPDA1)
-#define pWPDACNT0 ((volatile unsigned long *)WPDACNT0)
-#define pWPDACNT1 ((volatile unsigned long *)WPDACNT1)
-#define pWPSTAT ((volatile unsigned long *)WPSTAT)
-
-/* Performance Monitor Registers */
-#define pPFCTL ((volatile unsigned long *)PFCTL)
-#define pPFCNTR0 ((volatile unsigned long *)PFCNTR0)
-#define pPFCNTR1 ((volatile unsigned long *)PFCNTR1)
-
-/* #define IPRIO 0xFFE02110 */ /* Core Interrupt Priority Register */
-
-#endif	/* _CDEF_LPBLACKFIN_H */
diff --git a/arch/blackfin/include/asm/cpu/defBF531.h b/arch/blackfin/include/asm/cpu/defBF531.h
deleted file mode 100644
index 6c7cd5a6db..0000000000
--- a/arch/blackfin/include/asm/cpu/defBF531.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * defBF531.h
- *
- * This file is subject to the terms and conditions of the GNU Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Non-GPL License also available as part of VisualDSP++
- *
- * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html
- *
- * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved
- *
- * This file under source code control, please send bugs or changes to:
- * dsptools.support@xxxxxxxxxx
- *
- */
-
-#ifndef _DEFBF531_H
-#define _DEFBF531_H
-
-#include <defBF532.h>
-
-#endif /* _DEFBF531_H */
diff --git a/arch/blackfin/include/asm/cpu/defBF532.h b/arch/blackfin/include/asm/cpu/defBF532.h
deleted file mode 100644
index 65853ed434..0000000000
--- a/arch/blackfin/include/asm/cpu/defBF532.h
+++ /dev/null
@@ -1,1148 +0,0 @@
-/*
- * defBF532.h
- *
- * This file is subject to the terms and conditions of the GNU Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Non-GPL License also available as part of VisualDSP++
- *
- * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html
- *
- * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved
- *
- * This file under source code control, please send bugs or changes to:
- * dsptools.support@xxxxxxxxxx
- *
- */
-
-/* SYSTEM & MM REGISTER BIT & ADDRESS DEFINITIONS FOR ADSP-BF532 */
-
-#ifndef _DEF_BF532_H
-#define _DEF_BF532_H
-
-/*
- * #if !defined(__ADSPLPBLACKFIN__)
- * #warning defBF532.h should only be included for 532 compatible chips
- * #endif
- */
-
-/* include all Core registers and bit definitions */
-#include <asm/cpu/def_LPBlackfin.h>
-
-/*
- * System MMR Register Map
- */
-
-/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
-#define PLL_CTL			0xFFC00000	/* PLL Control register (16-bit) */
-#define PLL_DIV			0xFFC00004	/* PLL Divide Register (16-bit) */
-#define VR_CTL			0xFFC00008	/* Voltage Regulator Control Register (16-bit) */
-#define PLL_STAT		0xFFC0000C	/* PLL Status register (16-bit) */
-#define PLL_LOCKCNT		0xFFC00010	/* PLL Lock Count register (16-bit) */
-#define	CHIPID			0xFFC00014	/* Chip ID register (32-bit)	*/
-#define SWRST			0xFFC00100	/* Software Reset Register (16-bit) */
-#define SYSCR			0xFFC00104	/* System Configuration register */
-
-/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
-#define SIC_RVECT		0xFFC00108	/* Interrupt Reset Vector Address Register */
-#define SIC_IMASK		0xFFC0010C	/* Interrupt Mask Register */
-#define SIC_IAR0		0xFFC00110	/* Interrupt Assignment Register 0 */
-#define SIC_IAR1		0xFFC00114	/* Interrupt Assignment Register 1 */
-#define SIC_IAR2		0xFFC00118	/* Interrupt Assignment Register 2 */
-#define SIC_ISR			0xFFC00120	/* Interrupt Status Register */
-#define SIC_IWR			0xFFC00124	/* Interrupt Wakeup Register */
-
-/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
-#define WDOG_CTL		0xFFC00200	/* Watchdog Control Register */
-#define WDOG_CNT		0xFFC00204	/* Watchdog Count Register */
-#define WDOG_STAT		0xFFC00208	/* Watchdog Status Register */
-
-/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
-#define RTC_STAT		0xFFC00300	/* RTC Status Register */
-#define RTC_ICTL		0xFFC00304	/* RTC Interrupt Control Register */
-#define RTC_ISTAT		0xFFC00308	/* RTC Interrupt Status Register */
-#define RTC_SWCNT		0xFFC0030C	/* RTC Stopwatch Count Register */
-#define RTC_ALARM		0xFFC00310	/* RTC Alarm Time Register */
-#define RTC_FAST		0xFFC00314	/* RTC Prescaler Enable Register */
-#define RTC_PREN		0xFFC00314	/* RTC Prescaler Enable Register (alternate macro) */
-
-/* UART Controller (0xFFC00400 - 0xFFC004FF) */
-#define UART_THR		0xFFC00400	/* Transmit Holding register */
-#define UART_RBR		0xFFC00400	/* Receive Buffer register */
-#define UART_DLL		0xFFC00400	/* Divisor Latch (Low-Byte) */
-#define UART_IER		0xFFC00404	/* Interrupt Enable Register */
-#define UART_DLH		0xFFC00404	/* Divisor Latch (High-Byte) */
-#define UART_IIR		0xFFC00408	/* Interrupt Identification Register */
-#define UART_LCR		0xFFC0040C	/* Line Control Register */
-#define UART_MCR		0xFFC00410	/* Modem Control Register */
-#define UART_LSR		0xFFC00414	/* Line Status Register */
-/* #define UART_MSR 0xFFC00418 */	/* Modem Status Register (UNUSED in ADSP-BF532) */
-#define UART_SCR		0xFFC0041C	/* SCR Scratch Register */
-#define UART_GCTL		0xFFC00424	/* Global Control Register */
-
-/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
-#define SPI_CTL			0xFFC00500	/* SPI Control Register */
-#define SPI_FLG			0xFFC00504	/* SPI Flag register */
-#define SPI_STAT		0xFFC00508	/* SPI Status register */
-#define SPI_TDBR		0xFFC0050C	/* SPI Transmit Data Buffer Register */
-#define SPI_RDBR		0xFFC00510	/* SPI Receive Data Buffer Register */
-#define SPI_BAUD		0xFFC00514	/* SPI Baud rate Register */
-#define SPI_SHADOW		0xFFC00518	/* SPI_RDBR Shadow Register */
-
-/* TIMER 0, 1, 2 Registers (0xFFC00600 - 0xFFC006FF) */
-#define TIMER0_CONFIG		0xFFC00600	/* Timer 0 Configuration Register */
-#define TIMER0_COUNTER		0xFFC00604	/* Timer 0 Counter Register */
-#define TIMER0_PERIOD		0xFFC00608	/* Timer 0 Period Register */
-#define TIMER0_WIDTH		0xFFC0060C	/* Timer 0 Width Register */
-
-#define TIMER1_CONFIG		0xFFC00610	/*  Timer 1 Configuration Register */
-#define TIMER1_COUNTER		0xFFC00614	/*  Timer 1 Counter Register */
-#define TIMER1_PERIOD		0xFFC00618	/*  Timer 1 Period Register */
-#define TIMER1_WIDTH		0xFFC0061C	/*  Timer 1 Width Register */
-
-#define TIMER2_CONFIG		0xFFC00620	/* Timer 2 Configuration Register */
-#define TIMER2_COUNTER		0xFFC00624	/* Timer 2 Counter Register */
-#define TIMER2_PERIOD		0xFFC00628	/* Timer 2 Period Register */
-#define TIMER2_WIDTH		0xFFC0062C	/* Timer 2 Width Register */
-
-#define TIMER_ENABLE		0xFFC00640	/* Timer Enable Register */
-#define TIMER_DISABLE		0xFFC00644	/* Timer Disable Register */
-#define TIMER_STATUS		0xFFC00648	/* Timer Status Register */
-
-/* General Purpose IO (0xFFC00700 - 0xFFC007FF) */
-#define FIO_FLAG_D		0xFFC00700	/* Flag Mask to directly specify state of pins */
-#define FIO_FLAG_C		0xFFC00704	/* Peripheral Interrupt Flag Register (clear) */
-#define FIO_FLAG_S		0xFFC00708	/* Peripheral Interrupt Flag Register (set) */
-#define FIO_FLAG_T		0xFFC0070C	/* Flag Mask to directly toggle state of pins */
-#define FIO_MASKA_D		0xFFC00710	/* Flag Mask Interrupt A Register (set directly) */
-#define FIO_MASKA_C		0xFFC00714	/* Flag Mask Interrupt A Register (clear) */
-#define FIO_MASKA_S		0xFFC00718	/* Flag Mask Interrupt A Register (set) */
-#define FIO_MASKA_T		0xFFC0071C	/* Flag Mask Interrupt A Register (toggle) */
-#define FIO_MASKB_D		0xFFC00720	/* Flag Mask Interrupt B Register (set directly) */
-#define FIO_MASKB_C		0xFFC00724	/* Flag Mask Interrupt B Register (clear) */
-#define FIO_MASKB_S		0xFFC00728	/* Flag Mask Interrupt B Register (set) */
-#define FIO_MASKB_T		0xFFC0072C	/* Flag Mask Interrupt B Register (toggle) */
-#define FIO_DIR			0xFFC00730	/* Peripheral Flag Direction Register */
-#define FIO_POLAR		0xFFC00734	/* Flag Source Polarity Register */
-#define FIO_EDGE		0xFFC00738	/* Flag Source Sensitivity Register */
-#define FIO_BOTH		0xFFC0073C	/* Flag Set on BOTH Edges Register */
-#define FIO_INEN		0xFFC00740	/* Flag Input Enable Register */
-
-/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
-#define SPORT0_TCR1		0xFFC00800	/* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_TCR2		0xFFC00804	/* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_TCLKDIV		0xFFC00808	/* SPORT0 Transmit Clock Divider */
-#define SPORT0_TFSDIV		0xFFC0080C	/* SPORT0 Transmit Frame Sync Divider */
-#define SPORT0_TX		0xFFC00810	/* SPORT0 TX Data Register */
-#define SPORT0_RX		0xFFC00818	/* SPORT0 RX Data Register */
-#define SPORT0_RCR1		0xFFC00820	/* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_RCR2		0xFFC00824	/* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_RCLKDIV		0xFFC00828	/* SPORT0 Receive Clock Divider */
-#define SPORT0_RFSDIV		0xFFC0082C	/* SPORT0 Receive Frame Sync Divider */
-#define SPORT0_STAT		0xFFC00830	/* SPORT0 Status Register */
-#define SPORT0_CHNL		0xFFC00834	/* SPORT0 Current Channel Register */
-#define SPORT0_MCMC1		0xFFC00838	/* SPORT0 Multi-Channel Configuration Register 1 */
-#define SPORT0_MCMC2		0xFFC0083C	/* SPORT0 Multi-Channel Configuration Register 2 */
-#define SPORT0_MTCS0		0xFFC00840	/* SPORT0 Multi-Channel Transmit Select Register 0 */
-#define SPORT0_MTCS1		0xFFC00844	/* SPORT0 Multi-Channel Transmit Select Register 1 */
-#define SPORT0_MTCS2		0xFFC00848	/* SPORT0 Multi-Channel Transmit Select Register 2 */
-#define SPORT0_MTCS3		0xFFC0084C	/* SPORT0 Multi-Channel Transmit Select Register 3 */
-#define SPORT0_MRCS0		0xFFC00850	/* SPORT0 Multi-Channel Receive Select Register 0 */
-#define SPORT0_MRCS1		0xFFC00854	/* SPORT0 Multi-Channel Receive Select Register 1 */
-#define SPORT0_MRCS2		0xFFC00858	/* SPORT0 Multi-Channel Receive Select Register 2 */
-#define SPORT0_MRCS3		0xFFC0085C	/* SPORT0 Multi-Channel Receive Select Register 3 */
-
-/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
-#define SPORT1_TCR1		0xFFC00900	/* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_TCR2		0xFFC00904	/* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_TCLKDIV		0xFFC00908	/* SPORT1 Transmit Clock Divider */
-#define SPORT1_TFSDIV		0xFFC0090C	/* SPORT1 Transmit Frame Sync Divider */
-#define SPORT1_TX		0xFFC00910	/* SPORT1 TX Data Register */
-#define SPORT1_RX		0xFFC00918	/* SPORT1 RX Data Register */
-#define SPORT1_RCR1		0xFFC00920	/* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_RCR2		0xFFC00924	/* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_RCLKDIV		0xFFC00928	/* SPORT1 Receive Clock Divider */
-#define SPORT1_RFSDIV		0xFFC0092C	/* SPORT1 Receive Frame Sync Divider */
-#define SPORT1_STAT		0xFFC00930	/* SPORT1 Status Register */
-#define SPORT1_CHNL		0xFFC00934	/* SPORT1 Current Channel Register */
-#define SPORT1_MCMC1		0xFFC00938	/* SPORT1 Multi-Channel Configuration Register 1 */
-#define SPORT1_MCMC2		0xFFC0093C	/* SPORT1 Multi-Channel Configuration Register 2 */
-#define SPORT1_MTCS0		0xFFC00940	/* SPORT1 Multi-Channel Transmit Select Register 0 */
-#define SPORT1_MTCS1		0xFFC00944	/* SPORT1 Multi-Channel Transmit Select Register 1 */
-#define SPORT1_MTCS2		0xFFC00948	/* SPORT1 Multi-Channel Transmit Select Register 2 */
-#define SPORT1_MTCS3		0xFFC0094C	/* SPORT1 Multi-Channel Transmit Select Register 3 */
-#define SPORT1_MRCS0		0xFFC00950	/* SPORT1 Multi-Channel Receive Select Register 0 */
-#define SPORT1_MRCS1		0xFFC00954	/* SPORT1 Multi-Channel Receive Select Register 1 */
-#define SPORT1_MRCS2		0xFFC00958	/* SPORT1 Multi-Channel Receive Select Register 2 */
-#define SPORT1_MRCS3		0xFFC0095C	/* SPORT1 Multi-Channel Receive Select Register 3 */
-
-/* Asynchronous Memory Controller - External Bus Interface Unit */
-#define EBIU_AMGCTL		0xFFC00A00	/* Asynchronous Memory Global Control Register */
-#define EBIU_AMBCTL0		0xFFC00A04	/* Asynchronous Memory Bank Control Register 0 */
-#define EBIU_AMBCTL1		0xFFC00A08	/* Asynchronous Memory Bank Control Register 1 */
-
-/* SDRAM Controller External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
-#define EBIU_SDGCTL		0xFFC00A10	/* SDRAM Global Control Register */
-#define EBIU_SDBCTL		0xFFC00A14	/* SDRAM Bank Control Register */
-#define EBIU_SDRRC		0xFFC00A18	/* SDRAM Refresh Rate Control Register */
-#define EBIU_SDSTAT		0xFFC00A1C	/* SDRAM Status Register */
-
-/* DMA Test Registers */
-#define DMA_CCOMP		0xFFC00B04	/* DMA Cycle Count Register */
-#define DMA_ACOMP		0xFFC00B00	/* Debug Compare Address Register */
-#define DMA_MISR		0xFFC00B08	/* MISR Register */
-#define DMA_TCPER		0xFFC00B0C	/* Traffic Control Periods Register */
-#define DMA_TCCNT		0xFFC00B10	/* Traffic Control Current Counts Register */
-#define DMA_TMODE		0xFFC00B14	/* DMA Test Modes Register */
-#define DMA_TMCHAN		0xFFC00B18	/* DMA Testmode Selected Channel Register */
-#define DMA_TMSTAT		0xFFC00B1C	/* DMA Testmode Channel Status Register */
-#define DMA_TMBD		0xFFC00B20	/* DMA Testmode DAB Bus Data Register */
-#define DMA_TMM0D		0xFFC00B24	/* DMA Testmode Mem0 Data Register */
-#define DMA_TMM1D		0xFFC00B28	/* DMA Testmode Mem1 Data Register */
-#define DMA_TMMA		0xFFC00B2C	/* DMA Testmode Memory Address Register */
-
-/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */
-#define DMA0_CONFIG		0xFFC00C08	/* DMA Channel 0 Configuration Register */
-#define DMA0_NEXT_DESC_PTR	0xFFC00C00	/* DMA Channel 0 Next Descriptor Pointer Register */
-#define DMA0_START_ADDR		0xFFC00C04	/* DMA Channel 0 Start Address Register */
-#define DMA0_X_COUNT		0xFFC00C10	/* DMA Channel 0 X Count Register */
-#define DMA0_Y_COUNT		0xFFC00C18	/* DMA Channel 0 Y Count Register */
-#define DMA0_X_MODIFY		0xFFC00C14	/* DMA Channel 0 X Modify Register */
-#define DMA0_Y_MODIFY		0xFFC00C1C	/* DMA Channel 0 Y Modify Register */
-#define DMA0_CURR_DESC_PTR	0xFFC00C20	/* DMA Channel 0 Current Descriptor Pointer Register */
-#define DMA0_CURR_ADDR		0xFFC00C24	/* DMA Channel 0 Current Address Register */
-#define DMA0_CURR_X_COUNT	0xFFC00C30	/* DMA Channel 0 Current X Count Register */
-#define DMA0_CURR_Y_COUNT	0xFFC00C38	/* DMA Channel 0 Current Y Count Register */
-#define DMA0_IRQ_STATUS		0xFFC00C28	/* DMA Channel 0 Interrupt/Status Register */
-#define DMA0_PERIPHERAL_MAP	0xFFC00C2C	/* DMA Channel 0 Peripheral Map Register */
-
-#define DMA1_CONFIG		0xFFC00C48	/* DMA Channel 1 Configuration Register */
-#define DMA1_NEXT_DESC_PTR	0xFFC00C40	/* DMA Channel 1 Next Descriptor Pointer Register */
-#define DMA1_START_ADDR		0xFFC00C44	/* DMA Channel 1 Start Address Register */
-#define DMA1_X_COUNT		0xFFC00C50	/* DMA Channel 1 X Count Register */
-#define DMA1_Y_COUNT		0xFFC00C58	/* DMA Channel 1 Y Count Register */
-#define DMA1_X_MODIFY		0xFFC00C54	/* DMA Channel 1 X Modify Register */
-#define DMA1_Y_MODIFY		0xFFC00C5C	/* DMA Channel 1 Y Modify Register */
-#define DMA1_CURR_DESC_PTR	0xFFC00C60	/* DMA Channel 1 Current Descriptor Pointer Register */
-#define DMA1_CURR_ADDR		0xFFC00C64	/* DMA Channel 1 Current Address Register */
-#define DMA1_CURR_X_COUNT	0xFFC00C70	/* DMA Channel 1 Current X Count Register */
-#define DMA1_CURR_Y_COUNT	0xFFC00C78	/* DMA Channel 1 Current Y Count Register */
-#define DMA1_IRQ_STATUS		0xFFC00C68	/* DMA Channel 1 Interrupt/Status Register */
-#define DMA1_PERIPHERAL_MAP	0xFFC00C6C	/* DMA Channel 1 Peripheral Map Register */
-
-#define DMA2_CONFIG		0xFFC00C88	/* DMA Channel 2 Configuration Register */
-#define DMA2_NEXT_DESC_PTR	0xFFC00C80	/* DMA Channel 2 Next Descriptor Pointer Register */
-#define DMA2_START_ADDR		0xFFC00C84	/* DMA Channel 2 Start Address Register */
-#define DMA2_X_COUNT		0xFFC00C90	/* DMA Channel 2 X Count Register */
-#define DMA2_Y_COUNT		0xFFC00C98	/* DMA Channel 2 Y Count Register */
-#define DMA2_X_MODIFY		0xFFC00C94	/* DMA Channel 2 X Modify Register */
-#define DMA2_Y_MODIFY		0xFFC00C9C	/* DMA Channel 2 Y Modify Register */
-#define DMA2_CURR_DESC_PTR	0xFFC00CA0	/* DMA Channel 2 Current Descriptor Pointer Register */
-#define DMA2_CURR_ADDR		0xFFC00CA4	/* DMA Channel 2 Current Address Register */
-#define DMA2_CURR_X_COUNT	0xFFC00CB0	/* DMA Channel 2 Current X Count Register */
-#define DMA2_CURR_Y_COUNT	0xFFC00CB8	/* DMA Channel 2 Current Y Count Register */
-#define DMA2_IRQ_STATUS		0xFFC00CA8	/* DMA Channel 2 Interrupt/Status Register */
-#define DMA2_PERIPHERAL_MAP	0xFFC00CAC	/* DMA Channel 2 Peripheral Map Register */
-
-#define DMA3_CONFIG		0xFFC00CC8	/* DMA Channel 3 Configuration Register */
-#define DMA3_NEXT_DESC_PTR	0xFFC00CC0	/* DMA Channel 3 Next Descriptor Pointer Register */
-#define DMA3_START_ADDR		0xFFC00CC4	/* DMA Channel 3 Start Address Register */
-#define DMA3_X_COUNT		0xFFC00CD0	/* DMA Channel 3 X Count Register */
-#define DMA3_Y_COUNT		0xFFC00CD8	/* DMA Channel 3 Y Count Register */
-#define DMA3_X_MODIFY		0xFFC00CD4	/* DMA Channel 3 X Modify Register */
-#define DMA3_Y_MODIFY		0xFFC00CDC	/* DMA Channel 3 Y Modify Register */
-#define DMA3_CURR_DESC_PTR	0xFFC00CE0	/* DMA Channel 3 Current Descriptor Pointer Register */
-#define DMA3_CURR_ADDR		0xFFC00CE4	/* DMA Channel 3 Current Address Register */
-#define DMA3_CURR_X_COUNT	0xFFC00CF0	/* DMA Channel 3 Current X Count Register */
-#define DMA3_CURR_Y_COUNT	0xFFC00CF8	/* DMA Channel 3 Current Y Count Register */
-#define DMA3_IRQ_STATUS		0xFFC00CE8	/* DMA Channel 3 Interrupt/Status Register */
-#define DMA3_PERIPHERAL_MAP	0xFFC00CEC	/* DMA Channel 3 Peripheral Map Register */
-
-#define DMA4_CONFIG		0xFFC00D08	/* DMA Channel 4 Configuration Register */
-#define DMA4_NEXT_DESC_PTR	0xFFC00D00	/* DMA Channel 4 Next Descriptor Pointer Register */
-#define DMA4_START_ADDR		0xFFC00D04	/* DMA Channel 4 Start Address Register */
-#define DMA4_X_COUNT		0xFFC00D10	/* DMA Channel 4 X Count Register */
-#define DMA4_Y_COUNT		0xFFC00D18	/* DMA Channel 4 Y Count Register */
-#define DMA4_X_MODIFY		0xFFC00D14	/* DMA Channel 4 X Modify Register */
-#define DMA4_Y_MODIFY		0xFFC00D1C	/* DMA Channel 4 Y Modify Register */
-#define DMA4_CURR_DESC_PTR	0xFFC00D20	/* DMA Channel 4 Current Descriptor Pointer Register */
-#define DMA4_CURR_ADDR		0xFFC00D24	/* DMA Channel 4 Current Address Register */
-#define DMA4_CURR_X_COUNT	0xFFC00D30	/* DMA Channel 4 Current X Count Register */
-#define DMA4_CURR_Y_COUNT	0xFFC00D38	/* DMA Channel 4 Current Y Count Register */
-#define DMA4_IRQ_STATUS		0xFFC00D28	/* DMA Channel 4 Interrupt/Status Register */
-#define DMA4_PERIPHERAL_MAP	0xFFC00D2C	/* DMA Channel 4 Peripheral Map Register */
-
-#define DMA5_CONFIG		0xFFC00D48	/* DMA Channel 5 Configuration Register */
-#define DMA5_NEXT_DESC_PTR	0xFFC00D40	/* DMA Channel 5 Next Descriptor Pointer Register */
-#define DMA5_START_ADDR		0xFFC00D44	/* DMA Channel 5 Start Address Register */
-#define DMA5_X_COUNT		0xFFC00D50	/* DMA Channel 5 X Count Register */
-#define DMA5_Y_COUNT		0xFFC00D58	/* DMA Channel 5 Y Count Register */
-#define DMA5_X_MODIFY		0xFFC00D54	/* DMA Channel 5 X Modify Register */
-#define DMA5_Y_MODIFY		0xFFC00D5C	/* DMA Channel 5 Y Modify Register */
-#define DMA5_CURR_DESC_PTR	0xFFC00D60	/* DMA Channel 5 Current Descriptor Pointer Register */
-#define DMA5_CURR_ADDR		0xFFC00D64	/* DMA Channel 5 Current Address Register */
-#define DMA5_CURR_X_COUNT	0xFFC00D70	/* DMA Channel 5 Current X Count Register */
-#define DMA5_CURR_Y_COUNT	0xFFC00D78	/* DMA Channel 5 Current Y Count Register */
-#define DMA5_IRQ_STATUS		0xFFC00D68	/* DMA Channel 5 Interrupt/Status Register */
-#define DMA5_PERIPHERAL_MAP	0xFFC00D6C	/* DMA Channel 5 Peripheral Map Register */
-
-#define DMA6_CONFIG		0xFFC00D88	/* DMA Channel 6 Configuration Register */
-#define DMA6_NEXT_DESC_PTR	0xFFC00D80	/* DMA Channel 6 Next Descriptor Pointer Register */
-#define DMA6_START_ADDR		0xFFC00D84	/* DMA Channel 6 Start Address Register */
-#define DMA6_X_COUNT		0xFFC00D90	/* DMA Channel 6 X Count Register */
-#define DMA6_Y_COUNT		0xFFC00D98	/* DMA Channel 6 Y Count Register */
-#define DMA6_X_MODIFY		0xFFC00D94	/* DMA Channel 6 X Modify Register */
-#define DMA6_Y_MODIFY		0xFFC00D9C	/* DMA Channel 6 Y Modify Register */
-#define DMA6_CURR_DESC_PTR	0xFFC00DA0	/* DMA Channel 6 Current Descriptor Pointer Register */
-#define DMA6_CURR_ADDR		0xFFC00DA4	/* DMA Channel 6 Current Address Register */
-#define DMA6_CURR_X_COUNT	0xFFC00DB0	/* DMA Channel 6 Current X Count Register */
-#define DMA6_CURR_Y_COUNT	0xFFC00DB8	/* DMA Channel 6 Current Y Count Register */
-#define DMA6_IRQ_STATUS		0xFFC00DA8	/* DMA Channel 6 Interrupt/Status Register */
-#define DMA6_PERIPHERAL_MAP	0xFFC00DAC	/* DMA Channel 6 Peripheral Map Register */
-
-#define DMA7_CONFIG		0xFFC00DC8	/* DMA Channel 7 Configuration Register */
-#define DMA7_NEXT_DESC_PTR	0xFFC00DC0	/* DMA Channel 7 Next Descriptor Pointer Register */
-#define DMA7_START_ADDR		0xFFC00DC4	/* DMA Channel 7 Start Address Register */
-#define DMA7_X_COUNT		0xFFC00DD0	/* DMA Channel 7 X Count Register */
-#define DMA7_Y_COUNT		0xFFC00DD8	/* DMA Channel 7 Y Count Register */
-#define DMA7_X_MODIFY		0xFFC00DD4	/* DMA Channel 7 X Modify Register */
-#define DMA7_Y_MODIFY		0xFFC00DDC	/* DMA Channel 7 Y Modify Register */
-#define DMA7_CURR_DESC_PTR	0xFFC00DE0	/* DMA Channel 7 Current Descriptor Pointer Register */
-#define DMA7_CURR_ADDR		0xFFC00DE4	/* DMA Channel 7 Current Address Register */
-#define DMA7_CURR_X_COUNT	0xFFC00DF0	/* DMA Channel 7 Current X Count Register */
-#define DMA7_CURR_Y_COUNT	0xFFC00DF8	/* DMA Channel 7 Current Y Count Register */
-#define DMA7_IRQ_STATUS		0xFFC00DE8	/* DMA Channel 7 Interrupt/Status Register */
-#define DMA7_PERIPHERAL_MAP	0xFFC00DEC	/* DMA Channel 7 Peripheral Map Register */
-
-#define MDMA_D1_CONFIG		0xFFC00E88	/* MemDMA Stream 1 Destination Configuration Register */
-#define MDMA_D1_NEXT_DESC_PTR	0xFFC00E80	/* MemDMA Stream 1 Destination Next Descriptor Pointer Register */
-#define MDMA_D1_START_ADDR	0xFFC00E84	/* MemDMA Stream 1 Destination Start Address Register */
-#define MDMA_D1_X_COUNT		0xFFC00E90	/* MemDMA Stream 1 Destination X Count Register */
-#define MDMA_D1_Y_COUNT		0xFFC00E98	/* MemDMA Stream 1 Destination Y Count Register */
-#define MDMA_D1_X_MODIFY	0xFFC00E94	/* MemDMA Stream 1 Destination X Modify Register */
-#define MDMA_D1_Y_MODIFY	0xFFC00E9C	/* MemDMA Stream 1 Destination Y Modify Register */
-#define MDMA_D1_CURR_DESC_PTR	0xFFC00EA0	/* MemDMA Stream 1 Destination Current Descriptor Pointer Register */
-#define MDMA_D1_CURR_ADDR	0xFFC00EA4	/* MemDMA Stream 1 Destination Current Address Register */
-#define MDMA_D1_CURR_X_COUNT	0xFFC00EB0	/* MemDMA Stream 1 Destination Current X Count Register */
-#define MDMA_D1_CURR_Y_COUNT	0xFFC00EB8	/* MemDMA Stream 1 Destination Current Y Count Register */
-#define MDMA_D1_IRQ_STATUS	0xFFC00EA8	/* MemDMA Stream 1 Destination Interrupt/Status Register */
-#define MDMA_D1_PERIPHERAL_MAP	0xFFC00EAC	/* MemDMA Stream 1 Destination Peripheral Map Register */
-
-#define MDMA_S1_CONFIG		0xFFC00EC8	/* MemDMA Stream 1 Source Configuration Register */
-#define MDMA_S1_NEXT_DESC_PTR	0xFFC00EC0	/* MemDMA Stream 1 Source Next Descriptor Pointer Register */
-#define MDMA_S1_START_ADDR	0xFFC00EC4	/* MemDMA Stream 1 Source Start Address Register */
-#define MDMA_S1_X_COUNT		0xFFC00ED0	/* MemDMA Stream 1 Source X Count Register */
-#define MDMA_S1_Y_COUNT		0xFFC00ED8	/* MemDMA Stream 1 Source Y Count Register */
-#define MDMA_S1_X_MODIFY	0xFFC00ED4	/* MemDMA Stream 1 Source X Modify Register */
-#define MDMA_S1_Y_MODIFY	0xFFC00EDC	/* MemDMA Stream 1 Source Y Modify Register */
-#define MDMA_S1_CURR_DESC_PTR	0xFFC00EE0	/* MemDMA Stream 1 Source Current Descriptor Pointer Register */
-#define MDMA_S1_CURR_ADDR	0xFFC00EE4	/* MemDMA Stream 1 Source Current Address Register */
-#define MDMA_S1_CURR_X_COUNT	0xFFC00EF0	/* MemDMA Stream 1 Source Current X Count Register */
-#define MDMA_S1_CURR_Y_COUNT	0xFFC00EF8	/* MemDMA Stream 1 Source Current Y Count Register */
-#define MDMA_S1_IRQ_STATUS	0xFFC00EE8	/* MemDMA Stream 1 Source Interrupt/Status Register */
-#define MDMA_S1_PERIPHERAL_MAP	0xFFC00EEC	/* MemDMA Stream 1 Source Peripheral Map Register */
-
-#define MDMA_D0_CONFIG		0xFFC00E08	/* MemDMA Stream 0 Destination Configuration Register */
-#define MDMA_D0_NEXT_DESC_PTR	0xFFC00E00	/* MemDMA Stream 0 Destination Next Descriptor Pointer Register */
-#define MDMA_D0_START_ADDR	0xFFC00E04	/* MemDMA Stream 0 Destination Start Address Register */
-#define MDMA_D0_X_COUNT		0xFFC00E10	/* MemDMA Stream 0 Destination X Count Register */
-#define MDMA_D0_Y_COUNT		0xFFC00E18	/* MemDMA Stream 0 Destination Y Count Register */
-#define MDMA_D0_X_MODIFY	0xFFC00E14	/* MemDMA Stream 0 Destination X Modify Register */
-#define MDMA_D0_Y_MODIFY	0xFFC00E1C	/* MemDMA Stream 0 Destination Y Modify Register */
-#define MDMA_D0_CURR_DESC_PTR	0xFFC00E20	/* MemDMA Stream 0 Destination Current Descriptor Pointer Register */
-#define MDMA_D0_CURR_ADDR	0xFFC00E24	/* MemDMA Stream 0 Destination Current Address Register */
-#define MDMA_D0_CURR_X_COUNT	0xFFC00E30	/* MemDMA Stream 0 Destination Current X Count Register */
-#define MDMA_D0_CURR_Y_COUNT	0xFFC00E38	/* MemDMA Stream 0 Destination Current Y Count Register */
-#define MDMA_D0_IRQ_STATUS	0xFFC00E28	/* MemDMA Stream 0 Destination Interrupt/Status Register */
-#define MDMA_D0_PERIPHERAL_MAP	0xFFC00E2C	/* MemDMA Stream 0 Destination Peripheral Map Register */
-
-#define MDMA_S0_CONFIG		0xFFC00E48	/* MemDMA Stream 0 Source Configuration Register */
-#define MDMA_S0_NEXT_DESC_PTR	0xFFC00E40	/* MemDMA Stream 0 Source Next Descriptor Pointer Register */
-#define MDMA_S0_START_ADDR	0xFFC00E44	/* MemDMA Stream 0 Source Start Address Register */
-#define MDMA_S0_X_COUNT		0xFFC00E50	/* MemDMA Stream 0 Source X Count Register */
-#define MDMA_S0_Y_COUNT		0xFFC00E58	/* MemDMA Stream 0 Source Y Count Register */
-#define MDMA_S0_X_MODIFY	0xFFC00E54	/* MemDMA Stream 0 Source X Modify Register */
-#define MDMA_S0_Y_MODIFY	0xFFC00E5C	/* MemDMA Stream 0 Source Y Modify Register */
-#define MDMA_S0_CURR_DESC_PTR	0xFFC00E60	/* MemDMA Stream 0 Source Current Descriptor Pointer Register */
-#define MDMA_S0_CURR_ADDR	0xFFC00E64	/* MemDMA Stream 0 Source Current Address Register */
-#define MDMA_S0_CURR_X_COUNT	0xFFC00E70	/* MemDMA Stream 0 Source Current X Count Register */
-#define MDMA_S0_CURR_Y_COUNT	0xFFC00E78	/* MemDMA Stream 0 Source Current Y Count Register */
-#define MDMA_S0_IRQ_STATUS	0xFFC00E68	/* MemDMA Stream 0 Source Interrupt/Status Register */
-#define MDMA_S0_PERIPHERAL_MAP	0xFFC00E6C	/* MemDMA Stream 0 Source Peripheral Map Register */
-
-/* Parallel Peripheral Interface (PPI) (0xFFC01000 - 0xFFC010FF) */
-#define PPI_CONTROL		0xFFC01000	/* PPI Control Register */
-#define PPI_STATUS		0xFFC01004	/* PPI Status Register */
-#define PPI_COUNT		0xFFC01008	/* PPI Transfer Count Register */
-#define PPI_DELAY		0xFFC0100C	/* PPI Delay Count Register */
-#define PPI_FRAME		0xFFC01010	/* PPI Frame Length Register */
-
-/*
- * System MMR Register Bits
- */
-/*
- * PLL AND RESET MASKS
- */
-
-/* PLL_CTL Masks */
-#define PLL_CLKIN		0x00000000	/* Pass CLKIN to PLL */
-#define PLL_CLKIN_DIV2		0x00000001	/* Pass CLKIN/2 to PLL */
-#define PLL_OFF			0x00000002	/* Shut off PLL clocks */
-#define STOPCK_OFF		0x00000008	/* Core clock off */
-#define PDWN			0x00000020	/* Put the PLL in a Deep Sleep state */
-#define BYPASS			0x00000100	/* Bypass the PLL */
-
-/* PLL_DIV Masks */
-#define SCLK_DIV(x)		(x)		/* SCLK = VCO / x */
-
-#define CCLK_DIV1		0x00000000	/* CCLK = VCO / 1 */
-#define CCLK_DIV2		0x00000010	/* CCLK = VCO / 2 */
-#define CCLK_DIV4		0x00000020	/* CCLK = VCO / 4 */
-#define CCLK_DIV8		0x00000030	/* CCLK = VCO / 8 */
-
-/* SWRST Mask */
-#define SYSTEM_RESET		0x00000007	/* Initiates a system software reset */
-
-/*
- * SYSTEM INTERRUPT CONTROLLER MASKS
- */
-
-/* SIC_IAR0 Masks */
-#define P0_IVG(x)		((x)-7)		/* Peripheral #0 assigned IVG #x */
-#define P1_IVG(x)		((x)-7) << 0x4	/* Peripheral #1 assigned IVG #x */
-#define P2_IVG(x)		((x)-7) << 0x8	/* Peripheral #2 assigned IVG #x */
-#define P3_IVG(x)		((x)-7) << 0xC	/* Peripheral #3 assigned IVG #x */
-#define P4_IVG(x)		((x)-7) << 0x10	/* Peripheral #4 assigned IVG #x */
-#define P5_IVG(x)		((x)-7) << 0x14	/* Peripheral #5 assigned IVG #x */
-#define P6_IVG(x)		((x)-7) << 0x18	/* Peripheral #6 assigned IVG #x */
-#define P7_IVG(x)		((x)-7) << 0x1C	/* Peripheral #7 assigned IVG #x */
-
-/* SIC_IAR1 Masks */
-#define P8_IVG(x)		((x)-7)		/* Peripheral #8 assigned IVG #x */
-#define P9_IVG(x)		((x)-7) << 0x4	/* Peripheral #9 assigned IVG #x */
-#define P10_IVG(x)		((x)-7) << 0x8	/* Peripheral #10 assigned IVG #x */
-#define P11_IVG(x)		((x)-7) << 0xC	/* Peripheral #11 assigned IVG #x */
-#define P12_IVG(x)		((x)-7) << 0x10	/* Peripheral #12 assigned IVG #x */
-#define P13_IVG(x)		((x)-7) << 0x14	/* Peripheral #13 assigned IVG #x */
-#define P14_IVG(x)		((x)-7) << 0x18	/* Peripheral #14 assigned IVG #x */
-#define P15_IVG(x)		((x)-7) << 0x1C	/* Peripheral #15 assigned IVG #x */
-
-/* SIC_IAR2 Masks */
-#define P16_IVG(x)		((x)-7)		/* Peripheral #16 assigned IVG #x */
-#define P17_IVG(x)		((x)-7) << 0x4	/* Peripheral #17 assigned IVG #x */
-#define P18_IVG(x)		((x)-7) << 0x8	/* Peripheral #18 assigned IVG #x */
-#define P19_IVG(x)		((x)-7) << 0xC	/* Peripheral #19 assigned IVG #x */
-#define P20_IVG(x)		((x)-7) << 0x10	/* Peripheral #20 assigned IVG #x */
-#define P21_IVG(x)		((x)-7) << 0x14	/* Peripheral #21 assigned IVG #x */
-#define P22_IVG(x)		((x)-7) << 0x18	/* Peripheral #22 assigned IVG #x */
-#define P23_IVG(x)		((x)-7) << 0x1C	/* Peripheral #23 assigned IVG #x */
-
-/* SIC_IMASK Masks */
-#define SIC_UNMASK_ALL		0x00000000	/* Unmask all peripheral interrupts */
-#define SIC_MASK_ALL		0xFFFFFFFF	/* Mask all peripheral interrupts */
-#define SIC_MASK(x)		(1 << (x))	/* Mask Peripheral #x interrupt */
-#define SIC_UNMASK(x)		(0xFFFFFFFF ^ (1 << (x)))	/* Unmask Peripheral #x interrupt */
-
-/* SIC_IWR Masks */
-#define IWR_DISABLE_ALL		0x00000000	/* Wakeup Disable all peripherals */
-#define IWR_ENABLE_ALL		0xFFFFFFFF	/* Wakeup Enable all peripherals */
-#define IWR_ENABLE(x)		(1 << (x))	/* Wakeup Enable Peripheral #x */
-#define IWR_DISABLE(x)		(0xFFFFFFFF ^ (1 << (x)))	/*  Wakeup Disable Peripheral #x */
-
-/*
- * WATCHDOG TIMER MASKS
- */
-/* Watchdog Timer WDOG_CTL Register */
-#define ICTL(x)			((x<<1) & 0x0006)
-#define ENABLE_RESET		0x00000000	/* Set Watchdog Timer to generate reset */
-#define ENABLE_NMI		0x00000002	/* Set Watchdog Timer to generate non-maskable interrupt */
-#define ENABLE_GPI		0x00000004	/* Set Watchdog Timer to generate general-purpose interrupt */
-#define DISABLE_EVT		0x00000006	/* Disable Watchdog Timer interrupts */
-
-#define TMR_EN			0x0000
-#define TMR_DIS			0x0AD0
-#define TRO			0x8000
-
-#define ICTL_P0			0x01
-#define ICTL_P1			0x02
-#define TRO_P			0x0F
-
-/* RTC_STAT and RTC_ALARM register */
-#define	RTSEC			0x0000003F	/* Real-Time Clock Seconds */
-#define	RTMIN			0x00000FC0	/* Real-Time Clock Minutes */
-#define	RTHR			0x0001F000	/* Real-Time Clock Hours */
-#define	RTDAY			0xFFFE0000	/* Real-Time Clock Days */
-
-/* RTC_ICTL register */
-#define	SWIE			0x0001		/* Stopwatch Interrupt Enable */
-#define	AIE			0x0002		/* Alarm Interrupt Enable */
-#define	SIE			0x0004		/* Seconds (1 Hz) Interrupt Enable */
-#define	MIE			0x0008		/* Minutes Interrupt Enable */
-#define	HIE			0x0010		/* Hours Interrupt Enable */
-#define	DIE			0x0020		/* 24 Hours (Days) Interrupt Enable */
-#define	DAIE			0x0040		/* Day Alarm (Day, Hour, Minute, Second) Interrupt Enable */
-#define	WCIE			0x8000		/* Write Complete Interrupt Enable */
-
-/* RTC_ISTAT register */
-#define	SWEF			0x0001		/* Stopwatch Event Flag */
-#define	AEF			0x0002		/* Alarm Event Flag */
-#define	SEF			0x0004		/* Seconds (1 Hz) Event Flag */
-#define	MEF			0x0008		/* Minutes Event Flag */
-#define	HEF			0x0010		/* Hours Event Flag */
-#define	DEF			0x0020		/* 24 Hours (Days) Event Flag */
-#define	DAEF			0x0040		/* Day Alarm (Day, Hour, Minute, Second) Event Flag */
-#define	WPS			0x4000		/* Write Pending Status (RO) */
-#define	WCOM			0x8000		/* Write Complete */
-
-/* RTC_FAST Mask (RTC_PREN Mask) */
-#define ENABLE_PRESCALE		0x00000001	/* Enable prescaler so RTC runs at 1 Hz */
-#define PREN			0x00000001	/* ** Must be set after power-up for proper operation of RTC */
-
-/*
- * UART CONTROLLER MASKS
- */
-
-/* UART_LCR Register */
-#define DLAB			0x80
-#define SB			0x40
-#define STP			0x20
-#define EPS			0x10
-#define PEN			0x08
-#define STB			0x04
-#define WLS(x)			((x-5) & 0x03)
-
-#define DLAB_P			0x07
-#define SB_P			0x06
-#define STP_P			0x05
-#define EPS_P			0x04
-#define PEN_P			0x03
-#define STB_P			0x02
-#define WLS_P1			0x01
-#define WLS_P0			0x00
-
-/* UART_MCR Register */
-#define LOOP_ENA		0x10
-#define LOOP_ENA_P		0x04
-
-/* UART_LSR Register */
-#define TEMT			0x40
-#define THRE			0x20
-#define BI			0x10
-#define FE			0x08
-#define PE			0x04
-#define OE			0x02
-#define DR			0x01
-
-#define TEMP_P			0x06
-#define THRE_P			0x05
-#define BI_P			0x04
-#define FE_P			0x03
-#define PE_P			0x02
-#define OE_P			0x01
-#define DR_P			0x00
-
-/* UART_IER Register */
-#define ELSI			0x04
-#define ETBEI			0x02
-#define ERBFI			0x01
-
-#define ELSI_P			0x02
-#define ETBEI_P			0x01
-#define ERBFI_P			0x00
-
-/* UART_IIR Register */
-#define STATUS(x)		((x << 1) & 0x06)
-#define NINT			0x01
-#define STATUS_P1		0x02
-#define STATUS_P0		0x01
-#define NINT_P			0x00
-
-/* UART_GCTL Register */
-#define FFE			0x20
-#define FPE			0x10
-#define RPOLC			0x08
-#define TPOLC			0x04
-#define IREN			0x02
-#define UCEN			0x01
-
-#define FFE_P			0x05
-#define FPE_P			0x04
-#define RPOLC_P			0x03
-#define TPOLC_P			0x02
-#define IREN_P			0x01
-#define UCEN_P			0x00
-
-/*
- * SERIAL PORT MASKS
- */
-/* SPORTx_TCR1 Masks */
-#define TSPEN    		0x0001		/* TX enable */
-#define ITCLK    		0x0002		/* Internal TX Clock Select */
-#define TDTYPE			0x000C		/* TX Data Formatting Select */
-#define TLSBIT			0x0010		/* TX Bit Order */
-#define ITFS			0x0200		/* Internal TX Frame Sync Select */
-#define TFSR			0x0400		/* TX Frame Sync Required Select */
-#define DITFS			0x0800		/* Data Independent TX Frame Sync Select */
-#define LTFS			0x1000		/* Low TX Frame Sync Select */
-#define LATFS			0x2000		/* Late TX Frame Sync Select */
-#define TCKFE			0x4000		/* TX Clock Falling Edge Select */
-
-/* SPORTx_TCR2 Masks */
-#define SLEN			0x001F		/*TX Word Length */
-#define TXSE			0x0100		/*TX Secondary Enable */
-#define TSFSE			0x0200		/*TX Stereo Frame Sync Enable */
-#define TRFST			0x0400		/*TX Right-First Data Order */
-
-/* SPORTx_RCR1 Masks */
-#define RSPEN			0x0001		/* RX enable */
-#define IRCLK			0x0002		/* Internal RX Clock Select */
-#define RDTYPE			0x000C		/* RX Data Formatting Select */
-#define RULAW			0x0008		/* u-Law enable */
-#define RALAW			0x000C		/* A-Law enable */
-#define RLSBIT			0x0010		/* RX Bit Order */
-#define IRFS			0x0200		/* Internal RX Frame Sync Select */
-#define RFSR			0x0400		/* RX Frame Sync Required Select */
-#define LRFS			0x1000		/* Low RX Frame Sync Select */
-#define LARFS			0x2000		/* Late RX Frame Sync Select */
-#define RCKFE			0x4000		/* RX Clock Falling Edge Select */
-
-/* SPORTx_RCR2 Masks */
-#define SLEN			0x001F		/* RX Word Length */
-#define RXSE			0x0100		/* RX Secondary Enable */
-#define RSFSE			0x0200		/* RX Stereo Frame Sync Enable */
-#define RRFST			0x0400		/* Right-First Data Order */
-
-/* SPORTx_STAT Masks */
-#define RXNE			0x0001		/* RX FIFO Not Empty Status */
-#define RUVF			0x0002		/* RX Underflow Status */
-#define ROVF			0x0004		/* RX Overflow Status */
-#define TXF			0x0008		/* TX FIFO Full Status */
-#define TUVF			0x0010		/* TX Underflow Status */
-#define TOVF			0x0020		/* TX Overflow Status */
-#define TXHRE			0x0040		/* TX Hold Register Empty */
-
-/* SPORTx_MCMC1 Masks */
-#define WSIZE			0x0000F000	/* Multichannel Window Size Field */
-#define WOFF			0x000003FF	/* /Multichannel Window Offset Field */
-
-/* SPORTx_MCMC2 Masks */
-#define MCCRM			0x00000003	/* Multichannel Clock Recovery Mode */
-#define MCDTXPE			0x00000004	/* Multichannel DMA Transmit Packing */
-#define MCDRXPE			0x00000008	/* Multichannel DMA Receive Packing */
-#define MCMEN			0x00000010	/* Multichannel Frame Mode Enable */
-#define FSDR			0x00000080	/* Multichannel Frame Sync to Data Relationship */
-#define MFD			0x0000F000	/* Multichannel Frame Delay */
-
-/*
- * PARALLEL PERIPHERAL INTERFACE (PPI) MASKS
- */
-
-/* PPI_CONTROL Masks */
-#define PORT_EN			0x00000001	/* PPI Port Enable */
-#define PORT_DIR		0x00000002	/* PPI Port Direction */
-#define XFR_TYPE		0x0000000C	/* PPI Transfer Type */
-#define PORT_CFG		0x00000030	/* PPI Port Configuration */
-#define FLD_SEL			0x00000040	/* PPI Active Field Select */
-#define PACK_EN			0x00000080	/* PPI Packing Mode */
-#define DMA32			0x00000100	/* PPI 32-bit DMA Enable */
-#define SKIP_EN			0x00000200	/* PPI Skip Element Enable */
-#define SKIP_EO			0x00000400	/* PPI Skip Even/Odd Elements */
-#define DLENGTH			0x00003800	/* PPI Data Length */
-#define DLEN_8			0x0		/* PPI Data Length mask for DLEN=8 */
-#define DLEN(x)			(((x-9) & 0x07) << 11)	/* PPI Data Length (only works for x=10-->x=16) */
-#define POL			0x0000C000	/* PPI Signal Polarities */
-
-/* PPI_STATUS Masks */
-#define FLD			0x00000400	/* Field Indicator */
-#define FT_ERR			0x00000800	/* Frame Track Error */
-#define OVR			0x00001000	/* FIFO Overflow Error */
-#define UNDR			0x00002000	/* FIFO Underrun Error */
-#define ERR_DET			0x00004000	/* Error Detected Indicator */
-#define ERR_NCOR		0x00008000	/* Error Not Corrected Indicator */
-
-/*
- * DMA CONTROLLER MASKS
- */
-
-/* DMAx_CONFIG, MDMA_yy_CONFIG Masks */
-#define DMAEN			0x00000001	/* Channel Enable */
-#define WNR			0x00000002	/* Channel Direction (W/R*) */
-#define WDSIZE_8		0x00000000	/* Word Size 8 bits */
-#define WDSIZE_16		0x00000004	/* Word Size 16 bits */
-#define WDSIZE_32		0x00000008	/* Word Size 32 bits */
-#define DMA2D			0x00000010	/* 2D/1D* Mode */
-#define RESTART			0x00000020	/* Restart */
-#define DI_SEL			0x00000040	/* Data Interrupt Select */
-#define DI_EN			0x00000080	/* Data Interrupt Enable */
-#define NDSIZE			0x00000900	/* Next Descriptor Size */
-#define FLOW			0x00007000	/* Flow Control */
-
-#define DMAEN_P			0		/* Channel Enable */
-#define WNR_P			1		/* Channel Direction (W/R*) */
-#define DMA2D_P			4		/* 2D/1D* Mode */
-#define RESTART_P		5		/* Restart */
-#define DI_SEL_P		6		/* Data Interrupt Select */
-#define DI_EN_P			7		/* Data Interrupt Enable */
-
-/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */
-#define DMA_DONE		0x00000001	/* DMA Done Indicator */
-#define DMA_ERR			0x00000002	/* DMA Error Indicator */
-#define DFETCH			0x00000004	/* Descriptor Fetch Indicator */
-#define DMA_RUN			0x00000008	/* DMA Running Indicator */
-
-#define DMA_DONE_P		0		/* DMA Done Indicator */
-#define DMA_ERR_P		1		/* DMA Error Indicator */
-#define DFETCH_P		2		/* Descriptor Fetch Indicator */
-#define DMA_RUN_P		3		/* DMA Running Indicator */
-
-/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
-#define CTYPE			0x00000040	/* DMA Channel Type Indicator */
-#define CTYPE_P			6		/* DMA Channel Type Indicator BIT POSITION */
-#define PCAP8			0x00000080	/* DMA 8-bit Operation Indicator */
-#define PCAP16			0x00000100	/* DMA 16-bit Operation Indicator */
-#define PCAP32			0x00000200	/* DMA 32-bit Operation Indicator */
-#define PCAPWR			0x00000400	/* DMA Write Operation Indicator */
-#define PCAPRD			0x00000800	/* DMA Read Operation Indicator */
-#define PMAP			0x00007000	/* DMA Peripheral Map Field */
-
-/*
- * GENERAL PURPOSE TIMER MASKS
- */
-
-/* PWM Timer bit definitions */
-
-/* TIMER_ENABLE Register */
-#define TIMEN0			0x0001
-#define TIMEN1			0x0002
-#define TIMEN2			0x0004
-
-#define TIMEN0_P		0x00
-#define TIMEN1_P		0x01
-#define TIMEN2_P		0x02
-
-/* TIMER_DISABLE Register */
-#define TIMDIS0			0x0001
-#define TIMDIS1			0x0002
-#define TIMDIS2			0x0004
-
-#define TIMDIS0_P		0x00
-#define TIMDIS1_P		0x01
-#define TIMDIS2_P		0x02
-
-/* TIMER_STATUS Register */
-#define TIMIL0			0x0001
-#define TIMIL1			0x0002
-#define TIMIL2			0x0004
-#define TOVL_ERR0		0x0010
-#define TOVL_ERR1		0x0020
-#define TOVL_ERR2		0x0040
-#define TRUN0			0x1000
-#define TRUN1			0x2000
-#define TRUN2			0x4000
-
-#define TIMIL0_P		0x00
-#define TIMIL1_P		0x01
-#define TIMIL2_P		0x02
-#define TOVL_ERR0_P		0x04
-#define TOVL_ERR1_P		0x05
-#define TOVL_ERR2_P		0x06
-#define TRUN0_P			0x0C
-#define TRUN1_P			0x0D
-#define TRUN2_P			0x0E
-
-/* TIMERx_CONFIG Registers */
-#define PWM_OUT			0x0001
-#define WDTH_CAP		0x0002
-#define EXT_CLK			0x0003
-#define PULSE_HI		0x0004
-#define PERIOD_CNT		0x0008
-#define IRQ_ENA			0x0010
-#define TIN_SEL			0x0020
-#define OUT_DIS			0x0040
-#define CLK_SEL			0x0080
-#define TOGGLE_HI		0x0100
-#define EMU_RUN			0x0200
-#define ERR_TYP(x)		((x & 0x03) << 14)
-
-#define TMODE_P0		0x00
-#define TMODE_P1		0x01
-#define PULSE_HI_P		0x02
-#define PERIOD_CNT_P		0x03
-#define IRQ_ENA_P		0x04
-#define TIN_SEL_P		0x05
-#define OUT_DIS_P		0x06
-#define CLK_SEL_P		0x07
-#define TOGGLE_HI_P		0x08
-#define EMU_RUN_P		0x09
-#define ERR_TYP_P0		0x0E
-#define ERR_TYP_P1		0x0F
-
-/*
- * PROGRAMMABLE FLAG MASKS
- */
-
-/* General Purpose IO (0xFFC00700 - 0xFFC007FF)  Masks */
-#define PF0			0x0001
-#define PF1			0x0002
-#define PF2			0x0004
-#define PF3			0x0008
-#define PF4			0x0010
-#define PF5			0x0020
-#define PF6			0x0040
-#define PF7			0x0080
-#define PF8			0x0100
-#define PF9			0x0200
-#define PF10			0x0400
-#define PF11			0x0800
-#define PF12			0x1000
-#define PF13			0x2000
-#define PF14			0x4000
-#define PF15			0x8000
-
-/* General Purpose IO (0xFFC00700 - 0xFFC007FF)  BIT POSITIONS */
-#define PF0_P			0
-#define PF1_P			1
-#define PF2_P			2
-#define PF3_P			3
-#define PF4_P			4
-#define PF5_P			5
-#define PF6_P			6
-#define PF7_P			7
-#define PF8_P			8
-#define PF9_P			9
-#define PF10_P			10
-#define PF11_P			11
-#define PF12_P			12
-#define PF13_P			13
-#define PF14_P			14
-#define PF15_P			15
-
-/*
- * SERIAL PERIPHERAL INTERFACE (SPI) MASKS
- */
-
-/* SPI_CTL Masks */
-#define TIMOD			0x00000003	/* Transfer initiation mode and interrupt generation */
-#define SZ			0x00000004	/* Send Zero (=0) or last (=1) word when TDBR empty. */
-#define GM			0x00000008	/* When RDBR full, get more (=1) data or discard (=0) incoming Data */
-#define PSSE			0x00000010	/* Enable (=1) Slave-Select input for Master. */
-#define EMISO			0x00000020	/* Enable (=1) MISO pin as an output. */
-#define SIZE			0x00000100	/* Word length (0 => 8 bits, 1 => 16 bits) */
-#define LSBF			0x00000200	/* Data format (0 => MSB sent/received first 1 => LSB sent/received first) */
-#define CPHA			0x00000400	/* Clock phase (0 => SPICLK starts toggling in middle of xfer, 1 => SPICLK toggles at the beginning of xfer. */
-#define CPOL			0x00000800	/* Clock polarity (0 => active-high, 1 => active-low) */
-#define MSTR			0x00001000	/* Configures SPI as master (=1) or slave (=0) */
-#define WOM			0x00002000	/* Open drain (=1) data output enable (for MOSI and MISO) */
-#define SPE			0x00004000	/* SPI module enable (=1), disable (=0) */
-
-/* SPI_FLG Masks */
-#define FLS1			0x00000002	/* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
-#define FLS2			0x00000004	/* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
-#define FLS3			0x00000008	/* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
-#define FLS4			0x00000010	/* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
-#define FLS5			0x00000020	/* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
-#define FLS6			0x00000040	/* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
-#define FLS7			0x00000080	/* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
-#define FLG1			0x00000200	/* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */
-#define FLG2			0x00000400	/* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
-#define FLG3			0x00000800	/* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */
-#define FLG4			0x00001000	/* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */
-#define FLG5			0x00002000	/* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */
-#define FLG6			0x00004000	/* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */
-#define FLG7			0x00008000	/* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */
-
-/* SPI_FLG Bit Positions */
-#define FLS1_P			0x00000001	/* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
-#define FLS2_P			0x00000002	/* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
-#define FLS3_P			0x00000003	/* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
-#define FLS4_P			0x00000004	/* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
-#define FLS5_P			0x00000005	/* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
-#define FLS6_P			0x00000006	/* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
-#define FLS7_P			0x00000007	/* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
-#define FLG1_P			0x00000009	/* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */
-#define FLG2_P			0x0000000A	/* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
-#define FLG3_P			0x0000000B	/* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */
-#define FLG4_P			0x0000000C	/* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */
-#define FLG5_P			0x0000000D	/* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */
-#define FLG6_P			0x0000000E	/* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */
-#define FLG7_P			0x0000000F	/* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */
-
-/* SPI_STAT Masks */
-#define SPIF			0x00000001	/* Set (=1) when SPI single-word transfer complete */
-#define MODF			0x00000002	/* Set(=1)in a master device when some other device tries to become master */
-#define TXE			0x00000004	/* Set (=1) when transmission occurs with no new data in SPI_TDBR */
-#define TXS			0x00000008	/* SPI_TDBR Data Buffer Status (0=Empty, 1=Full) */
-#define RBSY			0x00000010	/* Set (=1) when data is received with RDBR full */
-#define RXS			0x00000020	/* SPI_RDBR Data Buffer Status (0=Empty, 1=Full) */
-#define TXCOL			0x00000040	/* When set (=1), corrupt data may have been transmitted */
-
-/*
- * ASYNCHRONOUS MEMORY CONTROLLER MASKS
- */
-
-/* AMGCTL Masks */
-#define AMCKEN			0x00000001	/* Enable CLKOUT */
-#define AMBEN_B0		0x00000002	/* Enable Asynchronous Memory Bank 0 only */
-#define AMBEN_B0_B1		0x00000004	/* Enable Asynchronous Memory Banks 0 & 1 only */
-#define AMBEN_B0_B1_B2		0x00000006	/* Enable Asynchronous Memory Banks 0, 1, and 2 */
-#define AMBEN_ALL		0x00000008	/* Enable Asynchronous Memory Banks (all) 0, 1, 2, and 3 */
-
-/* AMGCTL Bit Positions */
-#define AMCKEN_P		0x00000000	/* Enable CLKOUT */
-#define AMBEN_P0		0x00000001	/* Asynchronous Memory Enable, 000 - banks 0-3 disabled, 001 - Bank 0 enabled */
-#define AMBEN_P1		0x00000002	/* Asynchronous Memory Enable, 010 - banks 0&1 enabled,  011 - banks 0-3 enabled */
-#define AMBEN_P2		0x00000003	/* Asynchronous Memory Enable, 1xx - All banks (bank 0, 1, 2, and 3) enabled */
-
-/* AMBCTL0 Masks */
-#define B0RDYEN			0x00000001	/* Bank 0 RDY Enable, 0=disable, 1=enable */
-#define B0RDYPOL		0x00000002	/* Bank 0 RDY Active high, 0=active low, 1=active high */
-#define B0TT_1			0x00000004	/* Bank 0 Transition Time from Read to Write = 1 cycle */
-#define B0TT_2			0x00000008	/* Bank 0 Transition Time from Read to Write = 2 cycles */
-#define B0TT_3			0x0000000C	/* Bank 0 Transition Time from Read to Write = 3 cycles */
-#define B0TT_4			0x00000000	/* Bank 0 Transition Time from Read to Write = 4 cycles */
-#define B0ST_1			0x00000010	/* Bank 0 Setup Time from AOE asserted to Read/Write asserted=1 cycle */
-#define B0ST_2			0x00000020	/* Bank 0 Setup Time from AOE asserted to Read/Write asserted=2 cycles */
-#define B0ST_3			0x00000030	/* Bank 0 Setup Time from AOE asserted to Read/Write asserted=3 cycles */
-#define B0ST_4			0x00000000	/* Bank 0 Setup Time from AOE asserted to Read/Write asserted=4 cycles */
-#define B0HT_1			0x00000040	/* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 1 cycle */
-#define B0HT_2			0x00000080	/* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 2 cycles */
-#define B0HT_3			0x000000C0	/* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 3 cycles */
-#define B0HT_0			0x00000000	/* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 0 cycles */
-#define B0RAT_1			0x00000100	/* Bank 0 Read Access Time = 1 cycle */
-#define B0RAT_2			0x00000200	/* Bank 0 Read Access Time = 2 cycles */
-#define B0RAT_3			0x00000300	/* Bank 0 Read Access Time = 3 cycles */
-#define B0RAT_4			0x00000400	/* Bank 0 Read Access Time = 4 cycles */
-#define B0RAT_5			0x00000500	/* Bank 0 Read Access Time = 5 cycles */
-#define B0RAT_6			0x00000600	/* Bank 0 Read Access Time = 6 cycles */
-#define B0RAT_7			0x00000700	/* Bank 0 Read Access Time = 7 cycles */
-#define B0RAT_8			0x00000800	/* Bank 0 Read Access Time = 8 cycles */
-#define B0RAT_9			0x00000900	/* Bank 0 Read Access Time = 9 cycles */
-#define B0RAT_10		0x00000A00	/* Bank 0 Read Access Time = 10 cycles */
-#define B0RAT_11		0x00000B00	/* Bank 0 Read Access Time = 11 cycles */
-#define B0RAT_12		0x00000C00	/* Bank 0 Read Access Time = 12 cycles */
-#define B0RAT_13		0x00000D00	/* Bank 0 Read Access Time = 13 cycles */
-#define B0RAT_14		0x00000E00	/* Bank 0 Read Access Time = 14 cycles */
-#define B0RAT_15		0x00000F00	/* Bank 0 Read Access Time = 15 cycles */
-#define B0WAT_1			0x00001000	/* Bank 0 Write Access Time = 1 cycle */
-#define B0WAT_2			0x00002000	/* Bank 0 Write Access Time = 2 cycles */
-#define B0WAT_3			0x00003000	/* Bank 0 Write Access Time = 3 cycles */
-#define B0WAT_4			0x00004000	/* Bank 0 Write Access Time = 4 cycles */
-#define B0WAT_5			0x00005000	/* Bank 0 Write Access Time = 5 cycles */
-#define B0WAT_6			0x00006000	/* Bank 0 Write Access Time = 6 cycles */
-#define B0WAT_7			0x00007000	/* Bank 0 Write Access Time = 7 cycles */
-#define B0WAT_8			0x00008000	/* Bank 0 Write Access Time = 8 cycles */
-#define B0WAT_9			0x00009000	/* Bank 0 Write Access Time = 9 cycles */
-#define B0WAT_10		0x0000A000	/* Bank 0 Write Access Time = 10 cycles */
-#define B0WAT_11		0x0000B000	/* Bank 0 Write Access Time = 11 cycles */
-#define B0WAT_12		0x0000C000	/* Bank 0 Write Access Time = 12 cycles */
-#define B0WAT_13		0x0000D000	/* Bank 0 Write Access Time = 13 cycles */
-#define B0WAT_14		0x0000E000	/* Bank 0 Write Access Time = 14 cycles */
-#define B0WAT_15		0x0000F000	/* Bank 0 Write Access Time = 15 cycles */
-#define B1RDYEN			0x00010000	/* Bank 1 RDY enable, 0=disable, 1=enable */
-#define B1RDYPOL		0x00020000	/* Bank 1 RDY Active high, 0=active low, 1=active high */
-#define B1TT_1			0x00040000	/* Bank 1 Transition Time from Read to Write = 1 cycle */
-#define B1TT_2			0x00080000	/* Bank 1 Transition Time from Read to Write = 2 cycles */
-#define B1TT_3			0x000C0000	/* Bank 1 Transition Time from Read to Write = 3 cycles */
-#define B1TT_4			0x00000000	/* Bank 1 Transition Time from Read to Write = 4 cycles */
-#define B1ST_1			0x00100000	/* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
-#define B1ST_2			0x00200000	/* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
-#define B1ST_3			0x00300000	/* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
-#define B1ST_4			0x00000000	/* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
-#define B1HT_1			0x00400000	/* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
-#define B1HT_2			0x00800000	/* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
-#define B1HT_3			0x00C00000	/* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
-#define B1HT_0			0x00000000	/* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
-#define B1RAT_1			0x01000000	/* Bank 1 Read Access Time = 1 cycle */
-#define B1RAT_2			0x02000000	/* Bank 1 Read Access Time = 2 cycles */
-#define B1RAT_3			0x03000000	/* Bank 1 Read Access Time = 3 cycles */
-#define B1RAT_4			0x04000000	/* Bank 1 Read Access Time = 4 cycles */
-#define B1RAT_5			0x05000000	/* Bank 1 Read Access Time = 5 cycles */
-#define B1RAT_6			0x06000000	/* Bank 1 Read Access Time = 6 cycles */
-#define B1RAT_7			0x07000000	/* Bank 1 Read Access Time = 7 cycles */
-#define B1RAT_8			0x08000000	/* Bank 1 Read Access Time = 8 cycles */
-#define B1RAT_9			0x09000000	/* Bank 1 Read Access Time = 9 cycles */
-#define B1RAT_10		0x0A000000	/* Bank 1 Read Access Time = 10 cycles */
-#define B1RAT_11		0x0B000000	/* Bank 1 Read Access Time = 11 cycles */
-#define B1RAT_12		0x0C000000	/* Bank 1 Read Access Time = 12 cycles */
-#define B1RAT_13		0x0D000000	/* Bank 1 Read Access Time = 13 cycles */
-#define B1RAT_14		0x0E000000	/* Bank 1 Read Access Time = 14 cycles */
-#define B1RAT_15		0x0F000000	/* Bank 1 Read Access Time = 15 cycles */
-#define B1WAT_1			0x10000000	/* Bank 1 Write Access Time = 1 cycle */
-#define B1WAT_2			0x20000000	/* Bank 1 Write Access Time = 2 cycles */
-#define B1WAT_3			0x30000000	/* Bank 1 Write Access Time = 3 cycles */
-#define B1WAT_4			0x40000000	/* Bank 1 Write Access Time = 4 cycles */
-#define B1WAT_5			0x50000000	/* Bank 1 Write Access Time = 5 cycles */
-#define B1WAT_6			0x60000000	/* Bank 1 Write Access Time = 6 cycles */
-#define B1WAT_7			0x70000000	/* Bank 1 Write Access Time = 7 cycles */
-#define B1WAT_8			0x80000000	/* Bank 1 Write Access Time = 8 cycles */
-#define B1WAT_9			0x90000000	/* Bank 1 Write Access Time = 9 cycles */
-#define B1WAT_10		0xA0000000	/* Bank 1 Write Access Time = 10 cycles */
-#define B1WAT_11		0xB0000000	/* Bank 1 Write Access Time = 11 cycles */
-#define B1WAT_12		0xC0000000	/* Bank 1 Write Access Time = 12 cycles */
-#define B1WAT_13		0xD0000000	/* Bank 1 Write Access Time = 13 cycles */
-#define B1WAT_14		0xE0000000	/* Bank 1 Write Access Time = 14 cycles */
-#define B1WAT_15		0xF0000000	/* Bank 1 Write Access Time = 15 cycles */
-
-/* AMBCTL1 Masks */
-#define B2RDYEN			0x00000001	/* Bank 2 RDY Enable, 0=disable, 1=enable */
-#define B2RDYPOL		0x00000002	/* Bank 2 RDY Active high, 0=active low, 1=active high */
-#define B2TT_1			0x00000004	/* Bank 2 Transition Time from Read to Write = 1 cycle */
-#define B2TT_2			0x00000008	/* Bank 2 Transition Time from Read to Write = 2 cycles */
-#define B2TT_3			0x0000000C	/* Bank 2 Transition Time from Read to Write = 3 cycles */
-#define B2TT_4			0x00000000	/* Bank 2 Transition Time from Read to Write = 4 cycles */
-#define B2ST_1			0x00000010	/* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
-#define B2ST_2			0x00000020	/* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
-#define B2ST_3			0x00000030	/* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
-#define B2ST_4			0x00000000	/* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
-#define B2HT_1			0x00000040	/* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
-#define B2HT_2			0x00000080	/* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
-#define B2HT_3			0x000000C0	/* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
-#define B2HT_0			0x00000000	/* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
-#define B2RAT_1			0x00000100	/* Bank 2 Read Access Time = 1 cycle */
-#define B2RAT_2			0x00000200	/* Bank 2 Read Access Time = 2 cycles */
-#define B2RAT_3			0x00000300	/* Bank 2 Read Access Time = 3 cycles */
-#define B2RAT_4			0x00000400	/* Bank 2 Read Access Time = 4 cycles */
-#define B2RAT_5			0x00000500	/* Bank 2 Read Access Time = 5 cycles */
-#define B2RAT_6			0x00000600	/* Bank 2 Read Access Time = 6 cycles */
-#define B2RAT_7			0x00000700	/* Bank 2 Read Access Time = 7 cycles */
-#define B2RAT_8			0x00000800	/* Bank 2 Read Access Time = 8 cycles */
-#define B2RAT_9			0x00000900	/* Bank 2 Read Access Time = 9 cycles */
-#define B2RAT_10		0x00000A00	/* Bank 2 Read Access Time = 10 cycles */
-#define B2RAT_11		0x00000B00	/* Bank 2 Read Access Time = 11 cycles */
-#define B2RAT_12		0x00000C00	/* Bank 2 Read Access Time = 12 cycles */
-#define B2RAT_13		0x00000D00	/* Bank 2 Read Access Time = 13 cycles */
-#define B2RAT_14		0x00000E00	/* Bank 2 Read Access Time = 14 cycles */
-#define B2RAT_15		0x00000F00	/* Bank 2 Read Access Time = 15 cycles */
-#define B2WAT_1			0x00001000	/* Bank 2 Write Access Time = 1 cycle */
-#define B2WAT_2			0x00002000	/* Bank 2 Write Access Time = 2 cycles */
-#define B2WAT_3			0x00003000	/* Bank 2 Write Access Time = 3 cycles */
-#define B2WAT_4			0x00004000	/* Bank 2 Write Access Time = 4 cycles */
-#define B2WAT_5			0x00005000	/* Bank 2 Write Access Time = 5 cycles */
-#define B2WAT_6			0x00006000	/* Bank 2 Write Access Time = 6 cycles */
-#define B2WAT_7			0x00007000	/* Bank 2 Write Access Time = 7 cycles */
-#define B2WAT_8			0x00008000	/* Bank 2 Write Access Time = 8 cycles */
-#define B2WAT_9			0x00009000	/* Bank 2 Write Access Time = 9 cycles */
-#define B2WAT_10		0x0000A000	/* Bank 2 Write Access Time = 10 cycles */
-#define B2WAT_11		0x0000B000	/* Bank 2 Write Access Time = 11 cycles */
-#define B2WAT_12		0x0000C000	/* Bank 2 Write Access Time = 12 cycles */
-#define B2WAT_13		0x0000D000	/* Bank 2 Write Access Time = 13 cycles */
-#define B2WAT_14		0x0000E000	/* Bank 2 Write Access Time = 14 cycles */
-#define B2WAT_15		0x0000F000	/* Bank 2 Write Access Time = 15 cycles */
-#define B3RDYEN			0x00010000	/* Bank 3 RDY enable, 0=disable, 1=enable */
-#define B3RDYPOL		0x00020000	/* Bank 3 RDY Active high, 0=active low, 1=active high */
-#define B3TT_1			0x00040000	/* Bank 3 Transition Time from Read to Write = 1 cycle */
-#define B3TT_2			0x00080000	/* Bank 3 Transition Time from Read to Write = 2 cycles */
-#define B3TT_3			0x000C0000	/* Bank 3 Transition Time from Read to Write = 3 cycles */
-#define B3TT_4			0x00000000	/* Bank 3 Transition Time from Read to Write = 4 cycles */
-#define B3ST_1			0x00100000	/* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
-#define B3ST_2			0x00200000	/* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
-#define B3ST_3			0x00300000	/* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
-#define B3ST_4			0x00000000	/* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
-#define B3HT_1			0x00400000	/* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
-#define B3HT_2			0x00800000	/* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
-#define B3HT_3			0x00C00000	/* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
-#define B3HT_0			0x00000000	/* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
-#define B3RAT_1			0x01000000	/* Bank 3 Read Access Time = 1 cycle */
-#define B3RAT_2			0x02000000	/* Bank 3 Read Access Time = 2 cycles */
-#define B3RAT_3			0x03000000	/* Bank 3 Read Access Time = 3 cycles */
-#define B3RAT_4			0x04000000	/* Bank 3 Read Access Time = 4 cycles */
-#define B3RAT_5			0x05000000	/* Bank 3 Read Access Time = 5 cycles */
-#define B3RAT_6			0x06000000	/* Bank 3 Read Access Time = 6 cycles */
-#define B3RAT_7			0x07000000	/* Bank 3 Read Access Time = 7 cycles */
-#define B3RAT_8			0x08000000	/* Bank 3 Read Access Time = 8 cycles */
-#define B3RAT_9			0x09000000	/* Bank 3 Read Access Time = 9 cycles */
-#define B3RAT_10		0x0A000000	/* Bank 3 Read Access Time = 10 cycles */
-#define B3RAT_11		0x0B000000	/* Bank 3 Read Access Time = 11 cycles */
-#define B3RAT_12		0x0C000000	/* Bank 3 Read Access Time = 12 cycles */
-#define B3RAT_13		0x0D000000	/* Bank 3 Read Access Time = 13 cycles */
-#define B3RAT_14		0x0E000000	/* Bank 3 Read Access Time = 14 cycles */
-#define B3RAT_15		0x0F000000	/* Bank 3 Read Access Time = 15 cycles */
-#define B3WAT_1			0x10000000	/* Bank 3 Write Access Time = 1 cycle */
-#define B3WAT_2			0x20000000	/* Bank 3 Write Access Time = 2 cycles */
-#define B3WAT_3			0x30000000	/* Bank 3 Write Access Time = 3 cycles */
-#define B3WAT_4			0x40000000	/* Bank 3 Write Access Time = 4 cycles */
-#define B3WAT_5			0x50000000	/* Bank 3 Write Access Time = 5 cycles */
-#define B3WAT_6			0x60000000	/* Bank 3 Write Access Time = 6 cycles */
-#define B3WAT_7			0x70000000	/* Bank 3 Write Access Time = 7 cycles */
-#define B3WAT_8			0x80000000	/* Bank 3 Write Access Time = 8 cycles */
-#define B3WAT_9			0x90000000	/* Bank 3 Write Access Time = 9 cycles */
-#define B3WAT_10		0xA0000000	/* Bank 3 Write Access Time = 10 cycles */
-#define B3WAT_11		0xB0000000	/* Bank 3 Write Access Time = 11 cycles */
-#define B3WAT_12		0xC0000000	/* Bank 3 Write Access Time = 12 cycles */
-#define B3WAT_13		0xD0000000	/* Bank 3 Write Access Time = 13 cycles */
-#define B3WAT_14		0xE0000000	/* Bank 3 Write Access Time = 14 cycles */
-#define B3WAT_15		0xF0000000	/* Bank 3 Write Access Time = 15 cycles */
-
-/*
- * SDRAM CONTROLLER MASKS
- */
-
-/* SDGCTL Masks */
-#define SCTLE			0x00000001	/* Enable SCLK[0], /SRAS, /SCAS, /SWE, SDQM[3:0] */
-#define CL_2			0x00000008	/* SDRAM CAS latency = 2 cycles */
-#define CL_3			0x0000000C	/* SDRAM CAS latency = 3 cycles */
-#define PFE			0x00000010	/* Enable SDRAM prefetch */
-#define PFP			0x00000020	/* Prefetch has priority over AMC requests */
-#define TRAS_1			0x00000040	/* SDRAM tRAS = 1 cycle */
-#define TRAS_2			0x00000080	/* SDRAM tRAS = 2 cycles */
-#define TRAS_3			0x000000C0	/* SDRAM tRAS = 3 cycles */
-#define TRAS_4			0x00000100	/* SDRAM tRAS = 4 cycles */
-#define TRAS_5			0x00000140	/* SDRAM tRAS = 5 cycles */
-#define TRAS_6			0x00000180	/* SDRAM tRAS = 6 cycles */
-#define TRAS_7			0x000001C0	/* SDRAM tRAS = 7 cycles */
-#define TRAS_8			0x00000200	/* SDRAM tRAS = 8 cycles */
-#define TRAS_9			0x00000240	/* SDRAM tRAS = 9 cycles */
-#define TRAS_10			0x00000280	/* SDRAM tRAS = 10 cycles */
-#define TRAS_11			0x000002C0	/* SDRAM tRAS = 11 cycles */
-#define TRAS_12			0x00000300	/* SDRAM tRAS = 12 cycles */
-#define TRAS_13			0x00000340	/* SDRAM tRAS = 13 cycles */
-#define TRAS_14			0x00000380	/* SDRAM tRAS = 14 cycles */
-#define TRAS_15			0x000003C0	/* SDRAM tRAS = 15 cycles */
-#define TRP_1			0x00000800	/* SDRAM tRP = 1 cycle */
-#define TRP_2			0x00001000	/* SDRAM tRP = 2 cycles */
-#define TRP_3			0x00001800	/* SDRAM tRP = 3 cycles */
-#define TRP_4			0x00002000	/* SDRAM tRP = 4 cycles */
-#define TRP_5			0x00002800	/* SDRAM tRP = 5 cycles */
-#define TRP_6			0x00003000	/* SDRAM tRP = 6 cycles */
-#define TRP_7			0x00003800	/* SDRAM tRP = 7 cycles */
-#define TRCD_1			0x00008000	/* SDRAM tRCD = 1 cycle */
-#define TRCD_2			0x00010000	/* SDRAM tRCD = 2 cycles */
-#define TRCD_3			0x00018000	/* SDRAM tRCD = 3 cycles */
-#define TRCD_4			0x00020000	/* SDRAM tRCD = 4 cycles */
-#define TRCD_5			0x00028000	/* SDRAM tRCD = 5 cycles */
-#define TRCD_6			0x00030000	/* SDRAM tRCD = 6 cycles */
-#define TRCD_7			0x00038000	/* SDRAM tRCD = 7 cycles */
-#define TWR_1			0x00080000	/* SDRAM tWR = 1 cycle */
-#define TWR_2			0x00100000	/* SDRAM tWR = 2 cycles */
-#define TWR_3			0x00180000	/* SDRAM tWR = 3 cycles */
-#define PUPSD			0x00200000	/* Power-up start delay */
-#define PSM			0x00400000	/* SDRAM power-up sequence = Precharge, mode register set, 8 CBR refresh cycles */
-#define PSS			0x00800000	/* enable SDRAM power-up sequence on next SDRAM access */
-#define SRFS			0x01000000	/* Start SDRAM self-refresh mode */
-#define EBUFE			0x02000000	/* Enable external buffering timing */
-#define FBBRW			0x04000000	/* Fast back-to-back read write enable */
-#define EMREN			0x10000000	/* Extended mode register enable */
-#define TCSR			0x20000000	/* Temp compensated self refresh value 85 deg C */
-#define CDDBG			0x40000000	/* Tristate SDRAM controls during bus grant */
-
-/* EBIU_SDBCTL Masks */
-#define EBE			0x00000001	/* Enable SDRAM external bank */
-#define EBSZ_16			0x00000000	/* SDRAM external bank size = 16MB */
-#define EBSZ_32			0x00000002	/* SDRAM external bank size = 32MB */
-#define EBSZ_64			0x00000004	/* SDRAM external bank size = 64MB */
-#define EBSZ_128		0x00000006	/* SDRAM external bank size = 128MB */
-#define EBCAW_8			0x00000000	/* SDRAM external bank column address width = 8 bits */
-#define EBCAW_9			0x00000010	/* SDRAM external bank column address width = 9 bits */
-#define EBCAW_10		0x00000020	/* SDRAM external bank column address width = 9 bits */
-#define EBCAW_11		0x00000030	/* SDRAM external bank column address width = 9 bits */
-
-/* EBIU_SDSTAT Masks */
-#define SDCI			0x00000001	/* SDRAM controller is idle */
-#define SDSRA			0x00000002	/* SDRAM SDRAM self refresh is active */
-#define SDPUA			0x00000004	/* SDRAM power up active */
-#define SDRS			0x00000008	/* SDRAM is in reset state */
-#define SDEASE			0x00000010	/* SDRAM EAB sticky error status - W1C */
-#define BGSTAT			0x00000020	/* Bus granted */
-
-#endif /* _DEF_BF532_H */
diff --git a/arch/blackfin/include/asm/cpu/defBF533.h b/arch/blackfin/include/asm/cpu/defBF533.h
deleted file mode 100644
index 90e50afa7f..0000000000
--- a/arch/blackfin/include/asm/cpu/defBF533.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * defBF533.h
- *
- * This file is subject to the terms and conditions of the GNU Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Non-GPL License also available as part of VisualDSP++
- *
- * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html
- *
- * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved
- *
- * This file under source code control, please send bugs or changes to:
- * dsptools.support@xxxxxxxxxx
- *
- */
-
-#ifndef _DEFBF533_H
-#define _DEFBF533_H
-
-#include <asm/cpu/defBF532.h>
-
-#endif /* _DEFBF533_H */
diff --git a/arch/blackfin/include/asm/cpu/defBF533_extn.h b/arch/blackfin/include/asm/cpu/defBF533_extn.h
deleted file mode 100644
index a9a1c7ccbd..0000000000
--- a/arch/blackfin/include/asm/cpu/defBF533_extn.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- * defBF533_extn.h
- *
- * This file is subject to the terms and conditions of the GNU Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Non-GPL License also available as part of VisualDSP++
- *
- * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html
- *
- * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved
- *
- * This file under source code control, please send bugs or changes to:
- * dsptools.support@xxxxxxxxxx
- *
- */
-
-#ifndef _DEF_BF533_EXTN_H
-#define _DEF_BF533_EXTN_H
-
-#define OFFSET_( x )		((x) & 0x0000FFFF) /* define macro for offset */
-/* Delay inserted for PLL transition */
-#define DELAY			0x1000
-
-#define L1_ISRAM		0xFFA00000
-#define L1_ISRAM_END		0xFFA10000
-#define DATA_BANKA_SRAM		0xFF800000
-#define DATA_BANKA_SRAM_END	0xFF808000
-#define DATA_BANKB_SRAM		0xFF900000
-#define DATA_BANKB_SRAM_END	0xFF908000
-#define SYSMMR_BASE		0xFFC00000
-#define WDSIZE16		0x00000004
-
-/* Event Vector Table Address */
-#define EVT_EMULATION_ADDR	0xffe02000
-#define EVT_RESET_ADDR		0xffe02004
-#define EVT_NMI_ADDR		0xffe02008
-#define EVT_EXCEPTION_ADDR	0xffe0200c
-#define EVT_GLOBAL_INT_ENB_ADDR	0xffe02010
-#define EVT_HARDWARE_ERROR_ADDR	0xffe02014
-#define EVT_TIMER_ADDR		0xffe02018
-#define EVT_IVG7_ADDR		0xffe0201c
-#define EVT_IVG8_ADDR		0xffe02020
-#define EVT_IVG9_ADDR		0xffe02024
-#define EVT_IVG10_ADDR		0xffe02028
-#define EVT_IVG11_ADDR		0xffe0202c
-#define EVT_IVG12_ADDR		0xffe02030
-#define EVT_IVG13_ADDR		0xffe02034
-#define EVT_IVG14_ADDR		0xffe02038
-#define EVT_IVG15_ADDR		0xffe0203c
-#define EVT_OVERRIDE_ADDR	0xffe02100
-
-/* IMASK Bit values */
-#define IVG15_POS		0x00008000
-#define IVG14_POS		0x00004000
-#define IVG13_POS		0x00002000
-#define IVG12_POS		0x00001000
-#define IVG11_POS		0x00000800
-#define IVG10_POS		0x00000400
-#define IVG9_POS		0x00000200
-#define IVG8_POS		0x00000100
-#define IVG7_POS		0x00000080
-#define IVGTMR_POS		0x00000040
-#define IVGHW_POS		0x00000020
-
-#define WDOG_TMR_DISABLE	(0xAD << 4)
-#define ICTL_RST		0x00000000
-#define ICTL_NMI		0x00000002
-#define ICTL_GP			0x00000004
-#define ICTL_DISABLE		0x00000003
-
-/* Watch Dog timer values setup */
-#define WATCHDOG_DISABLE	WDOG_TMR_DISABLE | ICTL_DISABLE
-
-#endif	/* _DEF_BF533_EXTN_H */
diff --git a/arch/blackfin/include/asm/cpu/defBF561.h b/arch/blackfin/include/asm/cpu/defBF561.h
deleted file mode 100644
index 5ab53ab7f0..0000000000
--- a/arch/blackfin/include/asm/cpu/defBF561.h
+++ /dev/null
@@ -1,3057 +0,0 @@
-/************************************************************************
- *
- * defBF561.h
- *
- * (c) Copyright 2001-2003 Analog Devices, Inc.  All rights reserved.
- *
- ************************************************************************/
-
-/* SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF561 */
-
-#ifndef _DEF_BF561_H
-#define _DEF_BF561_H
-
-/*
- * #if !defined(__ADSPBF561__)
- * #warning defBF561.h should only be included for BF561 chip.
- * #endif
- */
-
-// include all Core registers and bit definitions
-#include <asm/cpu/def_LPBlackfin.h>
-
-//*****************************************************************************
-// System MMR Register Map
-//*****************************************************************************
-
-//// Clock and System Control (0xFFC00000 - 0xFFC000FF)
-#define PLL_CTL			0xFFC00000	// PLL Control register (16-bit)
-#define PLL_DIV		        0xFFC00004	// PLL Divide Register (16-bit)
-#define VR_CTL		        0xFFC00008	// Voltage Regulator
-						// Control Register (16-bit)
-#define PLL_STAT		0xFFC0000C	// PLL Status register (16-bit)
-#define PLL_LOCKCNT		0xFFC00010	// PLL Lock Count register
-						// (16-bit)
-
-// System Reset and Interrupt Controller registers for
-// core A (0xFFC0 0100-0xFFC0 01FF)
-#define SICA_SWRST              0xFFC00100	// Software Reset register
-#define SICA_SYSCR              0xFFC00104	// System Reset Configuration
-						// register
-#define SICA_RVECT              0xFFC00108	// SIC Reset Vector Address
-						// Register
-#define SICA_IMASK              0xFFC0010C	// SIC Interrupt Mask
-						// register 0 - hack to fix
-						// old tests
-#define SICA_IMASK0             0xFFC0010C	// SIC Interrupt Mask
-						// register 0
-#define SICA_IMASK1             0xFFC00110	// SIC Interrupt Mask
-						// register 1
-#define SICA_IAR0               0xFFC00124	// SIC Interrupt Assignment
-						// Register 0
-#define SICA_IAR1               0xFFC00128	// SIC Interrupt Assignment
-						// Register 1
-#define SICA_IAR2               0xFFC0012C	// SIC Interrupt Assignment
-						// Register 2
-#define SICA_IAR3               0xFFC00130	// SIC Interrupt Assignment
-						// Register 3
-#define SICA_IAR4               0xFFC00134	// SIC Interrupt Assignment
-						// Register 4
-#define SICA_IAR5               0xFFC00138	// SIC Interrupt Assignment
-						// Register 5
-#define SICA_IAR6               0xFFC0013C	// SIC Interrupt Assignment
-						// Register 6
-#define SICA_IAR7               0xFFC00140	// SIC Interrupt Assignment
-						// Register 7
-#define SICA_ISR0               0xFFC00114	// SIC Interrupt Status
-						// register 0
-#define SICA_ISR1               0xFFC00118	// SIC Interrupt Status
-						// register 1
-#define SICA_IWR0               0xFFC0011C	// SIC Interrupt
-						// Wakeup-Enable register 0
-#define SICA_IWR1               0xFFC00120	// SIC Interrupt
-						// Wakeup-Enable register 1
-
-// System Reset and Interrupt Controller registers for
-// Core B (0xFFC0 1100-0xFFC0 11FF)
-#define SICB_SWRST              0xFFC01100	// reserved
-#define SICB_SYSCR              0xFFC01104	// reserved
-#define SICB_RVECT              0xFFC01108	// SIC Reset Vector Address
-						// Register
-#define SICB_IMASK0             0xFFC0110C	// SIC Interrupt Mask
-						// register 0
-#define SICB_IMASK1             0xFFC01110	// SIC Interrupt Mask
-						// register 1
-#define SICB_IAR0               0xFFC01124	// SIC Interrupt Assignment
-						// Register 0
-#define SICB_IAR1               0xFFC01128	// SIC Interrupt Assignment
-						// Register 1
-#define SICB_IAR2               0xFFC0112C	// SIC Interrupt Assignment
-						// Register 2
-#define SICB_IAR3               0xFFC01130	// SIC Interrupt Assignment
-						// Register 3
-#define SICB_IAR4               0xFFC01134	// SIC Interrupt Assignment
-						// Register 4
-#define SICB_IAR5               0xFFC01138	// SIC Interrupt Assignment
-						// Register 5
-#define SICB_IAR6               0xFFC0113C	// SIC Interrupt Assignment
-						// Register 6
-#define SICB_IAR7               0xFFC01140	// SIC Interrupt Assignment
-						// Register 7
-#define SICB_ISR0               0xFFC01114	// SIC Interrupt Status
-						// register 0
-#define SICB_ISR1               0xFFC01118	// SIC Interrupt Status
-						// register 1
-#define SICB_IWR0               0xFFC0111C	// SIC Interrupt
-						// Wakeup-Enable register 0
-#define SICB_IWR1               0xFFC01120	// SIC Interrupt
-						// Wakeup-Enable register 1
-
-// Watchdog Timer registers for Core A (0xFFC0 0200-0xFFC0 02FF)
-#define WDOGA_CTL 		0xFFC00200	// Watchdog Control register
-#define WDOGA_CNT 		0xFFC00204	// Watchdog Count register
-#define WDOGA_STAT 		0xFFC00208	// Watchdog Status register
-
-// Watchdog Timer registers for Core B (0xFFC0 1200-0xFFC0 12FF)
-#define WDOGB_CTL		0xFFC01200	// Watchdog Control register
-#define WDOGB_CNT 		0xFFC01204	// Watchdog Count register
-#define WDOGB_STAT 		0xFFC01208	// Watchdog Status register
-
-// UART Controller (0xFFC00400 - 0xFFC004FF)
-#define UART_THR             	0xFFC00400	// Transmit Holding register
-#define UART_RBR             	0xFFC00400	// Receive Buffer register
-#define UART_DLL              	0xFFC00400	// Divisor Latch (Low-Byte)
-#define UART_IER              	0xFFC00404	// Interrupt Enable Register
-#define UART_DLH              	0xFFC00404	// Divisor Latch (High-Byte)
-#define UART_IIR              	0xFFC00408	// Interrupt Identification
-						// Register
-#define UART_LCR              	0xFFC0040C	// Line Control Register
-#define UART_MCR		0xFFC00410	// Modem Control Register
-#define UART_LSR              	0xFFC00414	// Line Status Register
-#define UART_MSR            	0xFFC00418	// Modem Status Register
-#define UART_SCR              	0xFFC0041C	// SCR Scratch Register
-#define UART_GCTL      	      	0xFFC00424	// Global Control Register
-
-// SPI Controller (0xFFC00500 - 0xFFC005FF)
-#define SPI_CTL          	0xFFC00500	// SPI Control Register
-#define SPI_FLG               	0xFFC00504	// SPI Flag register
-#define SPI_STAT              	0xFFC00508	// SPI Status register
-#define SPI_TDBR              	0xFFC0050C	// SPI Transmit Data
-						// Buffer Register
-#define SPI_RDBR              	0xFFC00510	// SPI Receive Data
-						// Buffer Register
-#define SPI_BAUD              	0xFFC00514	// SPI Baud rate
-						// Register
-#define SPI_SHADOW            	0xFFC00518	// SPI_RDBR Shadow
-						// Register
-
-// Timer 0-7 registers (0xFFC0 0600-0xFFC0 06FF)
-#define TIMER0_CONFIG 		0xFFC00600	// Timer0 Configuration
-						// register
-#define TIMER0_COUNTER 		0xFFC00604	// Timer0 Counter register
-#define TIMER0_PERIOD 		0xFFC00608	// Timer0 Period register
-#define TIMER0_WIDTH 		0xFFC0060C	// Timer0 Width register
-#define TIMER1_CONFIG 		0xFFC00610	// Timer1 Configuration
-						// register
-#define TIMER1_COUNTER 		0xFFC00614	// Timer1 Counter register
-#define TIMER1_PERIOD 		0xFFC00618	// Timer1 Period register
-#define TIMER1_WIDTH 		0xFFC0061C	// Timer1 Width register
-#define TIMER2_CONFIG 		0xFFC00620	// Timer2 Configuration
-						// register
-#define TIMER2_COUNTER 		0xFFC00624	// Timer2 Counter register
-#define TIMER2_PERIOD 		0xFFC00628	// Timer2 Period register
-#define TIMER2_WIDTH 		0xFFC0062C	// Timer2 Width register
-#define TIMER3_CONFIG 		0xFFC00630	// Timer3 Configuration
-						// register
-#define TIMER3_COUNTER 		0xFFC00634	// Timer3 Counter register
-#define TIMER3_PERIOD 		0xFFC00638	// Timer3 Period register
-#define TIMER3_WIDTH 		0xFFC0063C	// Timer3 Width register
-#define TIMER4_CONFIG 		0xFFC00640	// Timer4 Configuration
-						// register
-#define TIMER4_COUNTER 		0xFFC00644	// Timer4 Counter register
-#define TIMER4_PERIOD 		0xFFC00648	// Timer4 Period register
-#define TIMER4_WIDTH 		0xFFC0064C	// Timer4 Width register
-#define TIMER5_CONFIG 		0xFFC00650	// Timer5 Configuration
-						// register
-#define TIMER5_COUNTER 		0xFFC00654	// Timer5 Counter register
-#define TIMER5_PERIOD 		0xFFC00658	// Timer5 Period register
-#define TIMER5_WIDTH 		0xFFC0065C	// Timer5 Width register
-#define TIMER6_CONFIG 		0xFFC00660	// Timer6 Configuration
-						// register
-#define TIMER6_COUNTER 		0xFFC00664	// Timer6 Counter register
-#define TIMER6_PERIOD 		0xFFC00668	// Timer6 Period register
-#define TIMER6_WIDTH 		0xFFC0066C	// Timer6 Width register
-#define TIMER7_CONFIG 		0xFFC00670	// Timer7 Configuration
-						// register
-#define TIMER7_COUNTER 		0xFFC00674	// Timer7 Counter register
-#define TIMER7_PERIOD 		0xFFC00678	// Timer7 Period register
-#define TIMER7_WIDTH 		0xFFC0067C	// Timer7 Width register
-
-#define TMRS8_ENABLE 		0xFFC00680	// Timer Enable Register
-#define TMRS8_DISABLE 		0xFFC00684	// Timer Disable register
-#define TMRS8_STATUS 		0xFFC00688	// Timer Status register
-
-// Timer registers 8-11 (0xFFC0 1600-0xFFC0 16FF)
-#define TIMER8_CONFIG 		0xFFC01600	// Timer8 Configuration
-						// register
-#define TIMER8_COUNTER 		0xFFC01604	// Timer8 Counter register
-#define TIMER8_PERIOD 		0xFFC01608	// Timer8 Period register
-#define TIMER8_WIDTH 		0xFFC0160C	// Timer8 Width register
-#define TIMER9_CONFIG 		0xFFC01610	// Timer9 Configuration
-						// register
-#define TIMER9_COUNTER 		0xFFC01614	// Timer9 Counter register
-#define TIMER9_PERIOD 		0xFFC01618	// Timer9 Period register
-#define TIMER9_WIDTH 		0xFFC0161C	// Timer9 Width register
-#define TIMER10_CONFIG 		0xFFC01620	// Timer10 Configuration
-						// register
-#define TIMER10_COUNTER		0xFFC01624	// Timer10 Counter register
-#define TIMER10_PERIOD 		0xFFC01628	// Timer10 Period register
-#define TIMER10_WIDTH 		0xFFC0162C	// Timer10 Width register
-#define TIMER11_CONFIG 		0xFFC01630	// Timer11 Configuration
-						// register
-#define TIMER11_COUNTER		0xFFC01634	// Timer11 Counter register
-#define TIMER11_PERIOD 		0xFFC01638	// Timer11 Period register
-#define TIMER11_WIDTH 		0xFFC0163C	// Timer11 Width register
-
-#define TMRS4_ENABLE 		0xFFC01640	// Timer Enable Register
-#define TMRS4_DISABLE 		0xFFC01644	// Timer Disable register
-#define TMRS4_STATUS 		0xFFC01648	// Timer Status register
-
-// Programmable Flag 0 registers (0xFFC0 0700-0xFFC0 07FF)
-#define FIO0_FLAG_D 		0xFFC00700	// Flag Data register
-#define FIO0_FLAG_C 	        0xFFC00704	// Flag Clear register
-#define FIO0_FLAG_S 	        0xFFC00708	// Flag Set register
-#define FIO0_FLAG_T 	        0xFFC0070C	// Flag Toggle register
-#define FIO0_MASKA_D 	        0xFFC00710	// Flag Mask Interrupt A Data
-			        		// register
-#define FIO0_MASKA_C 	        0xFFC00714	// Flag Mask Interrupt A Clear
-			        		// register
-#define FIO0_MASKA_S 	        0xFFC00718	// Flag Mask Interrupt A Set
-			        		// register
-#define FIO0_MASKA_T 	        0xFFC0071C	// Flag Mask Interrupt A Toggle
-			        		// register
-#define FIO0_MASKB_D 	        0xFFC00720	// Flag Mask Interrupt B Data
-			        		// register
-#define FIO0_MASKB_C 	        0xFFC00724	// Flag Mask Interrupt B Clear
-			        		// register
-#define FIO0_MASKB_S 	        0xFFC00728	// Flag Mask Interrupt B Set
-			        		// register
-#define FIO0_MASKB_T 	        0xFFC0072C	// Flag Mask Interrupt B Toggle
-						// register
-#define FIO0_DIR 		0xFFC00730	// Flag Direction  register
-#define FIO0_POLAR 	        0xFFC00734	// Flag Polarity register
-#define FIO0_EDGE 	        0xFFC00738	// Flag Interrupt Sensitivity
-			        		// register
-#define FIO0_BOTH 	        0xFFC0073C	// Flag Set on Both Edges
-			        		// register
-#define FIO0_INEN 	        0xFFC00740	// Flag Input Enable register
-
-// Programmable Flag 1 registers (0xFFC0 1500-0xFFC0 15FF)
-#define FIO1_FLAG_D 	        0xFFC01500	// Flag Data register
-#define FIO1_FLAG_C 	        0xFFC01504	// Flag Clear register
-#define FIO1_FLAG_S 	        0xFFC01508	// Flag Set register
-#define FIO1_FLAG_T 	        0xFFC0150C	// Flag Toggle register
-#define FIO1_MASKA_D 	        0xFFC01510	// Flag Mask Interrupt A Data
-			        		// register
-#define FIO1_MASKA_C 	        0xFFC01514	// Flag Mask Interrupt A Clear
-			        		// register
-#define FIO1_MASKA_S 	        0xFFC01518	// Flag Mask Interrupt A Set
-			        		// register
-#define FIO1_MASKA_T 	        0xFFC0151C	// Flag Mask Interrupt A Toggle
-			        		// register
-#define FIO1_MASKB_D 	        0xFFC01520	// Flag Mask Interrupt B Data
-			        		// register
-#define FIO1_MASKB_C 	        0xFFC01524	// Flag Mask Interrupt B Clear
-			        		// register
-#define FIO1_MASKB_S 	        0xFFC01528	// Flag Mask Interrupt B Set
-			        		// register
-#define FIO1_MASKB_T 	        0xFFC0152C	// Flag Mask Interrupt B Toggle
-			        		// register
-#define FIO1_DIR 	       	0xFFC01530	// Flag Direction register
-#define FIO1_POLAR 	       	0xFFC01534	// Flag Polarity register
-#define FIO1_EDGE 	       	0xFFC01538	// Flag  Interrupt Sensitivity
-						// register
-#define FIO1_BOTH 	       	0xFFC0153C	// Flag Set on Both Edges
-						// register
-#define FIO1_INEN 	       	0xFFC01540	// Flag Input Enable register
-
-// Programmable Flag registers (0xFFC0 1700-0xFFC0 17FF)
-#define FIO2_FLAG_D 	        0xFFC01700	// Flag Data register
-#define FIO2_FLAG_C 	        0xFFC01704	// Flag Clear register
-#define FIO2_FLAG_S 	        0xFFC01708	// Flag Set register
-#define FIO2_FLAG_T 	        0xFFC0170C	// Flag Toggle register
-#define FIO2_MASKA_D 	        0xFFC01710	// Flag Mask Interrupt A Data
-			        		// register
-#define FIO2_MASKA_C 	        0xFFC01714	// Flag Mask Interrupt A Clear
-			        		// register
-#define FIO2_MASKA_S 	        0xFFC01718	// Flag Mask Interrupt A Set
-			        		// register
-#define FIO2_MASKA_T 	        0xFFC0171C	// Flag Mask Interrupt A Toggle
-			        		// register
-#define FIO2_MASKB_D 	        0xFFC01720	// Flag Mask Interrupt B Data
-			        		// register
-#define FIO2_MASKB_C 	        0xFFC01724	// Flag Mask Interrupt B Clear
-			        		// register
-#define FIO2_MASKB_S 	        0xFFC01728	// Flag Mask Interrupt B Set
-			        		// register
-#define FIO2_MASKB_T 	        0xFFC0172C	// Flag Mask Interrupt B Toggle
-			        		// register
-#define FIO2_DIR 	      	0xFFC01730	// Flag Direction register
-#define FIO2_POLAR 	       	0xFFC01734	// Flag Polarity register
-#define FIO2_EDGE 	       	0xFFC01738	// Flag Interrupt Sensitivity
-						// register
-#define FIO2_BOTH 	       	0xFFC0173C	// Flag Set on Both Edges
-						// register
-#define FIO2_INEN 	       	0xFFC01740	// Flag Input Enable register
-
-//// SPORT0 Controller (0xFFC00800 - 0xFFC008FF)
-#define SPORT0_TCR1      	0xFFC00800	// SPORT0 Transmit
-						// Configuration 1 Register
-#define SPORT0_TCR2      	0xFFC00804	// SPORT0 Transmit
-						// Configuration 2 Register
-#define SPORT0_TCLKDIV  	0xFFC00808	// SPORT0 Transmit Clock Divider
-#define SPORT0_TFSDIV           0xFFC0080C	// SPORT0 Transmit
-			        		// Frame Sync Divider
-#define SPORT0_TX	        0xFFC00810	// SPORT0 TX Data Register
-#define SPORT0_RX	        0xFFC00818	// SPORT0 RX Data Register
-#define SPORT0_RCR1            	0xFFC00820	// SPORT0 Transmit
-						// Configuration 1 Register
-#define SPORT0_RCR2            	0xFFC00824	// SPORT0 Transmit
-						// Configuration 2 Register
-#define SPORT0_RCLKDIV          0xFFC00828	// SPORT0 Receive Clock Divider
-#define SPORT0_RFSDIV           0xFFC0082C	// SPORT0 Receive
-			        		// Frame Sync Divider
-#define SPORT0_STAT             0xFFC00830	// SPORT0 Status Register
-#define SPORT0_CHNL             0xFFC00834	// SPORT0 Current
-			        		// Channel Register
-#define SPORT0_MCMC1            0xFFC00838	// SPORT0 Multi-Channel
-			        		// Configuration Register 1
-#define SPORT0_MCMC2            0xFFC0083C	// SPORT0 Multi-Channel
-			        		// Configuration Register 2
-#define SPORT0_MTCS0            0xFFC00840	// SPORT0 Multi-Channel
-			        		// Transmit Select Register 0
-#define SPORT0_MTCS1            0xFFC00844	// SPORT0 Multi-Channel
-			        		// Transmit Select Register 1
-#define SPORT0_MTCS2            0xFFC00848	// SPORT0 Multi-Channel
-			        		// Transmit Select Register 2
-#define SPORT0_MTCS3            0xFFC0084C	// SPORT0 Multi-Channel
-			        		// Transmit Select Register 3
-#define SPORT0_MRCS0            0xFFC00850	// SPORT0 Multi-Channel
-			        		// Receive Select Register 0
-#define SPORT0_MRCS1            0xFFC00854	// SPORT0 Multi-Channel
-			        		// Receive Select Register 1
-#define SPORT0_MRCS2            0xFFC00858	// SPORT0 Multi-Channel
-			        		// Receive Select Register 2
-#define SPORT0_MRCS3            0xFFC0085C	// SPORT0 Multi-Channel
-			        		// Receive Select Register 3
-
-//// SPORT1 Controller (0xFFC00900 - 0xFFC009FF)
-#define SPORT1_TCR1             0xFFC00900	// SPORT1 Transmit
-			        		// Configuration 1 Register
-#define SPORT1_TCR2             0xFFC00904	// SPORT1 Transmit
-			        		// Configuration 2 Register
-#define SPORT1_TCLKDIV        	0xFFC00908	// SPORT1 Transmit Clock Divider
-#define SPORT1_TFSDIV          	0xFFC0090C	// SPORT1 Transmit
-						// Frame Sync Divider
-#define SPORT1_TX	        0xFFC00910	// SPORT1 TX Data Register
-#define SPORT1_RX	        0xFFC00918	// SPORT1 RX Data Register
-#define SPORT1_RCR1      	0xFFC00920	// SPORT1 Transmit
-						// Configuration 1 Register
-#define SPORT1_RCR2   		0xFFC00924	// SPORT1 Transmit
-						// Configuration 2 Register
-#define SPORT1_RCLKDIV    	0xFFC00928	// SPORT1 Receive Clock Divider
-#define SPORT1_RFSDIV           0xFFC0092C	// SPORT1 Receive
-			        		// Frame Sync Divider
-#define SPORT1_STAT             0xFFC00930	// SPORT1 Status Register
-#define SPORT1_CHNL             0xFFC00934	// SPORT1 Current
-			        		// Channel Register
-#define SPORT1_MCMC1            0xFFC00938	// SPORT1 Multi-Channel
-			        		// Configuration Register 1
-#define SPORT1_MCMC2            0xFFC0093C	// SPORT1 Multi-Channel
-			        		// Configuration Register 2
-#define SPORT1_MTCS0            0xFFC00940	// SPORT1 Multi-Channel
-			        		// Transmit Select Register 0
-#define SPORT1_MTCS1            0xFFC00944	// SPORT1 Multi-Channel
-			        		// Transmit Select Register 1
-#define SPORT1_MTCS2            0xFFC00948	// SPORT1 Multi-Channel
-			        		// Transmit Select Register 2
-#define SPORT1_MTCS3            0xFFC0094C	// SPORT1 Multi-Channel
-			        		// Transmit Select Register 3
-#define SPORT1_MRCS0            0xFFC00950	// SPORT1 Multi-Channel
-			        		// Receive Select Register 0
-#define SPORT1_MRCS1            0xFFC00954	// SPORT1 Multi-Channel
-			        		// Receive Select Register 1
-#define SPORT1_MRCS2            0xFFC00958	// SPORT1 Multi-Channel
-			        		// Receive Select Register 2
-#define SPORT1_MRCS3            0xFFC0095C	// SPORT1 Multi-Channel
-			        		// Receive Select Register 3
-
-// Asynchronous Memory Controller - External Bus Interface Unit
-#define EBIU_AMGCTL		0xFFC00A00	// Asynchronous Memory
-						// Global Control Register
-#define EBIU_AMBCTL0		0xFFC00A04	// Asynchronous Memory
-						// Bank Control Register 0
-#define EBIU_AMBCTL1		0xFFC00A08	// Asynchronous Memory
-						// Bank Control Register 1
-
-// SDRAM Controller External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF)
-#define EBIU_SDGCTL		0xFFC00A10	// SDRAM Global Control
-						// Register
-#define EBIU_SDBCTL		0xFFC00A14	// SDRAM Bank Control Register
-#define EBIU_SDRRC 		0xFFC00A18	// SDRAM Refresh Rate Control
-						// Register
-#define EBIU_SDSTAT		0xFFC00A1C	// SDRAM Status Register
-
-// Parallel Peripheral Interface (PPI) 0 registers (0xFFC0 1000-0xFFC0 10FF)
-#define PPI0_CONTROL 		0xFFC01000	// PPI0 Control register
-#define PPI0_STATUS 		0xFFC01004	// PPI0 Status register
-#define PPI0_COUNT 		0xFFC01008	// PPI0 Transfer Count register
-#define PPI0_DELAY 		0xFFC0100C	// PPI0 Delay Count register
-#define PPI0_FRAME 		0xFFC01010	// PPI0 Frame Length register
-
-//Parallel Peripheral Interface (PPI) 1 registers (0xFFC0 1300-0xFFC0 13FF)
-#define PPI1_CONTROL		0xFFC01300	// PPI1 Control register
-#define PPI1_STATUS 		0xFFC01304	// PPI1 Status register
-#define PPI1_COUNT 		0xFFC01308	// PPI1 Transfer Count register
-#define PPI1_DELAY 		0xFFC0130C	// PPI1 Delay Count register
-#define PPI1_FRAME 		0xFFC01310	// PPI1 Frame Length register
-
-// DMA Traffic controls
-#define DMA_TCPER		0xFFC00B0C	// Traffic Control Periods
-						// Register
-#define DMA_TCCNT		0xFFC00B10	// Traffic Control Current
-						// Counts Register
-#define DMA_TC_PER		0xFFC00B0C	// Traffic Control Periods
-						// Register
-#define DMA_TC_CNT		0xFFC00B10	// Traffic Control Current
-						// Counts Register
-
-// DMA1 Controller registers (0xFFC0 1C00-0xFFC0 1FFF)
-#define DMA1_0_CONFIG		0xFFC01C08	// DMA1 Channel 0 Configuration
-						// register
-#define DMA1_0_NEXT_DESC_PTR	0xFFC01C00	// DMA1 Channel 0 Next
-						// Descripter Ptr Reg
-#define DMA1_0_START_ADDR	0xFFC01C04	// DMA1 Channel 0 Start Address
-#define DMA1_0_X_COUNT		0xFFC01C10	// DMA1 Channel 0 Inner Loop
-						// Count
-#define DMA1_0_Y_COUNT		0xFFC01C18	// DMA1 Channel 0 Outer Loop
-						// Count
-#define DMA1_0_X_MODIFY		0xFFC01C14	// DMA1 Channel 0 Inner Loop
-						// Addr Increment
-#define DMA1_0_Y_MODIFY		0xFFC01C1C	// DMA1 Channel 0 Outer Loop
-						// Addr Increment
-#define DMA1_0_CURR_DESC_PTR	0xFFC01C20	// DMA1 Channel 0 Current
-						// Descriptor Pointer
-#define DMA1_0_CURR_ADDR	0xFFC01C24	// DMA1 Channel 0 Current
-						// Address Pointer
-#define DMA1_0_CURR_X_COUNT	0xFFC01C30	// DMA1 Channel 0 Current Inner
-						// Loop Count
-#define DMA1_0_CURR_Y_COUNT	0xFFC01C38	// DMA1 Channel 0 Current Outer
-						// Loop Count
-#define DMA1_0_IRQ_STATUS	0xFFC01C28	// DMA1 Channel 0 Interrupt
-						// Status Register
-#define DMA1_0_PERIPHERAL_MAP	0xFFC01C2C	// DMA1 Channel 0 Peripheral
-						// Map Register
-
-#define DMA1_1_CONFIG		0xFFC01C48	// DMA1 Channel 1 Configuration
-						// register
-#define DMA1_1_NEXT_DESC_PTR	0xFFC01C40	// DMA1 Channel 1 Next
-						// Descripter Ptr Reg
-#define DMA1_1_START_ADDR	0xFFC01C44	// DMA1 Channel 1 Start Address
-#define DMA1_1_X_COUNT		0xFFC01C50	// DMA1 Channel 1 Inner Loop
-						// Count
-#define DMA1_1_Y_COUNT		0xFFC01C58	// DMA1 Channel 1 Outer Loop
-						// Count
-#define DMA1_1_X_MODIFY		0xFFC01C54	// DMA1 Channel 1 Inner Loop
-						// Addr Increment
-#define DMA1_1_Y_MODIFY		0xFFC01C5C	// DMA1 Channel 1 Outer Loop
-						// Addr Increment
-#define DMA1_1_CURR_DESC_PTR	0xFFC01C60	// DMA1 Channel 1 Current
-						// Descriptor Pointer
-#define DMA1_1_CURR_ADDR	0xFFC01C64	// DMA1 Channel 1 Current
-						// Address Pointer
-#define DMA1_1_CURR_X_COUNT	0xFFC01C70	// DMA1 Channel 1 Current Inner
-						// Loop Count
-#define DMA1_1_CURR_Y_COUNT	0xFFC01C78	// DMA1 Channel 1 Current Outer
-						// Loop Count
-#define DMA1_1_IRQ_STATUS	0xFFC01C68	// DMA1 Channel 1 Interrupt
-						// Status Register
-#define DMA1_1_PERIPHERAL_MAP	0xFFC01C6C	// DMA1 Channel 1 Peripheral
-						// Map Register
-
-#define DMA1_2_CONFIG		0xFFC01C88	// DMA1 Channel 2 Configuration
-						// register
-#define DMA1_2_NEXT_DESC_PTR	0xFFC01C80	// DMA1 Channel 2 Next
-						// Descripter Ptr Reg
-#define DMA1_2_START_ADDR	0xFFC01C84	// DMA1 Channel 2 Start Address
-#define DMA1_2_X_COUNT		0xFFC01C90	// DMA1 Channel 2 Inner Loop
-						// Count
-#define DMA1_2_Y_COUNT		0xFFC01C98	// DMA1 Channel 2 Outer Loop
-						// Count
-#define DMA1_2_X_MODIFY		0xFFC01C94	// DMA1 Channel 2 Inner Loop
-						// Addr Increment
-#define DMA1_2_Y_MODIFY		0xFFC01C9C	// DMA1 Channel 2 Outer Loop
-						// Addr Increment
-#define DMA1_2_CURR_DESC_PTR	0xFFC01CA0	// DMA1 Channel 2 Current
-						// Descriptor Pointer
-#define DMA1_2_CURR_ADDR	0xFFC01CA4	// DMA1 Channel 2 Current
-						// Address Pointer
-#define DMA1_2_CURR_X_COUNT	0xFFC01CB0	// DMA1 Channel 2 Current Inner
-						// Loop Count
-#define DMA1_2_CURR_Y_COUNT	0xFFC01CB8	// DMA1 Channel 2 Current Outer
-						// Loop Count
-#define DMA1_2_IRQ_STATUS	0xFFC01CA8	// DMA1 Channel 2 Interrupt
-						// Status Register
-#define DMA1_2_PERIPHERAL_MAP	0xFFC01CAC	// DMA1 Channel 2 Peripheral
-						// Map Register
-
-#define DMA1_3_CONFIG		0xFFC01CC8	// DMA1 Channel 3 Configuration
-						// register
-#define DMA1_3_NEXT_DESC_PTR	0xFFC01CC0	// DMA1 Channel 3 Next
-						// Descripter Ptr Reg
-#define DMA1_3_START_ADDR	0xFFC01CC4	// DMA1 Channel 3 Start Address
-#define DMA1_3_X_COUNT		0xFFC01CD0	// DMA1 Channel 3 Inner Loop
-						// Count
-#define DMA1_3_Y_COUNT		0xFFC01CD8	// DMA1 Channel 3 Outer Loop
-						// Count
-#define DMA1_3_X_MODIFY		0xFFC01CD4	// DMA1 Channel 3 Inner Loop
-						// Addr Increment
-#define DMA1_3_Y_MODIFY		0xFFC01CDC	// DMA1 Channel 3 Outer Loop
-						// Addr Increment
-#define DMA1_3_CURR_DESC_PTR	0xFFC01CE0	// DMA1 Channel 3 Current
-						// Descriptor Pointer
-#define DMA1_3_CURR_ADDR	0xFFC01CE4	// DMA1 Channel 3 Current
-						// Address Pointer
-#define DMA1_3_CURR_X_COUNT	0xFFC01CF0	// DMA1 Channel 3 Current Inner
-						// Loop Count
-#define DMA1_3_CURR_Y_COUNT	0xFFC01CF8	// DMA1 Channel 3 Current Outer
-						// Loop Count
-#define DMA1_3_IRQ_STATUS	0xFFC01CE8	// DMA1 Channel 3 Interrupt
-						// Status Register
-#define DMA1_3_PERIPHERAL_MAP	0xFFC01CEC	// DMA1 Channel 3 Peripheral
-						// Map Register
-
-#define DMA1_4_CONFIG		0xFFC01D08	// DMA1 Channel 4 Configuration
-						// register
-#define DMA1_4_NEXT_DESC_PTR	0xFFC01D00	// DMA1 Channel 4 Next
-						// Descripter Ptr Reg
-#define DMA1_4_START_ADDR	0xFFC01D04	// DMA1 Channel 4 Start Address
-#define DMA1_4_X_COUNT		0xFFC01D10	// DMA1 Channel 4 Inner Loop
-						// Count
-#define DMA1_4_Y_COUNT		0xFFC01D18	// DMA1 Channel 4 Outer Loop
-						// Count
-#define DMA1_4_X_MODIFY		0xFFC01D14	// DMA1 Channel 4 Inner Loop
-						// Addr Increment
-#define DMA1_4_Y_MODIFY		0xFFC01D1C	// DMA1 Channel 4 Outer Loop
-						// Addr Increment
-#define DMA1_4_CURR_DESC_PTR	0xFFC01D20	// DMA1 Channel 4 Current
-						// Descriptor Pointer
-#define DMA1_4_CURR_ADDR	0xFFC01D24	// DMA1 Channel 4 Current
-						// Address Pointer
-#define DMA1_4_CURR_X_COUNT	0xFFC01D30	// DMA1 Channel 4 Current Inner
-						// Loop Count
-#define DMA1_4_CURR_Y_COUNT	0xFFC01D38	// DMA1 Channel 4 Current Outer
-						// Loop Count
-#define DMA1_4_IRQ_STATUS	0xFFC01D28	// DMA1 Channel 4 Interrupt
-						// Status Register
-#define DMA1_4_PERIPHERAL_MAP	0xFFC01D2C	// DMA1 Channel 4 Peripheral
-						// Map Register
-
-#define DMA1_5_CONFIG		0xFFC01D48	// DMA1 Channel 5 Configuration
-						// register
-#define DMA1_5_NEXT_DESC_PTR	0xFFC01D40	// DMA1 Channel 5 Next
-						// Descripter Ptr Reg
-#define DMA1_5_START_ADDR	0xFFC01D44	// DMA1 Channel 5 Start Address
-#define DMA1_5_X_COUNT		0xFFC01D50	// DMA1 Channel 5 Inner Loop
-						// Count
-#define DMA1_5_Y_COUNT		0xFFC01D58	// DMA1 Channel 5 Outer Loop
-						// Count
-#define DMA1_5_X_MODIFY		0xFFC01D54	// DMA1 Channel 5 Inner Loop
-						// Addr Increment
-#define DMA1_5_Y_MODIFY		0xFFC01D5C	// DMA1 Channel 5 Outer Loop
-						// Addr Increment
-#define DMA1_5_CURR_DESC_PTR	0xFFC01D60	// DMA1 Channel 5 Current
-						// Descriptor Pointer
-#define DMA1_5_CURR_ADDR	0xFFC01D64	// DMA1 Channel 5 Current
-						// Address Pointer
-#define DMA1_5_CURR_X_COUNT	0xFFC01D70	// DMA1 Channel 5 Current Inner
-						// Loop Count
-#define DMA1_5_CURR_Y_COUNT	0xFFC01D78	// DMA1 Channel 5 Current Outer
-						// Loop Count
-#define DMA1_5_IRQ_STATUS	0xFFC01D68	// DMA1 Channel 5 Interrupt
-						// Status Register
-#define DMA1_5_PERIPHERAL_MAP	0xFFC01D6C	// DMA1 Channel 5 Peripheral
-						// Map Register
-
-#define DMA1_6_CONFIG		0xFFC01D88	// DMA1 Channel 6 Configuration
-						// register
-#define DMA1_6_NEXT_DESC_PTR	0xFFC01D80	// DMA1 Channel 6 Next
-						// Descripter Ptr Reg
-#define DMA1_6_START_ADDR	0xFFC01D84	// DMA1 Channel 6 Start Address
-#define DMA1_6_X_COUNT		0xFFC01D90	// DMA1 Channel 6 Inner Loop
-						// Count
-#define DMA1_6_Y_COUNT		0xFFC01D98	// DMA1 Channel 6 Outer Loop
-						// Count
-#define DMA1_6_X_MODIFY		0xFFC01D94	// DMA1 Channel 6 Inner Loop
-						// Addr Increment
-#define DMA1_6_Y_MODIFY		0xFFC01D9C	// DMA1 Channel 6 Outer Loop
-						// Addr Increment
-#define DMA1_6_CURR_DESC_PTR	0xFFC01DA0	// DMA1 Channel 6 Current
-						// Descriptor Pointer
-#define DMA1_6_CURR_ADDR	0xFFC01DA4	// DMA1 Channel 6 Current
-						// Address Pointer
-#define DMA1_6_CURR_X_COUNT	0xFFC01DB0	// DMA1 Channel 6 Current Inner
-						// Loop Count
-#define DMA1_6_CURR_Y_COUNT	0xFFC01DB8	// DMA1 Channel 6 Current Outer
-						// Loop Count
-#define DMA1_6_IRQ_STATUS	0xFFC01DA8	// DMA1 Channel 6 Interrupt
-						// /Status Register
-#define DMA1_6_PERIPHERAL_MAP	0xFFC01DAC	// DMA1 Channel 6 Peripheral
-						// Map Register
-
-#define DMA1_7_CONFIG		0xFFC01DC8	// DMA1 Channel 7 Configuration
-						// register
-#define DMA1_7_NEXT_DESC_PTR	0xFFC01DC0	// DMA1 Channel 7 Next
-						// Descripter Ptr Reg
-#define DMA1_7_START_ADDR	0xFFC01DC4	// DMA1 Channel 7 Start Address
-#define DMA1_7_X_COUNT		0xFFC01DD0	// DMA1 Channel 7 Inner Loop
-						// Count
-#define DMA1_7_Y_COUNT		0xFFC01DD8	// DMA1 Channel 7 Outer Loop
-						// Count
-#define DMA1_7_X_MODIFY		0xFFC01DD4	// DMA1 Channel 7 Inner Loop
-						// Addr Increment
-#define DMA1_7_Y_MODIFY		0xFFC01DDC	// DMA1 Channel 7 Outer Loop
-						// Addr Increment
-#define DMA1_7_CURR_DESC_PTR	0xFFC01DE0	// DMA1 Channel 7 Current
-						// Descriptor Pointer
-#define DMA1_7_CURR_ADDR	0xFFC01DE4	// DMA1 Channel 7 Current
-						// Address Pointer
-#define DMA1_7_CURR_X_COUNT	0xFFC01DF0	// DMA1 Channel 7 Current Inner
-						// Loop Count
-#define DMA1_7_CURR_Y_COUNT	0xFFC01DF8	// DMA1 Channel 7 Current Outer
-						// Loop Count
-#define DMA1_7_IRQ_STATUS	0xFFC01DE8	// DMA1 Channel 7 Interrupt
-						// /Status Register
-#define DMA1_7_PERIPHERAL_MAP	0xFFC01DEC	// DMA1 Channel 7 Peripheral
-						// Map Register
-
-#define DMA1_8_CONFIG		0xFFC01E08	// DMA1 Channel 8 Configuration
-						// register
-#define DMA1_8_NEXT_DESC_PTR	0xFFC01E00	// DMA1 Channel 8 Next
-						// Descripter Ptr Reg
-#define DMA1_8_START_ADDR	0xFFC01E04	// DMA1 Channel 8 Start Address
-#define DMA1_8_X_COUNT		0xFFC01E10	// DMA1 Channel 8 Inner Loop
-						// Count
-#define DMA1_8_Y_COUNT		0xFFC01E18	// DMA1 Channel 8 Outer Loop
-						// Count
-#define DMA1_8_X_MODIFY		0xFFC01E14	// DMA1 Channel 8 Inner Loop
-						// Addr Increment
-#define DMA1_8_Y_MODIFY		0xFFC01E1C	// DMA1 Channel 8 Outer Loop
-						// Addr Increment
-#define DMA1_8_CURR_DESC_PTR	0xFFC01E20	// DMA1 Channel 8 Current
-						// Descriptor Pointer
-#define DMA1_8_CURR_ADDR	0xFFC01E24	// DMA1 Channel 8 Current
-						// Address Pointer
-#define DMA1_8_CURR_X_COUNT	0xFFC01E30	// DMA1 Channel 8 Current Inner
-						// Loop Count
-#define DMA1_8_CURR_Y_COUNT	0xFFC01E38	// DMA1 Channel 8 Current Outer
-						// Loop Count
-#define DMA1_8_IRQ_STATUS	0xFFC01E28	// DMA1 Channel 8 Interrupt
-						// /Status Register
-#define DMA1_8_PERIPHERAL_MAP	0xFFC01E2C	// DMA1 Channel 8 Peripheral
-						// Map Register
-
-#define DMA1_9_CONFIG		0xFFC01E48	// DMA1 Channel 9 Configuration
-						// register
-#define DMA1_9_NEXT_DESC_PTR	0xFFC01E40	// DMA1 Channel 9 Next
-						// Descripter Ptr Reg
-#define DMA1_9_START_ADDR	0xFFC01E44	// DMA1 Channel 9 Start Address
-#define DMA1_9_X_COUNT		0xFFC01E50	// DMA1 Channel 9 Inner Loop
-						// Count
-#define DMA1_9_Y_COUNT		0xFFC01E58	// DMA1 Channel 9 Outer Loop
-						// Count
-#define DMA1_9_X_MODIFY		0xFFC01E54	// DMA1 Channel 9 Inner Loop
-						// Addr Increment
-#define DMA1_9_Y_MODIFY		0xFFC01E5C	// DMA1 Channel 9 Outer Loop
-						// Addr Increment
-#define DMA1_9_CURR_DESC_PTR	0xFFC01E60	// DMA1 Channel 9 Current
-						// Descriptor Pointer
-#define DMA1_9_CURR_ADDR	0xFFC01E64	// DMA1 Channel 9 Current
-						// Address Pointer
-#define DMA1_9_CURR_X_COUNT	0xFFC01E70	// DMA1 Channel 9 Current Inner
-						// Loop Count
-#define DMA1_9_CURR_Y_COUNT	0xFFC01E78	// DMA1 Channel 9 Current Outer
-						// Loop Count
-#define DMA1_9_IRQ_STATUS	0xFFC01E68	// DMA1 Channel 9 Interrupt
-						// /Status Register
-#define DMA1_9_PERIPHERAL_MAP	0xFFC01E6C	// DMA1 Channel 9 Peripheral
-						// Map Register
-
-#define DMA1_10_CONFIG		0xFFC01E88	// DMA1 Channel 10 Configuration
-						// register
-#define DMA1_10_NEXT_DESC_PTR	0xFFC01E80	// DMA1 Channel 10 Next
-						// Descripter Ptr Reg
-#define DMA1_10_START_ADDR	0xFFC01E84	// DMA1 Channel 10 Start Address
-#define DMA1_10_X_COUNT		0xFFC01E90	// DMA1 Channel 10 Inner Loop
-						// Count
-#define DMA1_10_Y_COUNT		0xFFC01E98	// DMA1 Channel 10 Outer Loop
-						// Count
-#define DMA1_10_X_MODIFY	0xFFC01E94	// DMA1 Channel 10 Inner Loop
-						// Addr Increment
-#define DMA1_10_Y_MODIFY	0xFFC01E9C	// DMA1 Channel 10 Outer Loop
-						// Addr Increment
-#define DMA1_10_CURR_DESC_PTR	0xFFC01EA0	// DMA1 Channel 10 Current
-						// Descriptor Pointer
-#define DMA1_10_CURR_ADDR	0xFFC01EA4	// DMA1 Channel 10 Current
-						// Address Pointer
-#define DMA1_10_CURR_X_COUNT	0xFFC01EB0	// DMA1 Channel 10 Current Inner
-						// Loop Count
-#define DMA1_10_CURR_Y_COUNT	0xFFC01EB8	// DMA1 Channel 10 Current Outer
-						// Loop Count
-#define DMA1_10_IRQ_STATUS	0xFFC01EA8	// DMA1 Channel 10 Interrupt
-						// /Status Register
-#define DMA1_10_PERIPHERAL_MAP	0xFFC01EAC	// DMA1 Channel 10 Peripheral
-						// Map Register
-
-#define DMA1_11_CONFIG		0xFFC01EC8	// DMA1 Channel 11 Configuration
-						// register
-#define DMA1_11_NEXT_DESC_PTR	0xFFC01EC0	// DMA1 Channel 11 Next
-						// Descripter Ptr Reg
-#define DMA1_11_START_ADDR	0xFFC01EC4	// DMA1 Channel 11 Start Address
-#define DMA1_11_X_COUNT		0xFFC01ED0	// DMA1 Channel 11 Inner Loop
-						// Count
-#define DMA1_11_Y_COUNT		0xFFC01ED8	// DMA1 Channel 11 Outer Loop
-						// Count
-#define DMA1_11_X_MODIFY	0xFFC01ED4	// DMA1 Channel 11 Inner Loop
-						// Addr Increment
-#define DMA1_11_Y_MODIFY	0xFFC01EDC	// DMA1 Channel 11 Outer Loop
-						// Addr Increment
-#define DMA1_11_CURR_DESC_PTR	0xFFC01EE0	// DMA1 Channel 11 Current
-						// Descriptor Pointer
-#define DMA1_11_CURR_ADDR	0xFFC01EE4	// DMA1 Channel 11 Current
-						// Address Pointer
-#define DMA1_11_CURR_X_COUNT	0xFFC01EF0	// DMA1 Channel 11 Current Inner
-						// Loop Count
-#define DMA1_11_CURR_Y_COUNT	0xFFC01EF8	// DMA1 Channel 11 Current Outer
-						// Loop Count
-#define DMA1_11_IRQ_STATUS	0xFFC01EE8	// DMA1 Channel 11 Interrupt
-						// /Status Register
-#define DMA1_11_PERIPHERAL_MAP	0xFFC01EEC	// DMA1 Channel 11 Peripheral
-						// Map Register
-
-// Memory DMA1 Controller registers (0xFFC0 1E80-0xFFC0 1FFF)
-#define MDMA1_D0_CONFIG		0xFFC01F08	// MemDMA1 Stream 0 Destination
-						// Configuration
-#define MDMA1_D0_NEXT_DESC_PTR	0xFFC01F00	// MemDMA1 Stream 0
-						// Destination Next
-						// Descriptor Ptr Reg
-#define MDMA1_D0_START_ADDR	0xFFC01F04	// MemDMA1 Stream 0 Destination
-						// Start Address
-#define MDMA1_D0_X_COUNT	0xFFC01F10	// MemDMA1 Stream 0 Destination
-						// Inner-Loop Count
-#define MDMA1_D0_Y_COUNT	0xFFC01F18	// MemDMA1 Stream 0 Destination
-						// Outer-Loop Count
-#define MDMA1_D0_X_MODIFY	0xFFC01F14	// MemDMA1 Stream 0 Dest
-						// Inner-Loop Address-Increment
-#define MDMA1_D0_Y_MODIFY	0xFFC01F1C	// MemDMA1 Stream 0 Dest
-						// Outer-Loop Address-Increment
-#define MDMA1_D0_CURR_DESC_PTR	0xFFC01F20	// MemDMA1 Stream 0 Dest
-						// Current Descriptor Ptr reg
-#define MDMA1_D0_CURR_ADDR	0xFFC01F24	// MemDMA1 Stream 0 Destination
-						// Current Address
-#define MDMA1_D0_CURR_X_COUNT	0xFFC01F30	// MemDMA1 Stream 0 Dest
-						// Current Inner-Loop Count
-#define MDMA1_D0_CURR_Y_COUNT	0xFFC01F38	// MemDMA1 Stream 0 Dest
-						// Current Outer-Loop Count
-#define MDMA1_D0_IRQ_STATUS	0xFFC01F28	// MemDMA1 Stream 0 Destination
-						// Interrupt/Status
-#define MDMA1_D0_PERIPHERAL_MAP	0xFFC01F2C	// MemDMA1 Stream 0
-						// Destination Peripheral Map
-
-#define MDMA1_S0_CONFIG		0xFFC01F48	// MemDMA1 Stream 0 Source
-						// Configuration
-#define MDMA1_S0_NEXT_DESC_PTR	0xFFC01F40	// MemDMA1 Stream 0 Source
-						// Next Descriptor Ptr Reg
-#define MDMA1_S0_START_ADDR	0xFFC01F44	// MemDMA1 Stream 0 Source
-						// Start Address
-#define MDMA1_S0_X_COUNT	0xFFC01F50	// MemDMA1 Stream 0 Source
-						// Inner-Loop Count
-#define MDMA1_S0_Y_COUNT	0xFFC01F58	// MemDMA1 Stream 0 Source
-						// Outer-Loop Count
-#define MDMA1_S0_X_MODIFY	0xFFC01F54	// MemDMA1 Stream 0 Source
-						// Inner-Loop Address-Increment
-#define MDMA1_S0_Y_MODIFY	0xFFC01F5C	// MemDMA1 Stream 0 Source
-						// Outer-Loop Address-Increment
-#define MDMA1_S0_CURR_DESC_PTR	0xFFC01F60	// MemDMA1 Stream 0 Source
-						// Current Descriptor Ptr reg
-#define MDMA1_S0_CURR_ADDR	0xFFC01F64	// MemDMA1 Stream 0 Source
-						// Current Address
-#define MDMA1_S0_CURR_X_COUNT	0xFFC01F70	// MemDMA1 Stream 0 Source
-						// Current Inner-Loop Count
-#define MDMA1_S0_CURR_Y_COUNT `	0xFFC01F78	// MemDMA1 Stream 0 Source
-						// Current Outer-Loop Count
-#define MDMA1_S0_IRQ_STATUS	0xFFC01F68	// MemDMA1 Stream 0 Source
-						// Interrupt/Status
-#define MDMA1_S0_PERIPHERAL_MAP 0xFFC01F6C	// MemDMA1 Stream 0 Source
-						// Peripheral Map
-
-#define MDMA1_D1_CONFIG		0xFFC01F88	// MemDMA1 Stream 1 Destination
-						// Configuration
-#define MDMA1_D1_NEXT_DESC_PTR	0xFFC01F80	// MemDMA1 Stream 1
-						// Destination Next
-						// Descriptor Ptr Reg
-#define MDMA1_D1_START_ADDR	0xFFC01F84	// MemDMA1 Stream 1 Destination
-						// Start Address
-#define MDMA1_D1_X_COUNT	0xFFC01F90	// MemDMA1 Stream 1 Destination
-						// Inner-Loop Count
-#define MDMA1_D1_Y_COUNT	0xFFC01F98	// MemDMA1 Stream 1 Destination
-						// Outer-Loop Count
-#define MDMA1_D1_X_MODIFY	0xFFC01F94	// MemDMA1 Stream 1 Dest
-						// Inner-Loop Address-Increment
-#define MDMA1_D1_Y_MODIFY	0xFFC01F9C	// MemDMA1 Stream 1 Dest
-						// Outer-Loop Address-Increment
-#define MDMA1_D1_CURR_DESC_PTR	0xFFC01FA0	// MemDMA1 Stream 1 Dest
-						// Current Descriptor Ptr reg
-#define MDMA1_D1_CURR_ADDR	0xFFC01FA4	// MemDMA1 Stream 1 Dest
-						// Current Address
-#define MDMA1_D1_CURR_X_COUNT	0xFFC01FB0	// MemDMA1 Stream 1 Dest
-						// Current Inner-Loop Count
-#define MDMA1_D1_CURR_Y_COUNT	0xFFC01FB8	// MemDMA1 Stream 1 Dest
-						// Current Outer-Loop Count
-#define MDMA1_D1_IRQ_STATUS	0xFFC01FA8	// MemDMA1 Stream 1 Dest
-						// Interrupt/Status
-#define MDMA1_D1_PERIPHERAL_MAP 0xFFC01FAC	// MemDMA1 Stream 1 Dest
-						// Peripheral Map
-
-#define MDMA1_S1_CONFIG		0xFFC01FC8	// MemDMA1 Stream 1 Source
-						// Configuration
-#define MDMA1_S1_NEXT_DESC_PTR	0xFFC01FC0	// MemDMA1 Stream 1 Source
-						// Next Descriptor Ptr Reg
-#define MDMA1_S1_START_ADDR	0xFFC01FC4	// MemDMA1 Stream 1 Source
-						// Start Address
-#define MDMA1_S1_X_COUNT	0xFFC01FD0	// MemDMA1 Stream 1 Source
-						// Inner-Loop Count
-#define MDMA1_S1_Y_COUNT	0xFFC01FD8	// MemDMA1 Stream 1 Source
-						// Outer-Loop Count
-#define MDMA1_S1_X_MODIFY	0xFFC01FD4	// MemDMA1 Stream 1 Source
-						// Inner-Loop Address-Increment
-#define MDMA1_S1_Y_MODIFY	0xFFC01FDC	// MemDMA1 Stream 1 Source
-						// Outer-Loop Address-Increment
-#define MDMA1_S1_CURR_DESC_PTR	0xFFC01FE0	// MemDMA1 Stream 1 Source
-						// Current Descriptor Ptr reg
-#define MDMA1_S1_CURR_ADDR	0xFFC01FE4	// MemDMA1 Stream 1 Source
-						// Current Address
-#define MDMA1_S1_CURR_X_COUNT	0xFFC01FF0	// MemDMA1 Stream 1 Source
-						// Current Inner-Loop Count
-#define MDMA1_S1_CURR_Y_COUNT	0xFFC01FF8	// MemDMA1 Stream 1 Source
-						// Current Outer-Loop Count
-#define MDMA1_S1_IRQ_STATUS	0xFFC01FE8	// MemDMA1 Stream 1 Source
-						// Interrupt/Status
-#define MDMA1_S1_PERIPHERAL_MAP 0xFFC01FEC	// MemDMA1 Stream 1 Source
-						// Peripheral Map
-
-// DMA2 Controller registers (0xFFC0 0C00-0xFFC0 0DFF)
-#define DMA2_0_CONFIG		0xFFC00C08	// DMA2 Channel 0 Configuration
-						// register
-#define DMA2_0_NEXT_DESC_PTR	0xFFC00C00	// DMA2 Channel 0 Next
-						// Descripter Ptr Reg
-#define DMA2_0_START_ADDR	0xFFC00C04	// DMA2 Channel 0 Start Address
-#define DMA2_0_X_COUNT		0xFFC00C10	// DMA2 Channel 0 Inner Loop
-						// Count
-#define DMA2_0_Y_COUNT		0xFFC00C18	// DMA2 Channel 0 Outer Loop
-						// Count
-#define DMA2_0_X_MODIFY		0xFFC00C14	// DMA2 Channel 0 Inner Loop
-						// Addr Increment
-#define DMA2_0_Y_MODIFY		0xFFC00C1C	// DMA2 Channel 0 Outer Loop
-						// Addr Increment
-#define DMA2_0_CURR_DESC_PTR	0xFFC00C20	// DMA2 Channel 0 Current
-						// Descriptor Pointer
-#define DMA2_0_CURR_ADDR	0xFFC00C24	// DMA2 Channel 0 Current
-						// Address Pointer
-#define DMA2_0_CURR_X_COUNT	0xFFC00C30	// DMA2 Channel 0 Current Inner
-						// Loop Count
-#define DMA2_0_CURR_Y_COUNT	0xFFC00C38	// DMA2 Channel 0 Current Outer
-						// Loop Count
-#define DMA2_0_IRQ_STATUS	0xFFC00C28	// DMA2 Channel 0 Interrupt
-						// /Status Register
-#define DMA2_0_PERIPHERAL_MAP	0xFFC00C2C	// DMA2 Channel 0 Peripheral
-						// Map Register
-
-#define DMA2_1_CONFIG		0xFFC00C48	// DMA2 Channel 1 Configuration
-						// register
-#define DMA2_1_NEXT_DESC_PTR	0xFFC00C40	// DMA2 Channel 1 Next
-						// Descripter Ptr Reg
-#define DMA2_1_START_ADDR	0xFFC00C44	// DMA2 Channel 1 Start Address
-#define DMA2_1_X_COUNT		0xFFC00C50	// DMA2 Channel 1 Inner Loop
-						// Count
-#define DMA2_1_Y_COUNT		0xFFC00C58	// DMA2 Channel 1 Outer Loop
-						// Count
-#define DMA2_1_X_MODIFY		0xFFC00C54	// DMA2 Channel 1 Inner Loop
-						// Addr Increment
-#define DMA2_1_Y_MODIFY		0xFFC00C5C	// DMA2 Channel 1 Outer Loop
-						// Addr Increment
-#define DMA2_1_CURR_DESC_PTR	0xFFC00C60	// DMA2 Channel 1 Current
-						// Descriptor Pointer
-#define DMA2_1_CURR_ADDR	0xFFC00C64	// DMA2 Channel 1 Current
-						// Address Pointer
-#define DMA2_1_CURR_X_COUNT	0xFFC00C70	// DMA2 Channel 1 Current
-						// Inner Loop Count
-#define DMA2_1_CURR_Y_COUNT	0xFFC00C78	// DMA2 Channel 1 Current
-						// Outer Loop Count
-#define DMA2_1_IRQ_STATUS	0xFFC00C68	// DMA2 Channel 1 Interrupt
-						// /Status Register
-#define DMA2_1_PERIPHERAL_MAP	0xFFC00C6C	// DMA2 Channel 1 Peripheral
-						// Map Register
-
-#define DMA2_2_CONFIG		0xFFC00C88	// DMA2 Channel 2 Configuration
-						// register
-#define DMA2_2_NEXT_DESC_PTR	0xFFC00C80	// DMA2 Channel 2 Next
-						// Descripter Ptr Reg
-#define DMA2_2_START_ADDR	0xFFC00C84	// DMA2 Channel 2 Start Address
-#define DMA2_2_X_COUNT		0xFFC00C90	// DMA2 Channel 2 Inner Loop
-						// Count
-#define DMA2_2_Y_COUNT		0xFFC00C98	// DMA2 Channel 2 Outer Loop
-						// Count
-#define DMA2_2_X_MODIFY		0xFFC00C94	// DMA2 Channel 2 Inner Loop
-						// Addr Increment
-#define DMA2_2_Y_MODIFY		0xFFC00C9C	// DMA2 Channel 2 Outer Loop
-						// Addr Increment
-#define DMA2_2_CURR_DESC_PTR	0xFFC00CA0	// DMA2 Channel 2 Current
-						// Descriptor Pointer
-#define DMA2_2_CURR_ADDR	0xFFC00CA4	// DMA2 Channel 2 Current
-						// Address Pointer
-#define DMA2_2_CURR_X_COUNT	0xFFC00CB0	// DMA2 Channel 2 Current Inner
-						// Loop Count
-#define DMA2_2_CURR_Y_COUNT	0xFFC00CB8	// DMA2 Channel 2 Current Outer
-						// Loop Count
-#define DMA2_2_IRQ_STATUS	0xFFC00CA8	// DMA2 Channel 2 Interrupt
-						// /Status Register
-#define DMA2_2_PERIPHERAL_MAP	0xFFC00CAC	// DMA2 Channel 2 Peripheral
-						// Map Register
-
-#define DMA2_3_CONFIG		0xFFC00CC8	// DMA2 Channel 3 Configuration
-						// register
-#define DMA2_3_NEXT_DESC_PTR	0xFFC00CC0	// DMA2 Channel 3 Next
-						// Descripter Ptr Reg
-#define DMA2_3_START_ADDR	0xFFC00CC4	// DMA2 Channel 3 Start Address
-#define DMA2_3_X_COUNT		0xFFC00CD0	// DMA2 Channel 3 Inner Loop
-						// Count
-#define DMA2_3_Y_COUNT		0xFFC00CD8	// DMA2 Channel 3 Outer Loop
-						// Count
-#define DMA2_3_X_MODIFY		0xFFC00CD4	// DMA2 Channel 3 Inner Loop
-						// Addr Increment
-#define DMA2_3_Y_MODIFY		0xFFC00CDC	// DMA2 Channel 3 Outer Loop
-						// Addr Increment
-#define DMA2_3_CURR_DESC_PTR	0xFFC00CE0	// DMA2 Channel 3 Current
-						// Descriptor Pointer
-#define DMA2_3_CURR_ADDR	0xFFC00CE4	// DMA2 Channel 3 Current
-						// Address Pointer
-#define DMA2_3_CURR_X_COUNT	0xFFC00CF0	// DMA2 Channel 3 Current Inner
-						// Loop Count
-#define DMA2_3_CURR_Y_COUNT	0xFFC00CF8	// DMA2 Channel 3 Current Outer
-						// Loop Count
-#define DMA2_3_IRQ_STATUS	0xFFC00CE8	// DMA2 Channel 3 Interrupt
-						// /Status Register
-#define DMA2_3_PERIPHERAL_MAP	0xFFC00CEC	// DMA2 Channel 3 Peripheral
-						// Map Register
-
-#define DMA2_4_CONFIG		0xFFC00D08	// DMA2 Channel 4 Configuration
-						// register
-#define DMA2_4_NEXT_DESC_PTR	0xFFC00D00	// DMA2 Channel 4 Next
-						// Descripter Ptr Reg
-#define DMA2_4_START_ADDR	0xFFC00D04	// DMA2 Channel 4 Start Address
-#define DMA2_4_X_COUNT		0xFFC00D10	// DMA2 Channel 4 Inner Loop
-						// Count
-#define DMA2_4_Y_COUNT		0xFFC00D18	// DMA2 Channel 4 Outer Loop
-						// Count
-#define DMA2_4_X_MODIFY		0xFFC00D14	// DMA2 Channel 4 Inner Loop
-						// Addr Increment
-#define DMA2_4_Y_MODIFY		0xFFC00D1C	// DMA2 Channel 4 Outer Loop
-						// Addr Increment
-#define DMA2_4_CURR_DESC_PTR	0xFFC00D20	// DMA2 Channel 4 Current
-						// Descriptor Pointer
-#define DMA2_4_CURR_ADDR	0xFFC00D24	// DMA2 Channel 4 Current
-						// Address Pointer
-#define DMA2_4_CURR_X_COUNT	0xFFC00D30	// DMA2 Channel 4 Current Inner
-						// Loop Count
-#define DMA2_4_CURR_Y_COUNT	0xFFC00D38	// DMA2 Channel 4 Current Outer
-						// Loop Count
-#define DMA2_4_IRQ_STATUS	0xFFC00D28	// DMA2 Channel 4 Interrupt
-						// /Status Register
-#define DMA2_4_PERIPHERAL_MAP	0xFFC00D2C	// DMA2 Channel 4 Peripheral
-						// Map Register
-
-#define DMA2_5_CONFIG		0xFFC00D48	// DMA2 Channel 5 Configuration
-						// register
-#define DMA2_5_NEXT_DESC_PTR	0xFFC00D40	// DMA2 Channel 5 Next
-						// Descripter Ptr Reg
-#define DMA2_5_START_ADDR	0xFFC00D44	// DMA2 Channel 5 Start Address
-#define DMA2_5_X_COUNT		0xFFC00D50	// DMA2 Channel 5 Inner Loop
-						// Count
-#define DMA2_5_Y_COUNT		0xFFC00D58	// DMA2 Channel 5 Outer Loop
-						// Count
-#define DMA2_5_X_MODIFY		0xFFC00D54	// DMA2 Channel 5 Inner Loop
-						// Addr Increment
-#define DMA2_5_Y_MODIFY		0xFFC00D5C	// DMA2 Channel 5 Outer Loop
-						// Addr Increment
-#define DMA2_5_CURR_DESC_PTR	0xFFC00D60	// DMA2 Channel 5 Current
-						// Descriptor Pointer
-#define DMA2_5_CURR_ADDR	0xFFC00D64	// DMA2 Channel 5 Current
-						// Address Pointer
-#define DMA2_5_CURR_X_COUNT	0xFFC00D70	// DMA2 Channel 5 Current Inner
-						// Loop Count
-#define DMA2_5_CURR_Y_COUNT	0xFFC00D78	// DMA2 Channel 5 Current Outer
-						// Loop Count
-#define DMA2_5_IRQ_STATUS	0xFFC00D68	// DMA2 Channel 5 Interrupt
-						// /Status Register
-#define DMA2_5_PERIPHERAL_MAP	0xFFC00D6C	// DMA2 Channel 5 Peripheral
-						// Map Register
-
-#define DMA2_6_CONFIG		0xFFC00D88	// DMA2 Channel 6 Configuration
-						// register
-#define DMA2_6_NEXT_DESC_PTR	0xFFC00D80	// DMA2 Channel 6 Next
-						// Descripter Ptr Reg
-#define DMA2_6_START_ADDR	0xFFC00D84	// DMA2 Channel 6 Start Address
-#define DMA2_6_X_COUNT		0xFFC00D90	// DMA2 Channel 6 Inner Loop
-						// Count
-#define DMA2_6_Y_COUNT		0xFFC00D98	// DMA2 Channel 6 Outer Loop
-						// Count
-#define DMA2_6_X_MODIFY		0xFFC00D94	// DMA2 Channel 6 Inner Loop
-						// Addr Increment
-#define DMA2_6_Y_MODIFY		0xFFC00D9C	// DMA2 Channel 6 Outer Loop
-						// Addr Increment
-#define DMA2_6_CURR_DESC_PTR	0xFFC00DA0	// DMA2 Channel 6 Current
-						// Descriptor Pointer
-#define DMA2_6_CURR_ADDR	0xFFC00DA4	// DMA2 Channel 6 Current
-						// Address Pointer
-#define DMA2_6_CURR_X_COUNT	0xFFC00DB0	// DMA2 Channel 6 Current Inner
-						// Loop Count
-#define DMA2_6_CURR_Y_COUNT	0xFFC00DB8	// DMA2 Channel 6 Current Outer
-						// Loop Count
-#define DMA2_6_IRQ_STATUS	0xFFC00DA8	// DMA2 Channel 6 Interrupt
-						// /Status Register
-#define DMA2_6_PERIPHERAL_MAP	0xFFC00DAC	// DMA2 Channel 6 Peripheral
-						// Map Register
-
-#define DMA2_7_CONFIG		0xFFC00DC8	// DMA2 Channel 7 Configuration
-						// register
-#define DMA2_7_NEXT_DESC_PTR	0xFFC00DC0	// DMA2 Channel 7 Next
-						// Descripter Ptr Reg
-#define DMA2_7_START_ADDR	0xFFC00DC4	// DMA2 Channel 7 Start Address
-#define DMA2_7_X_COUNT		0xFFC00DD0	// DMA2 Channel 7 Inner Loop
-						// Count
-#define DMA2_7_Y_COUNT		0xFFC00DD8	// DMA2 Channel 7 Outer Loop
-						// Count
-#define DMA2_7_X_MODIFY		0xFFC00DD4	// DMA2 Channel 7 Inner Loop
-						// Addr Increment
-#define DMA2_7_Y_MODIFY		0xFFC00DDC	// DMA2 Channel 7 Outer Loop
-						// Addr Increment
-#define DMA2_7_CURR_DESC_PTR	0xFFC00DE0	// DMA2 Channel 7 Current
-						// Descriptor Pointer
-#define DMA2_7_CURR_ADDR	0xFFC00DE4	// DMA2 Channel 7 Current
-						// Address Pointer
-#define DMA2_7_CURR_X_COUNT	0xFFC00DF0	// DMA2 Channel 7 Current Inner
-						// Loop Count
-#define DMA2_7_CURR_Y_COUNT	0xFFC00DF8	// DMA2 Channel 7 Current Outer
-						// Loop Count
-#define DMA2_7_IRQ_STATUS	0xFFC00DE8	// DMA2 Channel 7 Interrupt
-						// /Status Register
-#define DMA2_7_PERIPHERAL_MAP	0xFFC00DEC	// DMA2 Channel 7 Peripheral
-						// Map Register
-
-#define DMA2_8_CONFIG		0xFFC00E08	// DMA2 Channel 8 Configuration
-						// register
-#define DMA2_8_NEXT_DESC_PTR	0xFFC00E00	// DMA2 Channel 8 Next
-						// Descripter Ptr Reg
-#define DMA2_8_START_ADDR	0xFFC00E04	// DMA2 Channel 8 Start Address
-#define DMA2_8_X_COUNT		0xFFC00E10	// DMA2 Channel 8 Inner Loop
-						// Count
-#define DMA2_8_Y_COUNT		0xFFC00E18	// DMA2 Channel 8 Outer Loop
-						// Count
-#define DMA2_8_X_MODIFY		0xFFC00E14	// DMA2 Channel 8 Inner Loop
-						// Addr Increment
-#define DMA2_8_Y_MODIFY		0xFFC00E1C	// DMA2 Channel 8 Outer Loop
-						// Addr Increment
-#define DMA2_8_CURR_DESC_PTR	0xFFC00E20	// DMA2 Channel 8 Current
-						// Descriptor Pointer
-#define DMA2_8_CURR_ADDR	0xFFC00E24	// DMA2 Channel 8 Current
-						// Address Pointer
-#define DMA2_8_CURR_X_COUNT	0xFFC00E30	// DMA2 Channel 8 Current Inner
-						// Loop Count
-#define DMA2_8_CURR_Y_COUNT	0xFFC00E38	// DMA2 Channel 8 Current Outer
-						// Loop Count
-#define DMA2_8_IRQ_STATUS	0xFFC00E28	// DMA2 Channel 8 Interrupt
-						// /Status Register
-#define DMA2_8_PERIPHERAL_MAP	0xFFC00E2C	// DMA2 Channel 8 Peripheral
-						// Map Register
-
-#define DMA2_9_CONFIG		0xFFC00E48	// DMA2 Channel 9 Configuration
-						// register
-#define DMA2_9_NEXT_DESC_PTR	0xFFC00E40	// DMA2 Channel 9 Next
-						// Descripter Ptr Reg
-#define DMA2_9_START_ADDR	0xFFC00E44	// DMA2 Channel 9 Start Address
-#define DMA2_9_X_COUNT		0xFFC00E50	// DMA2 Channel 9 Inner Loop
-						// Count
-#define DMA2_9_Y_COUNT		0xFFC00E58	// DMA2 Channel 9 Outer Loop
-						// Count
-#define DMA2_9_X_MODIFY		0xFFC00E54	// DMA2 Channel 9 Inner Loop
-						// Addr Increment
-#define DMA2_9_Y_MODIFY		0xFFC00E5C	// DMA2 Channel 9 Outer Loop
-						// Addr Increment
-#define DMA2_9_CURR_DESC_PTR	0xFFC00E60	// DMA2 Channel 9 Current
-						// Descriptor Pointer
-#define DMA2_9_CURR_ADDR	0xFFC00E64	// DMA2 Channel 9 Current
-						// Address Pointer
-#define DMA2_9_CURR_X_COUNT	0xFFC00E70	// DMA2 Channel 9 Current Inner
-						// Loop Count
-#define DMA2_9_CURR_Y_COUNT	0xFFC00E78	// DMA2 Channel 9 Current Outer
-						// Loop Count
-#define DMA2_9_IRQ_STATUS	0xFFC00E68	// DMA2 Channel 9 Interrupt
-						// /Status Register
-#define DMA2_9_PERIPHERAL_MAP	0xFFC00E6C	// DMA2 Channel 9 Peripheral
-						// Map Register
-
-#define DMA2_10_CONFIG		0xFFC00E88	// DMA2 Channel 10 Configuration
-						// register
-#define DMA2_10_NEXT_DESC_PTR	0xFFC00E80	// DMA2 Channel 10 Next
-						// Descripter Ptr Reg
-#define DMA2_10_START_ADDR	0xFFC00E84	// DMA2 Channel 10 Start Address
-#define DMA2_10_X_COUNT		0xFFC00E90	// DMA2 Channel 10 Inner Loop
-						// Count
-#define DMA2_10_Y_COUNT		0xFFC00E98	// DMA2 Channel 10 Outer Loop
-						// Count
-#define DMA2_10_X_MODIFY	0xFFC00E94	// DMA2 Channel 10 Inner Loop
-						// Addr Increment
-#define DMA2_10_Y_MODIFY	0xFFC00E9C	// DMA2 Channel 10 Outer Loop
-						// Addr Increment
-#define DMA2_10_CURR_DESC_PTR	0xFFC00EA0	// DMA2 Channel 10 Current
-						// Descriptor Pointer
-#define DMA2_10_CURR_ADDR	0xFFC00EA4	// DMA2 Channel 10 Current
-						// Address Pointer
-#define DMA2_10_CURR_X_COUNT	0xFFC00EB0	// DMA2 Channel 10 Current Inner
-						// Loop Count
-#define DMA2_10_CURR_Y_COUNT	0xFFC00EB8	// DMA2 Channel 10 Current Outer
-						// Loop Count
-#define DMA2_10_IRQ_STATUS	0xFFC00EA8	// DMA2 Channel 10 Interrupt
-						// /Status Register
-#define DMA2_10_PERIPHERAL_MAP	0xFFC00EAC	// DMA2 Channel 10 Peripheral
-						// Map Register
-
-#define DMA2_11_CONFIG		0xFFC00EC8	// DMA2 Channel 11 Configuration
-						// register
-#define DMA2_11_NEXT_DESC_PTR	0xFFC00EC0	// DMA2 Channel 11 Next
-						// Descripter Ptr Reg
-#define DMA2_11_START_ADDR	0xFFC00EC4	// DMA2 Channel 11 Start Address
-#define DMA2_11_X_COUNT		0xFFC00ED0	// DMA2 Channel 11 Inner Loop
-						// Count
-#define DMA2_11_Y_COUNT		0xFFC00ED8	// DMA2 Channel 11 Outer Loop
-						// Count
-#define DMA2_11_X_MODIFY	0xFFC00ED4	// DMA2 Channel 11 Inner Loop
-						// Addr Increment
-#define DMA2_11_Y_MODIFY	0xFFC00EDC	// DMA2 Channel 11 Outer Loop
-						// Addr Increment
-#define DMA2_11_CURR_DESC_PTR	0xFFC00EE0	// DMA2 Channel 11 Current
-						// Descriptor Pointer
-#define DMA2_11_CURR_ADDR	0xFFC00EE4	// DMA2 Channel 11 Current
-						// Address Pointer
-#define DMA2_11_CURR_X_COUNT	0xFFC00EF0	// DMA2 Channel 11 Current Inner
-						// Loop Count
-#define DMA2_11_CURR_Y_COUNT	0xFFC00EF8	// DMA2 Channel 11 Current Outer
-						// Loop Count
-#define DMA2_11_IRQ_STATUS	0xFFC00EE8	// DMA2 Channel 11 Interrupt
-						// /Status Register
-#define DMA2_11_PERIPHERAL_MAP	0xFFC00EEC	// DMA2 Channel 11 Peripheral
-						// Map Register
-
-// Memory DMA2 Controller registers (0xFFC0 0E80-0xFFC0 0FFF)
-#define MDMA2_D0_CONFIG		0xFFC00F08	// MemDMA2 Stream 0 Destination
-						// Configuration register
-#define MDMA2_D0_NEXT_DESC_PTR	0xFFC00F00	// MemDMA2 Stream 0
-						// Destination Next
-						// Descriptor Ptr Reg
-#define MDMA2_D0_START_ADDR	0xFFC00F04	// MemDMA2 Stream 0 Destination
-						// Start Address
-#define MDMA2_D0_X_COUNT	0xFFC00F10	// MemDMA2 Stream 0 Dest
-						// Inner-Loop Count register
-#define MDMA2_D0_Y_COUNT	0xFFC00F18	// MemDMA2 Stream 0 Dest
-						// Outer-Loop Count register
-#define MDMA2_D0_X_MODIFY	0xFFC00F14	// MemDMA2 Stream 0 Dest
-						// Inner-Loop Address-Increment
-#define MDMA2_D0_Y_MODIFY	0xFFC00F1C	// MemDMA2 Stream 0 Dest
-						// Outer-Loop Address-Increment
-#define MDMA2_D0_CURR_DESC_PTR	0xFFC00F20	// MemDMA2 Stream 0 Dest
-						// Current Descriptor Ptr reg
-#define MDMA2_D0_CURR_ADDR	0xFFC00F24	// MemDMA2 Stream 0 Destination
-						// Current Address
-#define MDMA2_D0_CURR_X_COUNT	0xFFC00F30	// MemDMA2 Stream 0 Dest
-						// Current Inner-Loop Count reg
-#define MDMA2_D0_CURR_Y_COUNT	0xFFC00F38	// MemDMA2 Stream 0 Dest
-						// Current Outer-Loop Count reg
-#define MDMA2_D0_IRQ_STATUS	0xFFC00F28	// MemDMA2 Stream 0 Dest
-						// Interrupt/Status Register
-#define MDMA2_D0_PERIPHERAL_MAP 0xFFC00F2C	// MemDMA2 Stream 0
-						// Destination Peripheral Map
-						// register
-
-#define MDMA2_S0_CONFIG		0xFFC00F48	// MemDMA2 Stream 0 Source
-						// Configuration register
-#define MDMA2_S0_NEXT_DESC_PTR	0xFFC00F40	// MemDMA2 Stream 0 Source
-						// Next Descriptor Ptr Reg
-#define MDMA2_S0_START_ADDR	0xFFC00F44	// MemDMA2 Stream 0 Source
-						// Start Address
-#define MDMA2_S0_X_COUNT	0xFFC00F50	// MemDMA2 Stream 0 Source
-						// Inner-Loop Count register
-#define MDMA2_S0_Y_COUNT	0xFFC00F58	// MemDMA2 Stream 0 Source
-						// Outer-Loop Count register
-#define MDMA2_S0_X_MODIFY	0xFFC00F54	// MemDMA2 Stream 0 Src
-						// Inner-Loop Addr-Increment reg
-#define MDMA2_S0_Y_MODIFY	0xFFC00F5C	// MemDMA2 Stream 0 Src
-						// Outer-Loop Addr-Increment reg
-#define MDMA2_S0_CURR_DESC_PTR	0xFFC00F60	// MemDMA2 Stream 0 Source
-						// Current Descriptor Ptr reg
-#define MDMA2_S0_CURR_ADDR	0xFFC00F64	// MemDMA2 Stream 0 Source
-						// Current Address
-#define MDMA2_S0_CURR_X_COUNT	0xFFC00F70	// MemDMA2 Stream 0 Src
-						// Current Inner-Loop Count reg
-#define MDMA2_S0_CURR_Y_COUNT	0xFFC00F78	// MemDMA2 Stream 0 Src
-						// Current Outer-Loop Count reg
-#define MDMA2_S0_IRQ_STATUS	0xFFC00F68	// MemDMA2 Stream 0 Source
-						// Interrupt/Status Register
-#define MDMA2_S0_PERIPHERAL_MAP	0xFFC00F6C	// MemDMA2 Stream 0 Source
-						// Peripheral Map register
-
-#define MDMA2_D1_CONFIG		0xFFC00F88	// MemDMA2 Stream 1 Destination
-						// Configuration register
-#define MDMA2_D1_NEXT_DESC_PTR	0xFFC00F80	// MemDMA2 Stream 1
-						// Destination Next
-						// Descriptor Ptr Reg
-#define MDMA2_D1_START_ADDR	0xFFC00F84	// MemDMA2 Stream 1 Destination
-						// Start Address
-#define MDMA2_D1_X_COUNT	0xFFC00F90	// MemDMA2 Stream 1 Dest
-						// Inner-Loop Count register
-#define MDMA2_D1_Y_COUNT	0xFFC00F98	// MemDMA2 Stream 1 Dest
-						// Outer-Loop Count register
-#define MDMA2_D1_X_MODIFY	0xFFC00F94	// MemDMA2 Stream 1 Dest
-						// Inner-Loop Address-Increment
-#define MDMA2_D1_Y_MODIFY	0xFFC00F9C	// MemDMA2 Stream 1 Dest
-						// Outer-Loop Address-Increment
-#define MDMA2_D1_CURR_DESC_PTR	0xFFC00FA0	// MemDMA2 Stream 1
-						// Destination Current
-						// Descriptor Ptr
-#define MDMA2_D1_CURR_ADDR	0xFFC00FA4	// MemDMA2 Stream 1 Destination
-						// Current Address reg
-#define MDMA2_D1_CURR_X_COUNT	0xFFC00FB0	// MemDMA2 Stream 1 Dest
-						// Current Inner-Loop Count reg
-#define MDMA2_D1_CURR_Y_COUNT	0xFFC00FB8	// MemDMA2 Stream 1 Dest
-						// Current Outer-Loop Count reg
-#define MDMA2_D1_IRQ_STATUS	0xFFC00FA8	// MemDMA2 Stream 1 Destination
-						// Interrupt/Status Reg
-#define MDMA2_D1_PERIPHERAL_MAP 0xFFC00FAC	// MemDMA2 Stream 1
-						// Destination Peripheral Map
-						// register
-
-#define MDMA2_S1_CONFIG		0xFFC00FC8	// MemDMA2 Stream 1 Source
-						// Configuration register
-#define MDMA2_S1_NEXT_DESC_PTR	0xFFC00FC0	// MemDMA2 Stream 1 Source
-						// Next Descriptor Ptr Reg
-#define MDMA2_S1_START_ADDR	0xFFC00FC4	// MemDMA2 Stream 1 Source
-						// Start Address
-#define MDMA2_S1_X_COUNT	0xFFC00FD0	// MemDMA2 Stream 1 Source
-						// Inner-Loop Count register
-#define MDMA2_S1_Y_COUNT	0xFFC00FD8	// MemDMA2 Stream 1 Source
-						// Outer-Loop Count register
-#define MDMA2_S1_X_MODIFY	0xFFC00FD4	// MemDMA2 Stream 1 Src
-						// Inner-Loop Address-Increment
-#define MDMA2_S1_Y_MODIFY	0xFFC00FDC	// MemDMA2 Stream 1 Source
-						// Outer-Loop Address-Increment
-#define MDMA2_S1_CURR_DESC_PTR	0xFFC00FE0	// MemDMA2 Stream 1 Source
-						// Current Descriptor Ptr reg
-#define MDMA2_S1_CURR_ADDR	0xFFC00FE4	// MemDMA2 Stream 1 Source
-						// Current Address
-#define MDMA2_S1_CURR_X_COUNT	0xFFC00FF0	// MemDMA2 Stream 1 Source
-						// Current Inner-Loop Count
-#define MDMA2_S1_CURR_Y_COUNT	0xFFC00FF8	// MemDMA2 Stream 1 Source
-						// Current Outer-Loop Count
-#define MDMA2_S1_IRQ_STATUS	0xFFC00FE8	// MemDMA2 Stream 1 Source
-						// Interrupt/Status Register
-#define MDMA2_S1_PERIPHERAL_MAP	0xFFC00FEC	// MemDMA2 Stream 1 Source
-						// Peripheral Map register
-
-// Internal Memory DMA Registers (0xFFC0_1800 - 0xFFC0_19FF)
-#define IMDMA_D0_CONFIG		0xFFC01808	// IMDMA Stream 0 Destination
-						// Configuration
-#define IMDMA_D0_NEXT_DESC_PTR	0xFFC01800	// IMDMA Stream 0 Destination
-						// Next Descriptor Ptr Reg
-#define IMDMA_D0_START_ADDR	0xFFC01804	// IMDMA Stream 0 Destination
-						// Start Address
-#define IMDMA_D0_X_COUNT	0xFFC01810	// IMDMA Stream 0 Destination
-						// Inner-Loop Count
-#define IMDMA_D0_Y_COUNT	0xFFC01818	// IMDMA Stream 0 Destination
-						// Outer-Loop Count
-#define IMDMA_D0_X_MODIFY	0xFFC01814	// IMDMA Stream 0 Dest
-						// Inner-Loop Address-Increment
-#define IMDMA_D0_Y_MODIFY	0xFFC0181C	// IMDMA Stream 0 Dest
-						// Outer-Loop Address-Increment
-#define IMDMA_D0_CURR_DESC_PTR	0xFFC01820	// IMDMA Stream 0 Destination
-						// Current Descriptor Ptr
-#define IMDMA_D0_CURR_ADDR	0xFFC01824	// IMDMA Stream 0 Destination
-						// Current Address
-#define IMDMA_D0_CURR_X_COUNT	0xFFC01830	// IMDMA Stream 0 Destination
-						// Current Inner-Loop Count
-#define IMDMA_D0_CURR_Y_COUNT	0xFFC01838	// IMDMA Stream 0 Destination
-						// Current Outer-Loop Count
-#define IMDMA_D0_IRQ_STATUS	0xFFC01828	// IMDMA Stream 0 Destination
-						// Interrupt/Status
-
-#define IMDMA_S0_CONFIG		0xFFC01848	// IMDMA Stream 0 Source
-						// Configuration
-#define IMDMA_S0_NEXT_DESC_PTR	0xFFC01840	// IMDMA Stream 0 Source Next
-						// Descriptor Ptr Reg
-#define IMDMA_S0_START_ADDR	0xFFC01844	// IMDMA Stream 0 Source Start
-						// Address
-#define IMDMA_S0_X_COUNT	0xFFC01850	// IMDMA Stream 0 Source
-						// Inner-Loop Count
-#define IMDMA_S0_Y_COUNT	0xFFC01858	// IMDMA Stream 0 Source
-						// Outer-Loop Count
-#define IMDMA_S0_X_MODIFY	0xFFC01854	// IMDMA Stream 0 Source
-						// Inner-Loop Address-Increment
-#define IMDMA_S0_Y_MODIFY	0xFFC0185C	// IMDMA Stream 0 Source
-						// Outer-Loop Address-Increment
-#define IMDMA_S0_CURR_DESC_PTR	0xFFC01860	// IMDMA Stream 0 Source
-						// Current Descriptor Ptr reg
-#define IMDMA_S0_CURR_ADDR	0xFFC01864	// IMDMA Stream 0 Source Current
-						// Address
-#define IMDMA_S0_CURR_X_COUNT	0xFFC01870	// IMDMA Stream 0 Source
-						// Current Inner-Loop Count
-#define IMDMA_S0_CURR_Y_COUNT	0xFFC01878	// IMDMA Stream 0 Source
-						// Current Outer-Loop Count
-#define IMDMA_S0_IRQ_STATUS	0xFFC01868	// IMDMA Stream 0 Source
-						// Interrupt/Status
-
-#define IMDMA_D1_CONFIG		0xFFC01888	// IMDMA Stream 1 Destination
-						// Configuration
-#define IMDMA_D1_NEXT_DESC_PTR	0xFFC01880	// IMDMA Stream 1 Destination
-						// Next Descriptor Ptr Reg
-#define IMDMA_D1_START_ADDR	0xFFC01884	// IMDMA Stream 1 Destination
-						// Start Address
-#define IMDMA_D1_X_COUNT	0xFFC01890	// IMDMA Stream 1 Destination
-						// Inner-Loop Count
-#define IMDMA_D1_Y_COUNT	0xFFC01898	// IMDMA Stream 1 Destination
-						// Outer-Loop Count
-#define IMDMA_D1_X_MODIFY	0xFFC01894	// IMDMA Stream 1 Dest
-						// Inner-Loop Address-Increment
-#define IMDMA_D1_Y_MODIFY	0xFFC0189C	// IMDMA Stream 1 Dest
-						// Outer-Loop Address-Increment
-#define IMDMA_D1_CURR_DESC_PTR	0xFFC018A0	// IMDMA Stream 1 Destination
-						// Current Descriptor Ptr
-#define IMDMA_D1_CURR_ADDR	0xFFC018A4	// IMDMA Stream 1 Destination
-						// Current Address
-#define IMDMA_D1_CURR_X_COUNT	0xFFC018B0	// IMDMA Stream 1 Destination
-						// Current Inner-Loop Count
-#define IMDMA_D1_CURR_Y_COUNT	0xFFC018B8	// IMDMA Stream 1 Destination
-						// Current Outer-Loop Count
-#define IMDMA_D1_IRQ_STATUS	0xFFC018A8	// IMDMA Stream 1 Destination
-						// Interrupt/Status
-
-#define IMDMA_S1_CONFIG		0xFFC018C8	// IMDMA Stream 1 Source
-						// Configuration
-#define IMDMA_S1_NEXT_DESC_PTR	0xFFC018C0	// IMDMA Stream 1 Source Next
-						// Descriptor Ptr Reg
-#define IMDMA_S1_START_ADDR	0xFFC018C4	// IMDMA Stream 1 Source Start
-						// Address
-#define IMDMA_S1_X_COUNT	0xFFC018D0	// IMDMA Stream 1 Source
-						// Inner-Loop Count
-#define IMDMA_S1_Y_COUNT	0xFFC018D8	// IMDMA Stream 1 Source
-						// Outer-Loop Count
-#define IMDMA_S1_X_MODIFY	0xFFC018D4	// IMDMA Stream 1 Source
-						// Inner-Loop Address-Increment
-#define IMDMA_S1_Y_MODIFY	0xFFC018DC	// IMDMA Stream 1 Source
-						// Outer-Loop Address-Increment
-#define IMDMA_S1_CURR_DESC_PTR	0xFFC018E0	// IMDMA Stream 1 Source
-						// Current Descriptor Ptr reg
-#define IMDMA_S1_CURR_ADDR	0xFFC018E4	// IMDMA Stream 1 Source Current
-						// Address
-#define IMDMA_S1_CURR_X_COUNT	0xFFC018F0	// IMDMA Stream 1 Source
-						// Current Inner-Loop Count
-#define IMDMA_S1_CURR_Y_COUNT	0xFFC018F8	// IMDMA Stream 1 Source
-						// Current Outer-Loop Count
-#define IMDMA_S1_IRQ_STATUS	0xFFC018E8	// IMDMA Stream 1 Source
-						// Interrupt/Status
-
-//****************************************************************************
-// System MMR Register Bits
-//****************************************************************************
-
-// ********************* PLL AND RESET MASKS ************************
-
-//// PLL_CTL Masks
-#define PLL_CLKIN              0x00000000	// Pass CLKIN to PLL
-#define PLL_CLKIN_DIV2         0x00000001	// Pass CLKIN/2 to PLL
-#define PLL_OFF                0x00000002	// Shut off PLL clocks
-#define STOPCK_OFF             0x00000008	// Core clock off
-#define PDWN                   0x00000020	// Put the PLL in a Deep
-						// Sleep state
-#define BYPASS                 0x00000100	// Bypass the PLL
-
-//// PLL_DIV Masks
-
-#define SCLK_DIV(x)  (x)	// SCLK = VCO / x
-
-#define CCLK_DIV1              0x00000000	// CCLK = VCO / 1
-#define CCLK_DIV2              0x00000010	// CCLK = VCO / 2
-#define CCLK_DIV4              0x00000020	// CCLK = VCO / 4
-#define CCLK_DIV8              0x00000030	// CCLK = VCO / 8
-
-// SWRST Mask
-#define SYSTEM_RESET           0x00000007	// Initiates a system
-						// software reset
-#define SWRST_DBL_FAULT_B      0x00000800	// SWRST Core B Double Fault
-#define SWRST_DBL_FAULT_A      0x00001000	// SWRST Core A Double Fault
-#define SWRST_WDT_B	       0x00002000	// SWRST Watchdog B
-#define SWRST_WDT_A	       0x00004000	// SWRST Watchdog A
-#define SWRST_OCCURRED         0x00008000	// SWRST Status
-
-// *************  SYSTEM INTERRUPT CONTROLLER MASKS *****************
-
-// SICu_IARv Masks
-// u = A or B
-// v = 0 to 7
-// w = 0 or 1
-
-// Per_number = 0 to 63
-// IVG_number = 7 to 15
-// Peripheral #Per_number assigned IVG #IVG_number
-// Usage:
-//	r0.l = lo(Peripheral_IVG(62, 10));
-//	r0.h = hi(Peripheral_IVG(62, 10));
-#define Peripheral_IVG(Per_number, IVG_number)    \
-				( (IVG_number) -7) << ( ((Per_number)%8) *4)
-
-// SICx_IMASKw Masks
-// masks are 32 bit wide, so two writes reguired for "64 bit" wide registers
-#define SIC_UNMASK_ALL         0x00000000	// Unmask all peripheral
-						// interrupts
-#define SIC_MASK_ALL           0xFFFFFFFF	// Mask all peripheral
-						// interrupts
-#define SIC_MASK(x)	       (1 << (x))	// Mask Peripheral #x
-						// interrupt
-#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << (x)))	// Unmask Peripheral #x
-						// interrupt
-
-// SIC_IWR Masks
-#define IWR_DISABLE_ALL		0x00000000	// Wakeup Disable all
-						// peripherals
-#define IWR_ENABLE_ALL		0xFFFFFFFF	// Wakeup Enable all
-						// peripherals
-// x = pos 0 to 31, for 32-63 use value-32
-#define IWR_ENABLE(x)		(1 << (x))	// Wakeup Enable Peripheral
-						// #x
-// Wakeup Disable Peripheral #x
-#define IWR_DISABLE(x)		(0xFFFFFFFF ^ (1 << (x)))
-
-// *********  WATCHDOG TIMER MASKS  ********************8
-
-// Watchdog Timer WDOG_CTL Register
-#define	WDOGA_CTL		0xFFC00200
-#define	WDOGA_CNT		0xFFC00204
-#define	WDOGA_STAT		0xFFC00208
-#define	WDOGB_CTL		0xFFC01200
-#define	WDOGB_CNT		0xFFC01204
-#define	WDOGB_STAT		0xFFC01208
-#define ICTL(x)			((x<<1) & 0x0006)
-#define ENABLE_RESET		0x00000000	// Set Watchdog Timer to
-						// generate reset
-#define ENABLE_NMI		0x00000002	// Set Watchdog Timer to
-						// generate non-maskable
-						// interrupt
-#define ENABLE_GPI		0x00000004	// Set Watchdog Timer to
-						// generate general-purpose
-						// interrupt
-#define DISABLE_EVT		0x00000006	// Disable Watchdog Timer
-						// interrupts
-
-#define TMR_EN			0x0000
-#define TMR_DIS			0x0AD0
-#define TRO			0x8000
-
-#define ICTL_P0			0x01
-#define ICTL_P1			0x02
-#define TRO_P			0x0F
-
-// ***************************** UART CONTROLLER MASKS **********************
-
-// UART_LCR Register
-
-#define DLAB			0x80
-#define SB			0x40
-#define STP			0x20
-#define EPS			0x10
-#define PEN			0x08
-#define STB			0x04
-#define WLS(x)			((x-5) & 0x03)
-
-#define DLAB_P			0x07
-#define SB_P			0x06
-#define STP_P			0x05
-#define EPS_P			0x04
-#define PEN_P			0x03
-#define STB_P			0x02
-#define WLS_P1			0x01
-#define WLS_P0			0x00
-
-// UART_MCR Register
-#define LOOP_ENA		0x10
-#define LOOP_ENA_P		0x04
-
-// UART_LSR Register
-#define TEMT			0x40
-#define THRE			0x20
-#define BI			0x10
-#define FE			0x08
-#define PE			0x04
-#define OE			0x02
-#define DR			0x01
-
-#define TEMP_P			0x06
-#define THRE_P			0x05
-#define BI_P			0x04
-#define FE_P			0x03
-#define PE_P			0x02
-#define OE_P			0x01
-#define DR_P			0x00
-
-// UART_IER Register
-#define ELSI			0x04
-#define ETBEI			0x02
-#define ERBFI			0x01
-
-#define ELSI_P			0x02
-#define ETBEI_P			0x01
-#define ERBFI_P			0x00
-
-// UART_IIR Register
-#define STATUS(x)		((x << 1) & 0x06)
-#define NINT			0x01
-#define STATUS_P1		0x02
-#define STATUS_P0		0x01
-#define NINT_P			0x00
-
-// UART_GCTL Register
-#define FFE			0x20
-#define FPE			0x10
-#define RPOLC			0x08
-#define TPOLC			0x04
-#define IREN			0x02
-#define UCEN			0x01
-
-#define FFE_P			0x05
-#define FPE_P			0x04
-#define RPOLC_P			0x03
-#define TPOLC_P			0x02
-#define IREN_P			0x01
-#define UCEN_P			0x00
-
-// **********  SERIAL PORT MASKS  **********************
-
-// SPORTx_TCR1 Masks
-#define TSPEN			0x0001		// TX enable
-#define ITCLK			0x0002		// Internal TX Clock Select
-#define TDTYPE			0x000C		// TX Data Formatting Select
-#define TLSBIT			0x0010		// TX Bit Order
-#define ITFS			0x0200		// Internal TX Frame Sync Select
-#define TFSR			0x0400		// TX Frame Sync Required Select
-#define DITFS			0x0800		// Data Independent TX Frame Sync Select
-#define LTFS			0x1000		// Low TX Frame Sync Select
-#define LATFS			0x2000		// Late TX Frame Sync Select
-#define TCKFE			0x4000		// TX Clock Falling Edge Select
-
-// SPORTx_TCR2 Masks
-#define SLEN			0x001F	// TX Word Length
-#define TXSE			0x0100	// TX Secondary Enable
-#define TSFSE			0x0200	// TX Stereo Frame Sync Enable
-#define TRFST			0x0400	// TX Right-First Data Order
-
-// SPORTx_RCR1 Masks
-#define RSPEN			0x0001		// RX enable
-#define IRCLK			0x0002		// Internal RX Clock Select
-#define RDTYPE			0x000C		// RX Data Formatting Select
-#define RULAW			0x0008		// u-Law enable
-#define RALAW			0x000C		// A-Law enable
-#define RLSBIT			0x0010		// RX Bit Order
-#define IRFS			0x0200		// Internal RX Frame Sync Select
-#define RFSR			0x0400		// RX Frame Sync Required Select
-#define LRFS			0x1000		// Low RX Frame Sync Select
-#define LARFS			0x2000		// Late RX Frame Sync Select
-#define RCKFE			0x4000		// RX Clock Falling Edge Select
-
-// SPORTx_RCR2 Masks
-#define SLEN			0x001F	// RX Word Length
-#define RXSE			0x0100	// RX Secondary Enable
-#define RSFSE			0x0200	// RX Stereo Frame Sync Enable
-#define RRFST			0x0400	// Right-First Data Order
-
-//SPORTx_STAT Masks
-#define RXNE			0x0001	// RX FIFO Not Empty Status
-#define RUVF			0x0002	// RX Underflow Status
-#define ROVF			0x0004	// RX Overflow Status
-#define TXF			0x0008	// TX FIFO Full Status
-#define TUVF			0x0010	// TX Underflow Status
-#define TOVF			0x0020	// TX Overflow Status
-#define TXHRE			0x0040	// TX Hold Register Empty
-
-//SPORTx_MCMC1 Masks
-#define WSIZE			0x0000F000	// Multichannel Window Size Field
-#define WOFF			0x000003FF	// Multichannel Window Offset Field
-
-//SPORTx_MCMC2 Masks
-#define MCCRM			0x00000003	// Multichannel Clock Recovery Mode
-#define MCDTXPE			0x00000004	// Multichannel DMA Transmit Packing
-#define MCDRXPE			0x00000008	// Multichannel DMA Receive Packing
-#define MCMEN			0x00000010	// Multichannel Frame Mode Enable
-#define FSDR			0x00000080	// Multichannel Frame Sync to Data
-					// Relationship
-#define MFD			0x0000F000	// Multichannel Frame Delay
-
-//  *********  PARALLEL PERIPHERAL INTERFACE (PPI) MASKS ****************
-
-////  PPI_CONTROL Masks
-#define PORT_EN			0x00000001	// PPI Port Enable
-#define PORT_DIR		0x00000002	// PPI Port Direction
-#define XFR_TYPE		0x0000000C	// PPI Transfer Type
-#define PORT_CFG		0x00000030	// PPI Port Configuration
-#define FLD_SEL			0x00000040	// PPI Active Field Select
-#define PACK_EN			0x00000080	// PPI Packing Mode
-#define DMA32			0x00000100	// PPI 32-bit DMA Enable
-#define SKIP_EN			0x00000200	// PPI Skip Element Enable
-#define SKIP_EO			0x00000400	// PPI Skip Even/Odd Elements
-#define DLENGTH			0x00003800	// PPI Data Length
-#define DLEN_8			0x0	// PPI Data Length mask for DLEN=8
-#define DLEN(x)			(((x-9) & 0x07) << 11)	// PPI Data Length (only works for
-					// x=10-->x=16)
-#define POL			0x0000C000	// PPI Signal Polarities
-
-//// PPI_STATUS Masks
-#define FLD			0x00000400	// Field Indicator
-#define FT_ERR			0x00000800	// Frame Track Error
-#define OVR			0x00001000	// FIFO Overflow Error
-#define UNDR			0x00002000	// FIFO Underrun Error
-#define ERR_DET			0x00004000	// Error Detected Indicator
-#define ERR_NCOR		0x00008000	// Error Not Corrected Indicator
-
-// **********  DMA CONTROLLER MASKS  *********************8
-
-// DMAx_CONFIG, MDMA_yy_CONFIG, IMDMA_yy_CONFIG Masks
-#define DMAEN			0x00000001	// Channel Enable
-#define WNR			0x00000002	// Channel Direction (W/R*)
-#define WDSIZE_8		0x00000000	// Word Size 8 bits
-#define WDSIZE_16		0x00000004	// Word Size 16 bits
-#define WDSIZE_32		0x00000008	// Word Size 32 bits
-#define DMA2D			0x00000010	// 2D/1D* Mode
-#define RESTART			0x00000020	// Restart
-#define DI_SEL			0x00000040	// Data Interrupt Select
-#define DI_EN			0x00000080	// Data Interrupt Enable
-#define NDSIZE			0x00000900	// Next Descriptor Size
-#define FLOW			0x00007000	// Flow Control
-
-#define DMAEN_P	            	0	// Channel Enable
-#define WNR_P	            	1	// Channel Direction (W/R*)
-#define DMA2D_P	        	4	// 2D/1D* Mode
-#define RESTART_P	      	5	// Restart
-#define DI_SEL_P	     	6	// Data Interrupt Select
-#define DI_EN_P	            	7	// Data Interrupt Enable
-
-////DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS, IMDMA_yy_IRQ_STATUS Masks
-
-#define DMA_DONE		0x00000001	// DMA Done Indicator
-#define DMA_ERR	        	0x00000002	// DMA Error Indicator
-#define DFETCH	            	0x00000004	// Descriptor Fetch Indicator
-#define DMA_RUN	            	0x00000008	// DMA Running Indicator
-
-#define DMA_DONE_P	    	0	// DMA Done Indicator
-#define DMA_ERR_P     		1	// DMA Error Indicator
-#define DFETCH_P     		2	// Descriptor Fetch Indicator
-#define DMA_RUN_P     		3	// DMA Running Indicator
-
-////DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP, IMDMA_yy_PERIPHERAL_MAP Masks
-
-#define CTYPE			0x00000040	// DMA Channel Type Indicator
-#define CTYPE_P			6	// DMA Channel Type Indicator BIT POSITION
-#define PCAP8			0x00000080	// DMA 8-bit Operation Indicator
-#define PCAP16			0x00000100	// DMA 16-bit Operation Indicator
-#define PCAP32			0x00000200	// DMA 32-bit Operation Indicator
-#define PCAPWR			0x00000400	// DMA Write Operation Indicator
-#define PCAPRD			0x00000800	// DMA Read Operation Indicator
-#define PMAP			0x00007000	// DMA Peripheral Map Field
-
-//  *************  GENERAL PURPOSE TIMER MASKS  ********************
-
-/* PWM Timer bit definitions */
-
-// TIMER_ENABLE Register
-#define TIMEN0			0x0001
-#define TIMEN1			0x0002
-#define TIMEN2			0x0004
-#define TIMEN3			0x0008
-#define TIMEN4			0x0010
-#define TIMEN5			0x0020
-#define TIMEN6			0x0040
-#define TIMEN7			0x0080
-#define TIMEN8			0x0001
-#define TIMEN9			0x0002
-#define TIMEN10			0x0004
-#define TIMEN11			0x0008
-
-#define TIMEN0_P		0x00
-#define TIMEN1_P		0x01
-#define TIMEN2_P		0x02
-#define TIMEN3_P		0x03
-#define TIMEN4_P		0x04
-#define TIMEN5_P		0x05
-#define TIMEN6_P		0x06
-#define TIMEN7_P		0x07
-#define TIMEN8_P		0x00
-#define TIMEN9_P		0x01
-#define TIMEN10_P		0x02
-#define TIMEN11_P		0x03
-
-// TIMER_DISABLE Register
-#define TIMDIS0			0x0001
-#define TIMDIS1			0x0002
-#define TIMDIS2			0x0004
-#define TIMDIS3			0x0008
-#define TIMDIS4			0x0010
-#define TIMDIS5			0x0020
-#define TIMDIS6			0x0040
-#define TIMDIS7			0x0080
-#define TIMDIS8			0x0001
-#define TIMDIS9			0x0002
-#define TIMDIS10		0x0004
-#define TIMDIS11		0x0008
-
-#define TIMDIS0_P		0x00
-#define TIMDIS1_P		0x01
-#define TIMDIS2_P		0x02
-#define TIMDIS3_P		0x03
-#define TIMDIS4_P		0x04
-#define TIMDIS5_P		0x05
-#define TIMDIS6_P		0x06
-#define TIMDIS7_P		0x07
-#define TIMDIS8_P		0x00
-#define TIMDIS9_P		0x01
-#define TIMDIS10_P		0x02
-#define TIMDIS11_P		0x03
-
-// TIMER_STATUS Register
-#define TIMIL0			0x00000001
-#define TIMIL1			0x00000002
-#define TIMIL2			0x00000004
-#define TIMIL3			0x00000008
-#define TIMIL4			0x00010000
-#define TIMIL5			0x00020000
-#define TIMIL6			0x00040000
-#define TIMIL7			0x00080000
-#define TIMIL8			0x0001
-#define TIMIL9			0x0002
-#define TIMIL10			0x0004
-#define TIMIL11			0x0008
-#define TOVL_ERR0		0x00000010
-#define TOVL_ERR1		0x00000020
-#define TOVL_ERR2		0x00000040
-#define TOVL_ERR3		0x00000080
-#define TOVL_ERR4		0x00100000
-#define TOVL_ERR5		0x00200000
-#define TOVL_ERR6		0x00400000
-#define TOVL_ERR7		0x00800000
-#define TOVL_ERR8		0x0010
-#define TOVL_ERR9		0x0020
-#define TOVL_ERR10		0x0040
-#define TOVL_ERR11		0x0080
-#define TRUN0			0x00001000
-#define TRUN1			0x00002000
-#define TRUN2			0x00004000
-#define TRUN3			0x00008000
-#define TRUN4			0x10000000
-#define TRUN5			0x20000000
-#define TRUN6			0x40000000
-#define TRUN7			0x80000000
-#define TRUN8			0x1000
-#define TRUN9			0x2000
-#define TRUN10			0x4000
-#define TRUN11			0x8000
-
-#define TIMIL0_P		0x00
-#define TIMIL1_P		0x01
-#define TIMIL2_P		0x02
-#define TIMIL3_P		0x03
-#define TIMIL4_P		0x10
-#define TIMIL5_P		0x11
-#define TIMIL6_P		0x12
-#define TIMIL7_P		0x13
-#define TIMIL8_P		0x00
-#define TIMIL9_P		0x01
-#define TIMIL10_P		0x02
-#define TIMIL11_P		0x03
-#define TOVL_ERR0_P		0x04
-#define TOVL_ERR1_P		0x05
-#define TOVL_ERR2_P		0x06
-#define TOVL_ERR3_P		0x07
-#define TOVL_ERR4_P		0x14
-#define TOVL_ERR5_P		0x15
-#define TOVL_ERR6_P		0x16
-#define TOVL_ERR7_P		0x17
-#define TOVL_ERR8_P		0x04
-#define TOVL_ERR9_P		0x05
-#define TOVL_ERR10_P		0x06
-#define TOVL_ERR11_P		0x07
-#define TRUN0_P			0x0C
-#define TRUN1_P			0x0D
-#define TRUN2_P			0x0E
-#define TRUN3_P			0x0F
-#define TRUN4_P			0x1C
-#define TRUN5_P			0x1D
-#define TRUN6_P			0x1E
-#define TRUN7_P			0x1F
-#define TRUN8_P			0x0C
-#define TRUN9_P			0x0D
-#define TRUN10_P		0x0E
-#define TRUN11_P		0x0F
-
-// TIMERx_CONFIG Registers
-#define PWM_OUT			0x0001
-#define WDTH_CAP		0x0002
-#define EXT_CLK			0x0003
-#define PULSE_HI		0x0004
-#define PERIOD_CNT		0x0008
-#define IRQ_ENA			0x0010
-#define TIN_SEL			0x0020
-#define OUT_DIS			0x0040
-#define CLK_SEL			0x0080
-#define TOGGLE_HI		0x0100
-#define EMU_RUN			0x0200
-#define ERR_TYP(x)		((x & 0x03) << 14)
-
-#define TMODE_P0		0x00
-#define TMODE_P1		0x01
-#define PULSE_HI_P		0x02
-#define PERIOD_CNT_P		0x03
-#define IRQ_ENA_P		0x04
-#define TIN_SEL_P		0x05
-#define OUT_DIS_P		0x06
-#define CLK_SEL_P		0x07
-#define TOGGLE_HI_P		0x08
-#define EMU_RUN_P		0x09
-#define ERR_TYP_P0		0x0E
-#define ERR_TYP_P1		0x0F
-
-/// ******************   PROGRAMMABLE FLAG MASKS  *********************
-
-//  General Purpose IO (0xFFC00700 - 0xFFC007FF)  Masks
-#define PF0			0x0001
-#define PF1			0x0002
-#define PF2			0x0004
-#define PF3			0x0008
-#define PF4			0x0010
-#define PF5			0x0020
-#define PF6			0x0040
-#define PF7			0x0080
-#define PF8			0x0100
-#define PF9			0x0200
-#define PF10			0x0400
-#define PF11			0x0800
-#define PF12			0x1000
-#define PF13			0x2000
-#define PF14			0x4000
-#define PF15			0x8000
-
-//  General Purpose IO (0xFFC00700 - 0xFFC007FF)  BIT POSITIONS
-#define PF0_P			0
-#define PF1_P			1
-#define PF2_P			2
-#define PF3_P			3
-#define PF4_P			4
-#define PF5_P			5
-#define PF6_P			6
-#define PF7_P			7
-#define PF8_P			8
-#define PF9_P			9
-#define PF10_P			10
-#define PF11_P			11
-#define PF12_P			12
-#define PF13_P			13
-#define PF14_P			14
-#define PF15_P			15
-
-// ***********  SERIAL PERIPHERAL INTERFACE (SPI) MASKS  ****************
-
-//// SPI_CTL Masks
-#define TIMOD			0x00000003	// Transfer initiation mode
-						// and interrupt generation
-#define SZ			0x00000004	// Send Zero (=0) or last
-						// (=1) word when TDBR empty.
-#define GM			0x00000008	// When RDBR full, get more
-						// (=1) data or discard (=0)
-						// incoming Data
-#define PSSE			0x00000010	// Enable (=1) Slave-Select
-						// input for Master.
-#define EMISO			0x00000020	// Enable (=1) MISO pin as an
-						// output.
-#define SIZE			0x00000100	// Word length (0 => 8 bits,
-						// 1 => 16 bits)
-#define LSBF			0x00000200	// Data format (0 => MSB
-						// sent/received first 1 =>
-						// LSB sent/received first)
-#define CPHA			0x00000400	// Clock phase (0 => SPICLK
-						// starts toggling in middle
-						// of xfer, 1 => SPICLK
-						// toggles at the beginning
-						// of xfer.
-#define CPOL			0x00000800	// Clock polarity (0 =>
-						// active-high, 1 =>
-						// active-low)
-#define MSTR			0x00001000	// Configures SPI as master
-						// (=1) or slave (=0)
-#define WOM			0x00002000	// Open drain (=1) data
-						// output enable (for MOSI
-						// and MISO)
-#define SPE			0x00004000	// SPI module enable (=1),
-						// disable (=0)
-
-//// SPI_FLG Masks
-#define FLS1			0x00000002	// Enables (=1) SPI_FLOUT1 as
-						// flag output for SPI
-						// Slave-select
-#define FLS2			0x00000004	// Enables (=1) SPI_FLOUT2 as
-						// flag output for SPI
-						// Slave-select
-#define FLS3			0x00000008	// Enables (=1) SPI_FLOUT3 as
-						// flag output for SPI
-						// Slave-select
-#define FLS4			0x00000010	// Enables (=1) SPI_FLOUT4 as
-						// flag output for SPI
-						// Slave-select
-#define FLS5			0x00000020	// Enables (=1) SPI_FLOUT5 as
-						// flag output for SPI
-						// Slave-select
-#define FLS6			0x00000040	// Enables (=1) SPI_FLOUT6 as
-						// flag output for SPI
-						// Slave-select
-#define FLS7			0x00000080	// Enables (=1) SPI_FLOUT7 as
-						// flag output for SPI
-						// Slave-select
-#define FLG1			0x00000200	// Activates (=0) SPI_FLOUT1
-						// as flag output for SPI
-						// Slave-select
-#define FLG2			0x00000400	// Activates (=0) SPI_FLOUT2
-						// as flag output for SPI
-						// Slave-select
-#define FLG3			0x00000800	// Activates (=0) SPI_FLOUT3
-						// as flag output for SPI
-						// Slave-select
-#define FLG4			0x00001000	// Activates (=0) SPI_FLOUT4
-						// as flag output for SPI
-						// Slave-select
-#define FLG5			0x00002000	// Activates (=0) SPI_FLOUT5
-						// as flag output for SPI
-						// Slave-select
-#define FLG6			0x00004000	// Activates (=0) SPI_FLOUT6
-						// as flag output for SPI
-						// Slave-select
-#define FLG7			0x00008000	// Activates (=0) SPI_FLOUT7
-						// as flag output for SPI
-						// Slave-select
-
-//// SPI_FLG Bit Positions
-#define FLS1_P			0x00000001	// Enables (=1) SPI_FLOUT1 as
-						// flag output for SPI
-						// Slave-select
-#define FLS2_P			0x00000002	// Enables (=1) SPI_FLOUT2 as
-						// flag output for SPI
-						// Slave-select
-#define FLS3_P			0x00000003	// Enables (=1) SPI_FLOUT3 as
-						// flag output for SPI
-						// Slave-select
-#define FLS4_P			0x00000004	// Enables (=1) SPI_FLOUT4 as
-						// flag output for SPI
-						// Slave-select
-#define FLS5_P			0x00000005	// Enables (=1) SPI_FLOUT5 as
-						// flag output for SPI
-						// Slave-select
-#define FLS6_P			0x00000006	// Enables (=1) SPI_FLOUT6 as
-						// flag output for SPI
-						// Slave-select
-#define FLS7_P			0x00000007	// Enables (=1) SPI_FLOUT7 as
-						// flag output for SPI
-						// Slave-select
-#define FLG1_P			0x00000009	// Activates (=0) SPI_FLOUT1
-						// as flag output for SPI
-						// Slave-select
-#define FLG2_P			0x0000000A	// Activates (=0) SPI_FLOUT2
-						// as flag output for SPI
-						// Slave-select
-#define FLG3_P			0x0000000B	// Activates (=0) SPI_FLOUT3
-						// as flag output for SPI
-						// Slave-select
-#define FLG4_P			0x0000000C	// Activates (=0) SPI_FLOUT4
-						// as flag output for SPI
-						// Slave-select
-#define FLG5_P			0x0000000D	// Activates (=0) SPI_FLOUT5
-						// as flag output for SPI
-						// Slave-select
-#define FLG6_P			0x0000000E	// Activates (=0) SPI_FLOUT6
-						// as flag output for SPI
-						// Slave-select
-#define FLG7_P			0x0000000F	// Activates (=0) SPI_FLOUT7
-						// as flag output for SPI
-						// Slave-select
-
-//// SPI_STAT Masks
-#define SPIF			0x00000001	// Set (=1) when SPI
-						// single-word transfer
-						// complete
-#define MODF			0x00000002	// Set (=1) in a master
-						// device when some other
-						// device tries to become
-						// master
-#define TXE			0x00000004	// Set (=1) when transmission
-						// occurs with no new data in
-						// SPI_TDBR
-#define TXS			0x00000008	// SPI_TDBR Data Buffer
-						// Status (0=Empty, 1=Full)
-#define RBSY			0x00000010	// Set (=1) when data is
-						// received with RDBR full
-#define RXS			0x00000020	// SPI_RDBR Data Buffer
-						// Status (0=Empty, 1=Full)
-#define TXCOL			0x00000040	// When set (=1), corrupt
-						// data may have been
-						// transmitted
-
-// *********************  ASYNCHRONOUS MEMORY CONTROLLER MASKS  *************
-
-// AMGCTL Masks
-#define AMCKEN			0x0001	// Enable CLKOUT
-#define AMBEN_B0		0x0002	// Enable Asynchronous Memory Bank 0
-					// only
-#define AMBEN_B0_B1		0x0004	// Enable Asynchronous Memory Banks 0
-					// & 1 only
-#define AMBEN_B0_B1_B2		0x0006	// Enable Asynchronous Memory Banks 0,
-					// 1, and 2
-#define AMBEN_ALL		0x0008	// Enable Asynchronous Memory Banks
-					// (all) 0, 1, 2, and 3
-#define B0_PEN			0x0010	// Enable 16-bit packing Bank 0
-#define B1_PEN			0x0020	// Enable 16-bit packing Bank 1
-#define B2_PEN			0x0040	// Enable 16-bit packing Bank 2
-#define B3_PEN			0x0080	// Enable 16-bit packing Bank 3
-
-// AMGCTL Bit Positions
-#define AMCKEN_P		0x00000000	// Enable CLKOUT
-#define AMBEN_P0		0x00000001	// Asynchronous Memory
-						// Enable, 000 - banks 0-3
-						// disabled, 001 - Bank 0
-						// enabled
-#define AMBEN_P1		0x00000002	// Asynchronous Memory
-						// Enable, 010 - banks 0&1
-						// enabled, 011 - banks 0-3
-						// enabled
-#define AMBEN_P2		0x00000003	// Asynchronous Memory
-						// Enable, 1xx - All banks
-						// (bank 0, 1, 2, and 3)
-						// enabled
-#define B0_PEN_P		0x004	// Enable 16-bit packing Bank 0
-#define B1_PEN_P		0x005	// Enable 16-bit packing Bank 1
-#define B2_PEN_P		0x006	// Enable 16-bit packing Bank 2
-#define B3_PEN_P		0x007	// Enable 16-bit packing Bank 3
-
-// AMBCTL0 Masks
-#define B0RDYEN			0x00000001	// Bank 0 RDY Enable,
-						// 0=disable, 1=enable
-#define B0RDYPOL		0x00000002	// Bank 0 RDY Active high,
-						// 0=active low, 1=active high
-#define B0TT_1			0x00000004	// Bank 0 Transition Time from
-						// Read to Write = 1 cycle
-#define B0TT_2			0x00000008	// Bank 0 Transition Time from
-						// Read to Write = 2 cycles
-#define B0TT_3			0x0000000C	// Bank 0 Transition Time from
-						// Read to Write = 3 cycles
-#define B0TT_4			0x00000000	// Bank 0 Transition Time from
-						// Read to Write = 4 cycles
-#define B0ST_1			0x00000010	// Bank 0 Setup Time from AOE
-						// asserted to Read/Write
-						// asserted=1 cycle
-#define B0ST_2			0x00000020	// Bank 0 Setup Time from AOE
-						// asserted to Read/Write
-						// asserted=2 cycles
-#define B0ST_3			0x00000030	// Bank 0 Setup Time from AOE
-						// asserted to Read/Write
-						// asserted=3 cycles
-#define B0ST_4			0x00000000	// Bank 0 Setup Time from AOE
-						// asserted to Read/Write
-						// asserted=4 cycles
-#define B0HT_1			0x00000040	// Bank 0 Hold Time from
-						// Read/Write deasserted to AOE
-						// deasserted = 1 cycle
-#define B0HT_2			0x00000080	// Bank 0 Hold Time from
-						// Read/Write deasserted to AOE
-						// deasserted = 2 cycles
-#define B0HT_3			0x000000C0	// Bank 0 Hold Time from
-						// Read/Write deasserted to AOE
-						// deasserted = 3 cycles
-#define B0HT_0			0x00000000	// Bank 0 Hold Time from
-						// Read/Write deasserted to AOE
-						// deasserted = 0 cycles
-#define B0RAT_1			0x00000100	// Bank 0 Read Access Time =
-						// 1 cycle
-#define B0RAT_2			0x00000200	// Bank 0 Read Access Time =
-						// 2 cycles
-#define B0RAT_3			0x00000300	// Bank 0 Read Access Time =
-						// 3 cycles
-#define B0RAT_4			0x00000400	// Bank 0 Read Access Time =
-						// 4 cycles
-#define B0RAT_5			0x00000500	// Bank 0 Read Access Time =
-						// 5 cycles
-#define B0RAT_6			0x00000600	// Bank 0 Read Access Time =
-						// 6 cycles
-#define B0RAT_7			0x00000700	// Bank 0 Read Access Time =
-						// 7 cycles
-#define B0RAT_8			0x00000800	// Bank 0 Read Access Time =
-						// 8 cycles
-#define B0RAT_9			0x00000900	// Bank 0 Read Access Time =
-						// 9 cycles
-#define B0RAT_10		0x00000A00	// Bank 0 Read Access Time =
-						// 10 cycles
-#define B0RAT_11		0x00000B00	// Bank 0 Read Access Time =
-						// 11 cycles
-#define B0RAT_12		0x00000C00	// Bank 0 Read Access Time =
-						// 12 cycles
-#define B0RAT_13		0x00000D00	// Bank 0 Read Access Time =
-						// 13 cycles
-#define B0RAT_14		0x00000E00	// Bank 0 Read Access Time =
-						// 14 cycles
-#define B0RAT_15		0x00000F00	// Bank 0 Read Access Time =
-						// 15 cycles
-#define B0WAT_1			0x00001000	// Bank 0 Write Access Time =
-						// 1 cycle
-#define B0WAT_2			0x00002000	// Bank 0 Write Access Time =
-						// 2 cycles
-#define B0WAT_3			0x00003000	// Bank 0 Write Access Time =
-						// 3 cycles
-#define B0WAT_4			0x00004000	// Bank 0 Write Access Time =
-						// 4 cycles
-#define B0WAT_5			0x00005000	// Bank 0 Write Access Time =
-						// 5 cycles
-#define B0WAT_6			0x00006000	// Bank 0 Write Access Time =
-						// 6 cycles
-#define B0WAT_7			0x00007000	// Bank 0 Write Access Time =
-						// 7 cycles
-#define B0WAT_8			0x00008000	// Bank 0 Write Access Time =
-						// 8 cycles
-#define B0WAT_9			0x00009000	// Bank 0 Write Access Time =
-						// 9 cycles
-#define B0WAT_10		0x0000A000	// Bank 0 Write Access Time =
-						// 10 cycles
-#define B0WAT_11		0x0000B000	// Bank 0 Write Access Time =
-						// 11 cycles
-#define B0WAT_12		0x0000C000	// Bank 0 Write Access Time =
-						// 12 cycles
-#define B0WAT_13		0x0000D000	// Bank 0 Write Access Time =
-						// 13 cycles
-#define B0WAT_14		0x0000E000	// Bank 0 Write Access Time =
-						// 14 cycles
-#define B0WAT_15		0x0000F000	// Bank 0 Write Access Time =
-						// 15 cycles
-#define B1RDYEN			0x00010000	// Bank 1 RDY enable,
-						// 0=disable, 1=enable
-#define B1RDYPOL		0x00020000	// Bank 1 RDY Active high,
-						// 0=active low, 1=active
-						// high
-#define B1TT_1			0x00040000	// Bank 1 Transition Time
-						// from Read to Write = 1
-						// cycle
-#define B1TT_2			0x00080000	// Bank 1 Transition Time
-						// from Read to Write = 2
-						// cycles
-#define B1TT_3			0x000C0000	// Bank 1 Transition Time
-						// from Read to Write = 3
-						// cycles
-#define B1TT_4			0x00000000	// Bank 1 Transition Time
-						// from Read to Write = 4
-						// cycles
-#define B1ST_1			0x00100000	// Bank 1 Setup Time from AOE
-						// asserted to Read or Write
-						// asserted = 1 cycle
-#define B1ST_2			0x00200000	// Bank 1 Setup Time from AOE
-						// asserted to Read or Write
-						// asserted = 2 cycles
-#define B1ST_3			0x00300000	// Bank 1 Setup Time from AOE
-						// asserted to Read or Write
-						// asserted = 3 cycles
-#define B1ST_4			0x00000000	// Bank 1 Setup Time from AOE
-						// asserted to Read or Write
-						// asserted = 4 cycles
-#define B1HT_1			0x00400000	// Bank 1 Hold Time from Read
-						// or Write deasserted to AOE
-						// deasserted = 1 cycle
-#define B1HT_2			0x00800000	// Bank 1 Hold Time from Read
-						// or Write deasserted to AOE
-						// deasserted = 2 cycles
-#define B1HT_3			0x00C00000	// Bank 1 Hold Time from Read
-						// or Write deasserted to AOE
-						// deasserted = 3 cycles
-#define B1HT_0			0x00000000	// Bank 1 Hold Time from Read
-						// or Write deasserted to AOE
-						// deasserted = 0 cycles
-#define B1RAT_1			0x01000000	// Bank 1 Read Access Time =
-						// 1 cycle
-#define B1RAT_2			0x02000000	// Bank 1 Read Access Time =
-						// 2 cycles
-#define B1RAT_3			0x03000000	// Bank 1 Read Access Time =
-						// 3 cycles
-#define B1RAT_4			0x04000000	// Bank 1 Read Access Time =
-						// 4 cycles
-#define B1RAT_5			0x05000000	// Bank 1 Read Access Time =
-						// 5 cycles
-#define B1RAT_6			0x06000000	// Bank 1 Read Access Time =
-						// 6 cycles
-#define B1RAT_7			0x07000000	// Bank 1 Read Access Time =
-						// 7 cycles
-#define B1RAT_8			0x08000000	// Bank 1 Read Access Time =
-						// 8 cycles
-#define B1RAT_9			0x09000000	// Bank 1 Read Access Time =
-						// 9 cycles
-#define B1RAT_10		0x0A000000	// Bank 1 Read Access Time =
-						// 10 cycles
-#define B1RAT_11		0x0B000000	// Bank 1 Read Access Time =
-						// 11 cycles
-#define B1RAT_12		0x0C000000	// Bank 1 Read Access Time =
-						// 12 cycles
-#define B1RAT_13		0x0D000000	// Bank 1 Read Access Time =
-						// 13 cycles
-#define B1RAT_14		0x0E000000	// Bank 1 Read Access Time =
-						// 14 cycles
-#define B1RAT_15		0x0F000000	// Bank 1 Read Access Time =
-						// 15 cycles
-#define B1WAT_1			0x10000000	// Bank 1 Write Access Time =
-						// 1 cycle
-#define B1WAT_2			0x20000000	// Bank 1 Write Access Time =
-						// 2 cycles
-#define B1WAT_3			0x30000000	// Bank 1 Write Access Time =
-						// 3 cycles
-#define B1WAT_4			0x40000000	// Bank 1 Write Access Time =
-						// 4 cycles
-#define B1WAT_5			0x50000000	// Bank 1 Write Access Time =
-						// 5 cycles
-#define B1WAT_6			0x60000000	// Bank 1 Write Access Time =
-						// 6 cycles
-#define B1WAT_7			0x70000000	// Bank 1 Write Access Time =
-						// 7 cycles
-#define B1WAT_8			0x80000000	// Bank 1 Write Access Time =
-						// 8 cycles
-#define B1WAT_9			0x90000000	// Bank 1 Write Access Time =
-						// 9 cycles
-#define B1WAT_10		0xA0000000	// Bank 1 Write Access Time =
-						// 10 cycles
-#define B1WAT_11		0xB0000000	// Bank 1 Write Access Time =
-						// 11 cycles
-#define B1WAT_12		0xC0000000	// Bank 1 Write Access Time =
-						// 12 cycles
-#define B1WAT_13		0xD0000000	// Bank 1 Write Access Time =
-						// 13 cycles
-#define B1WAT_14		0xE0000000	// Bank 1 Write Access Time =
-						// 14 cycles
-#define B1WAT_15		0xF0000000	// Bank 1 Write Access Time =
-						// 15 cycles
-
-// AMBCTL1 Masks
-#define B2RDYEN			0x00000001	// Bank 2 RDY Enable,
-						// 0=disable, 1=enable
-#define B2RDYPOL		0x00000002	// Bank 2 RDY Active high,
-						// 0=active low, 1=active
-						// high
-#define B2TT_1			0x00000004	// Bank 2 Transition Time
-						// from Read to Write = 1
-						// cycle
-#define B2TT_2			0x00000008	// Bank 2 Transition Time
-						// from Read to Write = 2
-						// cycles
-#define B2TT_3			0x0000000C	// Bank 2 Transition Time
-						// from Read to Write = 3
-						// cycles
-#define B2TT_4			0x00000000	// Bank 2 Transition Time
-						// from Read to Write = 4
-						// cycles
-#define B2ST_1			0x00000010	// Bank 2 Setup Time from AOE
-						// asserted to Read or Write
-						// asserted = 1 cycle
-#define B2ST_2			0x00000020	// Bank 2 Setup Time from AOE
-						// asserted to Read or Write
-						// asserted = 2 cycles
-#define B2ST_3			0x00000030	// Bank 2 Setup Time from AOE
-						// asserted to Read or Write
-						// asserted = 3 cycles
-#define B2ST_4			0x00000000	// Bank 2 Setup Time from AOE
-						// asserted to Read or Write
-						// asserted = 4 cycles
-#define B2HT_1			0x00000040	// Bank 2 Hold Time from Read
-						// or Write deasserted to AOE
-						// deasserted = 1 cycle
-#define B2HT_2			0x00000080	// Bank 2 Hold Time from Read
-						// or Write deasserted to AOE
-						// deasserted = 2 cycles
-#define B2HT_3			0x000000C0	// Bank 2 Hold Time from Read
-						// or Write deasserted to AOE
-						// deasserted = 3 cycles
-#define B2HT_0			0x00000000	// Bank 2 Hold Time from Read
-						// or Write deasserted to AOE
-						// deasserted = 0 cycles
-#define B2RAT_1			0x00000100	// Bank 2 Read Access Time =
-						// 1 cycle
-#define B2RAT_2			0x00000200	// Bank 2 Read Access Time =
-						// 2 cycles
-#define B2RAT_3			0x00000300	// Bank 2 Read Access Time =
-						// 3 cycles
-#define B2RAT_4			0x00000400	// Bank 2 Read Access Time =
-						// 4 cycles
-#define B2RAT_5			0x00000500	// Bank 2 Read Access Time =
-						// 5 cycles
-#define B2RAT_6			0x00000600	// Bank 2 Read Access Time =
-						// 6 cycles
-#define B2RAT_7			0x00000700	// Bank 2 Read Access Time =
-						// 7 cycles
-#define B2RAT_8			0x00000800	// Bank 2 Read Access Time =
-						// 8 cycles
-#define B2RAT_9			0x00000900	// Bank 2 Read Access Time =
-						// 9 cycles
-#define B2RAT_10		0x00000A00	// Bank 2 Read Access Time =
-						// 10 cycles
-#define B2RAT_11		0x00000B00	// Bank 2 Read Access Time =
-						// 11 cycles
-#define B2RAT_12		0x00000C00	// Bank 2 Read Access Time =
-						// 12 cycles
-#define B2RAT_13		0x00000D00	// Bank 2 Read Access Time =
-						// 13 cycles
-#define B2RAT_14		0x00000E00	// Bank 2 Read Access Time =
-						// 14 cycles
-#define B2RAT_15		0x00000F00	// Bank 2 Read Access Time =
-						// 15 cycles
-#define B2WAT_1			0x00001000	// Bank 2 Write Access Time =
-						// 1 cycle
-#define B2WAT_2			0x00002000	// Bank 2 Write Access Time =
-						// 2 cycles
-#define B2WAT_3			0x00003000	// Bank 2 Write Access Time =
-						// 3 cycles
-#define B2WAT_4			0x00004000	// Bank 2 Write Access Time =
-						// 4 cycles
-#define B2WAT_5			0x00005000	// Bank 2 Write Access Time =
-						// 5 cycles
-#define B2WAT_6			0x00006000	// Bank 2 Write Access Time =
-						// 6 cycles
-#define B2WAT_7			0x00007000	// Bank 2 Write Access Time =
-						// 7 cycles
-#define B2WAT_8			0x00008000	// Bank 2 Write Access Time =
-						// 8 cycles
-#define B2WAT_9			0x00009000	// Bank 2 Write Access Time =
-						// 9 cycles
-#define B2WAT_10		0x0000A000	// Bank 2 Write Access Time =
-						// 10 cycles
-#define B2WAT_11		0x0000B000	// Bank 2 Write Access Time =
-						// 11 cycles
-#define B2WAT_12		0x0000C000	// Bank 2 Write Access Time =
-						// 12 cycles
-#define B2WAT_13		0x0000D000	// Bank 2 Write Access Time =
-						// 13 cycles
-#define B2WAT_14		0x0000E000	// Bank 2 Write Access Time =
-						// 14 cycles
-#define B2WAT_15		0x0000F000	// Bank 2 Write Access Time =
-						// 15 cycles
-#define B3RDYEN			0x00010000	// Bank 3 RDY enable,
-						// 0=disable, 1=enable
-#define B3RDYPOL		0x00020000	// Bank 3 RDY Active high,
-						// 0=active low, 1=active
-						// high
-#define B3TT_1			0x00040000	// Bank 3 Transition Time
-						// from Read to Write = 1
-						// cycle
-#define B3TT_2			0x00080000	// Bank 3 Transition Time
-						// from Read to Write = 2
-						// cycles
-#define B3TT_3			0x000C0000	// Bank 3 Transition Time
-						// from Read to Write = 3
-						// cycles
-#define B3TT_4			0x00000000	// Bank 3 Transition Time
-						// from Read to Write = 4
-						// cycles
-#define B3ST_1			0x00100000	// Bank 3 Setup Time from AOE
-						// asserted to Read or Write
-						// asserted = 1 cycle
-#define B3ST_2			0x00200000	// Bank 3 Setup Time from AOE
-						// asserted to Read or Write
-						// asserted = 2 cycles
-#define B3ST_3			0x00300000	// Bank 3 Setup Time from AOE
-						// asserted to Read or Write
-						// asserted = 3 cycles
-#define B3ST_4			0x00000000	// Bank 3 Setup Time from AOE
-						// asserted to Read or Write
-						// asserted = 4 cycles
-#define B3HT_1			0x00400000	// Bank 3 Hold Time from Read
-						// or Write deasserted to AOE
-						// deasserted = 1 cycle
-#define B3HT_2			0x00800000	// Bank 3 Hold Time from Read
-						// or Write deasserted to AOE
-						// deasserted = 2 cycles
-#define B3HT_3			0x00C00000	// Bank 3 Hold Time from Read
-						// or Write deasserted to AOE
-						// deasserted = 3 cycles
-#define B3HT_0			0x00000000	// Bank 3 Hold Time from Read
-						// or Write deasserted to AOE
-						// deasserted = 0 cycles
-#define B3RAT_1			0x01000000	// Bank 3 Read Access Time =
-						// 1 cycle
-#define B3RAT_2			0x02000000	// Bank 3 Read Access Time =
-						// 2 cycles
-#define B3RAT_3			0x03000000	// Bank 3 Read Access Time =
-						// 3 cycles
-#define B3RAT_4			0x04000000	// Bank 3 Read Access Time =
-						// 4 cycles
-#define B3RAT_5			0x05000000	// Bank 3 Read Access Time =
-						// 5 cycles
-#define B3RAT_6			0x06000000	// Bank 3 Read Access Time =
-						// 6 cycles
-#define B3RAT_7			0x07000000	// Bank 3 Read Access Time =
-						// 7 cycles
-#define B3RAT_8			0x08000000	// Bank 3 Read Access Time =
-						// 8 cycles
-#define B3RAT_9			0x09000000	// Bank 3 Read Access Time =
-						// 9 cycles
-#define B3RAT_10		0x0A000000	// Bank 3 Read Access Time =
-						// 10 cycles
-#define B3RAT_11		0x0B000000	// Bank 3 Read Access Time =
-						// 11 cycles
-#define B3RAT_12		0x0C000000	// Bank 3 Read Access Time =
-						// 12 cycles
-#define B3RAT_13		0x0D000000	// Bank 3 Read Access Time =
-						// 13 cycles
-#define B3RAT_14		0x0E000000	// Bank 3 Read Access Time =
-						// 14 cycles
-#define B3RAT_15		0x0F000000	// Bank 3 Read Access Time =
-						// 15 cycles
-#define B3WAT_1			0x10000000	// Bank 3 Write Access Time =
-						// 1 cycle
-#define B3WAT_2			0x20000000	// Bank 3 Write Access Time =
-						// 2 cycles
-#define B3WAT_3			0x30000000	// Bank 3 Write Access Time =
-						// 3 cycles
-#define B3WAT_4			0x40000000	// Bank 3 Write Access Time =
-						// 4 cycles
-#define B3WAT_5			0x50000000	// Bank 3 Write Access Time =
-						// 5 cycles
-#define B3WAT_6			0x60000000	// Bank 3 Write Access Time =
-						// 6 cycles
-#define B3WAT_7			0x70000000	// Bank 3 Write Access Time =
-						// 7 cycles
-#define B3WAT_8			0x80000000	// Bank 3 Write Access Time =
-						// 8 cycles
-#define B3WAT_9			0x90000000	// Bank 3 Write Access Time =
-						// 9 cycles
-#define B3WAT_10		0xA0000000	// Bank 3 Write Access Time =
-						// 10 cycles
-#define B3WAT_11		0xB0000000	// Bank 3 Write Access Time =
-						// 11 cycles
-#define B3WAT_12		0xC0000000	// Bank 3 Write Access Time =
-						// 12 cycles
-#define B3WAT_13		0xD0000000	// Bank 3 Write Access Time =
-						// 13 cycles
-#define B3WAT_14		0xE0000000	// Bank 3 Write Access Time =
-						// 14 cycles
-#define B3WAT_15		0xF0000000	// Bank 3 Write Access Time =
-						// 15 cycles
-
-// **********************  SDRAM CONTROLLER MASKS  ***************************
-
-// EBIU_SDGCTL Masks
-#define SCTLE			0x00000001	// Enable SCLK[0], /SRAS,
-						// /SCAS, /SWE, SDQM[3:0]
-#define CL_2			0x00000008	// SDRAM CAS latency = 2
-						// cycles
-#define CL_3			0x0000000C	// SDRAM CAS latency = 3
-						// cycles
-#define PFE			0x00000010	// Enable SDRAM prefetch
-#define PFP			0x00000020	// Prefetch has priority over
-						// AMC requests
-#define TRAS_1			0x00000040	// SDRAM tRAS = 1 cycle
-#define TRAS_2			0x00000080	// SDRAM tRAS = 2 cycles
-#define TRAS_3			0x000000C0	// SDRAM tRAS = 3 cycles
-#define TRAS_4			0x00000100	// SDRAM tRAS = 4 cycles
-#define TRAS_5			0x00000140	// SDRAM tRAS = 5 cycles
-#define TRAS_6			0x00000180	// SDRAM tRAS = 6 cycles
-#define TRAS_7			0x000001C0	// SDRAM tRAS = 7 cycles
-#define TRAS_8			0x00000200	// SDRAM tRAS = 8 cycles
-#define TRAS_9			0x00000240	// SDRAM tRAS = 9 cycles
-#define TRAS_10			0x00000280	// SDRAM tRAS = 10 cycles
-#define TRAS_11			0x000002C0	// SDRAM tRAS = 11 cycles
-#define TRAS_12			0x00000300	// SDRAM tRAS = 12 cycles
-#define TRAS_13			0x00000340	// SDRAM tRAS = 13 cycles
-#define TRAS_14			0x00000380	// SDRAM tRAS = 14 cycles
-#define TRAS_15			0x000003C0	// SDRAM tRAS = 15 cycles
-#define TRP_1			0x00000800	// SDRAM tRP = 1 cycle
-#define TRP_2			0x00001000	// SDRAM tRP = 2 cycles
-#define TRP_3			0x00001800	// SDRAM tRP = 3 cycles
-#define TRP_4			0x00002000	// SDRAM tRP = 4 cycles
-#define TRP_5			0x00002800	// SDRAM tRP = 5 cycles
-#define TRP_6			0x00003000	// SDRAM tRP = 6 cycles
-#define TRP_7			0x00003800	// SDRAM tRP = 7 cycles
-#define TRCD_1			0x00008000	// SDRAM tRCD = 1 cycle
-#define TRCD_2			0x00010000	// SDRAM tRCD = 2 cycles
-#define TRCD_3			0x00018000	// SDRAM tRCD = 3 cycles
-#define TRCD_4			0x00020000	// SDRAM tRCD = 4 cycles
-#define TRCD_5			0x00028000	// SDRAM tRCD = 5 cycles
-#define TRCD_6			0x00030000	// SDRAM tRCD = 6 cycles
-#define TRCD_7			0x00038000	// SDRAM tRCD = 7 cycles
-#define TWR_1			0x00080000	// SDRAM tWR = 1 cycle
-#define TWR_2			0x00100000	// SDRAM tWR = 2 cycles
-#define TWR_3			0x00180000	// SDRAM tWR = 3 cycles
-#define PUPSD			0x00200000	// Power-up start delay
-#define PSM			0x00400000	// SDRAM power-up sequence =
-						// Precharge, mode register
-						// set, 8 CBR refresh cycles
-#define PSS			0x00800000	// enable SDRAM power-up
-						// sequence on next SDRAM access
-#define SRFS			0x01000000	// Start SDRAM self-refresh
-						// mode
-#define EBUFE			0x02000000	// Enable external buffering
-						// timing
-#define FBBRW			0x04000000	// Fast back-to-back read
-						// write enable
-#define EMREN			0x10000000	// Extended mode register
-						// enable
-#define TCSR			0x20000000	// Temp compensated self
-						// refresh value 85 deg C
-#define CDDBG			0x40000000	// Tristate SDRAM controls
-						// during bus grant
-
-// EBIU_SDBCTL Masks
-#define EB0_E			0x00000001	// Enable SDRAM
-						// external bank 0
-#define EB0_SZ_16		0x00000000	// SDRAM external
-						// bank size = 16MB
-#define EB0_SZ_32		0x00000002	// SDRAM external
-						// bank size = 32MB
-#define EB0_SZ_64		0x00000004	// SDRAM external
-						// bank size = 64MB
-#define EB0_SZ_128		0x00000006	// SDRAM external
-						// bank size = 128MB
-#define EB0_CAW_8		0x00000000	// SDRAM external bank column
-						// address width = 8 bits
-#define EB0_CAW_9		0x00000010	// SDRAM external bank column
-						// address width = 9 bits
-#define EB0_CAW_10		0x00000020	// SDRAM external bank column
-						// address width = 9 bits
-#define EB0_CAW_11		0x00000030	// SDRAM external bank column
-						// address width = 9 bits
-
-#define EB1_E			0x00000100	// Enable SDRAM
-						// external bank 1
-#define EB1__SZ_16		0x00000000	// SDRAM external
-						// bank size = 16MB
-#define EB1__SZ_32		0x00000200	// SDRAM external
-						// bank size = 32MB
-#define EB1__SZ_64		0x00000400	// SDRAM external
-						// bank size = 64MB
-#define EB1__SZ_128		0x00000600	// SDRAM external
-						// bank size = 128MB
-#define EB1__CAW_8		0x00000000	// SDRAM external bank column
-						// address width = 8 bits
-#define EB1__CAW_9		0x00001000	// SDRAM external bank column
-						// address width = 9 bits
-#define EB1__CAW_10		0x00002000	// SDRAM external bank column
-						// address width = 9 bits
-#define EB1__CAW_11		0x00003000	// SDRAM external bank column
-						// address width = 9 bits
-
-#define EB2__E			0x00010000	// Enable SDRAM
-						// external bank 2
-#define EB2__SZ_16		0x00000000	// SDRAM external
-						// bank size = 16MB
-#define EB2__SZ_32		0x00020000	// SDRAM external
-						// bank size = 32MB
-#define EB2__SZ_64		0x00040000	// SDRAM external
-						// bank size = 64MB
-#define EB2__SZ_128		0x00060000	// SDRAM external
-						// bank size = 128MB
-#define EB2__CAW_8		0x00000000	// SDRAM external bank column
-						// address width = 8 bits
-#define EB2__CAW_9		0x00100000	// SDRAM external bank column
-						// address width = 9 bits
-#define EB2__CAW_10		0x00200000	// SDRAM external bank column
-						// address width = 9 bits
-#define EB2__CAW_11		0x00300000	// SDRAM external bank column
-						// address width = 9 bits
-
-#define EB3__E			0x01000000	// Enable SDRAM external bank 3
-#define EB3__SZ_16		0x00000000	// SDRAM external
-						// bank size = 16MB
-#define EB3__SZ_32		0x02000000	// SDRAM external
-						// bank size = 32MB
-#define EB3__SZ_64		0x04000000	// SDRAM external
-						// bank size = 64MB
-#define EB3__SZ_128		0x06000000	// SDRAM external
-						// bank size = 128MB
-#define EB3__CAW_8		0x00000000	// SDRAM external bank column
-						// address width = 8 bits
-#define EB3__CAW_9		0x10000000	// SDRAM external bank column
-						// address width = 9 bits
-#define EB3__CAW_10		0x20000000	// SDRAM external bank column
-						// address width = 9 bits
-#define EB3__CAW_11		0x30000000	// SDRAM external bank column
-						// address width = 9 bits
-
-// EBIU_SDSTAT Masks
-#define SDCI			0x00000001	// SDRAM controller is idle
-#define SDSRA			0x00000002	// SDRAM SDRAM self refresh
-						// is active
-#define SDPUA			0x00000004	// SDRAM power up active
-#define SDRS			0x00000008	// SDRAM is in reset state
-#define SDEASE			0x00000010	// SDRAM EAB sticky error
-						// status - W1C
-#define BGSTAT			0x00000020	// Bus granted
-
-
-#if 1	/* comment by mhfan */
-#define COREMMR_BASE		0xFFE00000	// Core MMRs
-#define SYSMMR_BASE		0xFFC00000	// System MMRs
-
-// Watchdog Timer registers for Core A (0xFFC0 0200-0xFFC0 02FF)
-#define WDOG_CTL 		0xFFC00200	// Watchdog Control register
-#define WDOG_CNT 		0xFFC00204	// Watchdog Count register
-#define WDOG_STAT 		0xFFC00208	// Watchdog Status register
-
-// Programmable Flag 0 registers (0xFFC0 0700-0xFFC0 07FF)
-#define FIO_FLAG_D 		0xFFC00700	// Flag Data register
-#define FIO_FLAG_C 	        0xFFC00704	// Flag Clear register
-#define FIO_FLAG_S 	        0xFFC00708	// Flag Set register
-#define FIO_FLAG_T 	        0xFFC0070C	// Flag Toggle register
-#define FIO_MASKA_D 	        0xFFC00710	// Flag Mask Interrupt A Data
-						// register
-#define FIO_MASKA_C 	        0xFFC00714	// Flag Mask Interrupt A Clear
-						// register
-#define FIO_MASKA_S 	        0xFFC00718	// Flag Mask Interrupt A Set
-						// register
-#define FIO_MASKA_T 	        0xFFC0071C	// Flag Mask Interrupt A Toggle
-						// register
-#define FIO_MASKB_D 	        0xFFC00720	// Flag Mask Interrupt B Data
-						// register
-#define FIO_MASKB_C 	        0xFFC00724	// Flag Mask Interrupt B Clear
-						// register
-#define FIO_MASKB_S 	        0xFFC00728	// Flag Mask Interrupt B Set
-						// register
-#define FIO_MASKB_T 	        0xFFC0072C	// Flag Mask Interrupt B Toggle
-						// register
-#define FIO_DIR 		0xFFC00730	// Flag Direction  register
-#define FIO_POLAR 	        0xFFC00734	// Flag Polarity register
-#define FIO_EDGE 	        0xFFC00738	// Flag Interrupt Sensitivity
-						// register
-#define FIO_BOTH 	        0xFFC0073C	// Flag Set on Both Edges
-						// register
-#define FIO_INEN 	        0xFFC00740	// Flag Input Enable register
-
-// Parallel Peripheral Interface (PPI) 0 registers (0xFFC0 1000-0xFFC0 10FF)
-#define PPI_CONTROL 		0xFFC01000	// PPI0 Control register
-#define PPI_STATUS 		0xFFC01004	// PPI0 Status register
-#define PPI_COUNT 		0xFFC01008	// PPI0 Transfer Count register
-#define PPI_DELAY 		0xFFC0100C	// PPI0 Delay Count register
-#define PPI_FRAME 		0xFFC01010	// PPI0 Frame Length register
-
-// System Reset and Interrupt Controller registers for
-// core A (0xFFC0 0100-0xFFC0 01FF)
-#define SWRST			0xFFC00100	// Software Reset register
-#define SYSCR			0xFFC00104	// System Reset Configuration
-						// register
-#define RVECT			0xFFC00108	// SIC Reset Vector Address
-						// Register
-#define SIC_SWRST		0xFFC00100	// Software Reset register
-#define SIC_SYSCR		0xFFC00104	// System Reset Configuration
-						// register
-#define SIC_RVECT		0xFFC00108	// SIC Reset Vector Address
-			    			// Register
-#define SIC_IMASK		0xFFC0010C	// SIC Interrupt Mask
-						// register 0 - hack to fix
-						// old tests
-#define SIC_IAR			0xFFC00124	// SIC Interrupt Assignment
-						// Register 0
-#define SIC_IAR1		0xFFC00128	// SIC Interrupt Assignment
-						// Register 1
-#define SIC_IAR2		0xFFC0012C	// SIC Interrupt Assignment
-						// Register 2
-#define SIC_ISR			0xFFC00114	// SIC Interrupt Status
-						// register 0
-#define SIC_IWR			0xFFC0011C	// SIC Interrupt
-						// Wakeup-Enable register 0
-
-// EBIU_SDBCTL Masks
-#define EB_E			0x00000001	// Enable SDRAM
-						// external bank 0
-#define EB_SZ_16		0x00000000	// SDRAM external
-						// bank size = 16MB
-#define EB_SZ_32		0x00000002	// SDRAM external
-						// bank size = 32MB
-#define EB_SZ_64		0x00000004	// SDRAM external
-						// bank size = 64MB
-#define EB_SZ_128		0x00000006	// SDRAM external
-						// bank size = 128MB
-#define EB_CAW_8		0x00000000	// SDRAM external bank column
-						// address width = 8 bits
-#define EB_CAW_9		0x00000010	// SDRAM external bank column
-						// address width = 9 bits
-#define EB_CAW_10		0x00000020	// SDRAM external bank column
-						// address width = 9 bits
-#define EB_CAW_11		0x00000030	// SDRAM external bank column
-						// address width = 9 bits
-
-// EBIU_SDBCTL Masks
-#define EBE			0x00000001	// Enable SDRAM
-						// external bank 0
-#define EBSZ_16			0x00000000	// SDRAM external
-						// bank size = 16MB
-#define EBSZ_32			0x00000002	// SDRAM external
-						// bank size = 32MB
-#define EBSZ_64			0x00000004	// SDRAM external
-						// bank size = 64MB
-#define EBSZ_128		0x00000006	// SDRAM external
-						// bank size = 128MB
-#define EBCAW_8			0x00000000	// SDRAM external bank column
-						// address width = 8 bits
-#define EBCAW_9			0x00000010	// SDRAM external bank column
-						// address width = 9 bits
-#define EBCAW_10		0x00000020	// SDRAM external bank column
-						// address width = 9 bits
-#define EBCAW_11		0x00000030	// SDRAM external bank column
-						// address width = 9 bits
-
-// Memory DMA1 Controller registers (0xFFC0 1E80-0xFFC0 1FFF)
-#define MDMA_D0_CONFIG		0xFFC01F08	// MemDMA1 Stream 0 Destination
-						// Configuration
-#define MDMA_D0_NEXT_DESC_PTR	0xFFC01F00	// MemDMA1 Stream 0
-						// Destination Next
-						// Descriptor Ptr Reg
-#define MDMA_D0_START_ADDR	0xFFC01F04	// MemDMA1 Stream 0 Destination
-						// Start Address
-#define MDMA_D0_X_COUNT		0xFFC01F10	// MemDMA1 Stream 0 Destination
-						// Inner-Loop Count
-#define MDMA_D0_Y_COUNT		0xFFC01F18	// MemDMA1 Stream 0 Destination
-						// Outer-Loop Count
-#define MDMA_D0_X_MODIFY	0xFFC01F14	// MemDMA1 Stream 0 Dest
-						// Inner-Loop Address-Increment
-#define MDMA_D0_Y_MODIFY	0xFFC01F1C	// MemDMA1 Stream 0 Dest
-						// Outer-Loop Address-Increment
-#define MDMA_D0_CURR_DESC_PTR	0xFFC01F20	// MemDMA1 Stream 0 Dest
-						// Current Descriptor Ptr reg
-#define MDMA_D0_CURR_ADDR	0xFFC01F24	// MemDMA1 Stream 0 Destination
-						// Current Address
-#define MDMA_D0_CURR_X_COUNT	0xFFC01F30	// MemDMA1 Stream 0 Dest
-						// Current Inner-Loop Count
-#define MDMA_D0_CURR_Y_COUNT	0xFFC01F38	// MemDMA1 Stream 0 Dest
-						// Current Outer-Loop Count
-#define MDMA_D0_IRQ_STATUS	0xFFC01F28	// MemDMA1 Stream 0 Destination
-						// Interrupt/Status
-#define MDMA_D0_PERIPHERAL_MAP	0xFFC01F2C	// MemDMA1 Stream 0
-						// Destination Peripheral Map
-
-#define MDMA_S0_CONFIG		0xFFC01F48	// MemDMA1 Stream 0 Source
-						// Configuration
-#define MDMA_S0_NEXT_DESC_PTR	0xFFC01F40	// MemDMA1 Stream 0 Source
-						// Next Descriptor Ptr Reg
-#define MDMA_S0_START_ADDR	0xFFC01F44	// MemDMA1 Stream 0 Source
-						// Start Address
-#define MDMA_S0_X_COUNT		0xFFC01F50	// MemDMA1 Stream 0 Source
-						// Inner-Loop Count
-#define MDMA_S0_Y_COUNT		0xFFC01F58	// MemDMA1 Stream 0 Source
-						// Outer-Loop Count
-#define MDMA_S0_X_MODIFY	0xFFC01F54	// MemDMA1 Stream 0 Source
-						// Inner-Loop Address-Increment
-#define MDMA_S0_Y_MODIFY	0xFFC01F5C	// MemDMA1 Stream 0 Source
-						// Outer-Loop Address-Increment
-#define MDMA_S0_CURR_DESC_PTR	0xFFC01F60	// MemDMA1 Stream 0 Source
-						// Current Descriptor Ptr reg
-#define MDMA_S0_CURR_ADDR	0xFFC01F64	// MemDMA1 Stream 0 Source
-						// Current Address
-#define MDMA_S0_CURR_X_COUNT	0xFFC01F70	// MemDMA1 Stream 0 Source
-						// Current Inner-Loop Count
-#define MDMA_S0_CURR_Y_COUNT `	0xFFC01F78	// MemDMA1 Stream 0 Source
-						// Current Outer-Loop Count
-#define MDMA_S0_IRQ_STATUS	0xFFC01F68	// MemDMA1 Stream 0 Source
-						// Interrupt/Status
-#define MDMA_S0_PERIPHERAL_MAP	0xFFC01F6C	// MemDMA1 Stream 0 Source
-						// Peripheral Map
-
-#define MDMA_D1_CONFIG		0xFFC01F88	// MemDMA1 Stream 1 Destination
-						// Configuration
-#define MDMA_D1_NEXT_DESC_PTR	0xFFC01F80	// MemDMA1 Stream 1
-						// Destination Next
-						// Descriptor Ptr Reg
-#define MDMA_D1_START_ADDR	0xFFC01F84	// MemDMA1 Stream 1 Destination
-						// Start Address
-#define MDMA_D1_X_COUNT		0xFFC01F90	// MemDMA1 Stream 1 Destination
-						// Inner-Loop Count
-#define MDMA_D1_Y_COUNT		0xFFC01F98	// MemDMA1 Stream 1 Destination
-						// Outer-Loop Count
-#define MDMA_D1_X_MODIFY	0xFFC01F94	// MemDMA1 Stream 1 Dest
-						// Inner-Loop Address-Increment
-#define MDMA_D1_Y_MODIFY	0xFFC01F9C	// MemDMA1 Stream 1 Dest
-						// Outer-Loop Address-Increment
-#define MDMA_D1_CURR_DESC_PTR	0xFFC01FA0	// MemDMA1 Stream 1 Dest
-						// Current Descriptor Ptr reg
-#define MDMA_D1_CURR_ADDR	0xFFC01FA4	// MemDMA1 Stream 1 Dest
-						// Current Address
-#define MDMA_D1_CURR_X_COUNT	0xFFC01FB0	// MemDMA1 Stream 1 Dest
-						// Current Inner-Loop Count
-#define MDMA_D1_CURR_Y_COUNT	0xFFC01FB8	// MemDMA1 Stream 1 Dest
-						// Current Outer-Loop Count
-#define MDMA_D1_IRQ_STATUS	0xFFC01FA8	// MemDMA1 Stream 1 Dest
-						// Interrupt/Status
-#define MDMA_D1_PERIPHERAL_MAP	0xFFC01FAC	// MemDMA1 Stream 1 Dest
-						// Peripheral Map
-
-#define MDMA_S1_CONFIG		0xFFC01FC8	// MemDMA1 Stream 1 Source
-						// Configuration
-#define MDMA_S1_NEXT_DESC_PTR	0xFFC01FC0	// MemDMA1 Stream 1 Source
-						// Next Descriptor Ptr Reg
-#define MDMA_S1_START_ADDR	0xFFC01FC4	// MemDMA1 Stream 1 Source
-						// Start Address
-#define MDMA_S1_X_COUNT		0xFFC01FD0	// MemDMA1 Stream 1 Source
-						// Inner-Loop Count
-#define MDMA_S1_Y_COUNT		0xFFC01FD8	// MemDMA1 Stream 1 Source
-						// Outer-Loop Count
-#define MDMA_S1_X_MODIFY	0xFFC01FD4	// MemDMA1 Stream 1 Source
-						// Inner-Loop Address-Increment
-#define MDMA_S1_Y_MODIFY	0xFFC01FDC	// MemDMA1 Stream 1 Source
-						// Outer-Loop Address-Increment
-#define MDMA_S1_CURR_DESC_PTR	0xFFC01FE0	// MemDMA1 Stream 1 Source
-						// Current Descriptor Ptr reg
-#define MDMA_S1_CURR_ADDR	0xFFC01FE4	// MemDMA1 Stream 1 Source
-						// Current Address
-#define MDMA_S1_CURR_X_COUNT	0xFFC01FF0	// MemDMA1 Stream 1 Source
-						// Current Inner-Loop Count
-#define MDMA_S1_CURR_Y_COUNT	0xFFC01FF8	// MemDMA1 Stream 1 Source
-						// Current Outer-Loop Count
-#define MDMA_S1_IRQ_STATUS	0xFFC01FE8	// MemDMA1 Stream 1 Source
-						// Interrupt/Status
-#define MDMA_S1_PERIPHERAL_MAP	0xFFC01FEC	// MemDMA1 Stream 1 Source
-						// Peripheral Map
-
-#define DMA0_CONFIG		0xFFC01C08	// DMA1 Channel 0 Configuration
-						// register
-#define DMA0_NEXT_DESC_PTR	0xFFC01C00	// DMA1 Channel 0 Next
-						// Descripter Ptr Reg
-#define DMA0_START_ADDR		0xFFC01C04	// DMA1 Channel 0 Start Address
-#define DMA0_X_COUNT		0xFFC01C10	// DMA1 Channel 0 Inner Loop
-						// Count
-#define DMA0_Y_COUNT		0xFFC01C18	// DMA1 Channel 0 Outer Loop
-						// Count
-#define DMA0_X_MODIFY		0xFFC01C14	// DMA1 Channel 0 Inner Loop
-						// Addr Increment
-#define DMA0_Y_MODIFY		0xFFC01C1C	// DMA1 Channel 0 Outer Loop
-						// Addr Increment
-#define DMA0_CURR_DESC_PTR	0xFFC01C20	// DMA1 Channel 0 Current
-						// Descriptor Pointer
-#define DMA0_CURR_ADDR		0xFFC01C24	// DMA1 Channel 0 Current
-						// Address Pointer
-#define DMA0_CURR_X_COUNT	0xFFC01C30	// DMA1 Channel 0 Current Inner
-						// Loop Count
-#define DMA0_CURR_Y_COUNT	0xFFC01C38	// DMA1 Channel 0 Current Outer
-						// Loop Count
-#define DMA0_IRQ_STATUS		0xFFC01C28	// DMA1 Channel 0 Interrupt
-						// Status Register
-#define DMA0_PERIPHERAL_MAP	0xFFC01C2C	// DMA1 Channel 0 Peripheral
-						// Map Register
-
-#define DMA1_CONFIG		0xFFC00C08	// DMA2 Channel 0 Configuration
-						// register
-#define DMA1_NEXT_DESC_PTR	0xFFC00C00	// DMA2 Channel 0 Next
-						// Descripter Ptr Reg
-#define DMA1_START_ADDR		0xFFC00C04	// DMA2 Channel 0 Start Address
-#define DMA1_X_COUNT		0xFFC00C10	// DMA2 Channel 0 Inner Loop
-						// Count
-#define DMA1_Y_COUNT		0xFFC00C18	// DMA2 Channel 0 Outer Loop
-						// Count
-#define DMA1_X_MODIFY		0xFFC00C14	// DMA2 Channel 0 Inner Loop
-						// Addr Increment
-#define DMA1_Y_MODIFY		0xFFC00C1C	// DMA2 Channel 0 Outer Loop
-						// Addr Increment
-#define DMA1_CURR_DESC_PTR	0xFFC00C20	// DMA2 Channel 0 Current
-						// Descriptor Pointer
-#define DMA1_CURR_ADDR		0xFFC00C24	// DMA2 Channel 0 Current
-						// Address Pointer
-#define DMA1_CURR_X_COUNT	0xFFC00C30	// DMA2 Channel 0 Current Inner
-						// Loop Count
-#define DMA1_CURR_Y_COUNT	0xFFC00C38	// DMA2 Channel 0 Current Outer
-						// Loop Count
-#define DMA1_IRQ_STATUS		0xFFC00C28	// DMA2 Channel 0 Interrupt
-						// /Status Register
-#define DMA1_PERIPHERAL_MAP	0xFFC00C2C	// DMA2 Channel 0 Peripheral
-						// Map Register
-
-#define DMA2_CONFIG		0xFFC00C48	// DMA2 Channel 1 Configuration
-						// register
-#define DMA2_NEXT_DESC_PTR	0xFFC00C40	// DMA2 Channel 1 Next
-						// Descripter Ptr Reg
-#define DMA2_START_ADDR		0xFFC00C44	// DMA2 Channel 1 Start Address
-#define DMA2_X_COUNT		0xFFC00C50	// DMA2 Channel 1 Inner Loop
-						// Count
-#define DMA2_Y_COUNT		0xFFC00C58	// DMA2 Channel 1 Outer Loop
-						// Count
-#define DMA2_X_MODIFY		0xFFC00C54	// DMA2 Channel 1 Inner Loop
-						// Addr Increment
-#define DMA2_Y_MODIFY		0xFFC00C5C	// DMA2 Channel 1 Outer Loop
-						// Addr Increment
-#define DMA2_CURR_DESC_PTR	0xFFC00C60	// DMA2 Channel 1 Current
-						// Descriptor Pointer
-#define DMA2_CURR_ADDR		0xFFC00C64	// DMA2 Channel 1 Current
-						// Address Pointer
-#define DMA2_CURR_X_COUNT	0xFFC00C70	// DMA2 Channel 1 Current
-						// Inner Loop Count
-#define DMA2_CURR_Y_COUNT	0xFFC00C78	// DMA2 Channel 1 Current
-						// Outer Loop Count
-#define DMA2_IRQ_STATUS		0xFFC00C68	// DMA2 Channel 1 Interrupt
-						// /Status Register
-#define DMA2_PERIPHERAL_MAP	0xFFC00C6C	// DMA2 Channel 1 Peripheral
-						// Map Register
-
-#define DMA3_CONFIG		0xFFC00C88	// DMA2 Channel 2 Configuration
-						// register
-#define DMA3_NEXT_DESC_PTR	0xFFC00C80	// DMA2 Channel 2 Next
-						// Descripter Ptr Reg
-#define DMA3_START_ADDR		0xFFC00C84	// DMA2 Channel 2 Start Address
-#define DMA3_X_COUNT		0xFFC00C90	// DMA2 Channel 2 Inner Loop
-						// Count
-#define DMA3_Y_COUNT		0xFFC00C98	// DMA2 Channel 2 Outer Loop
-						// Count
-#define DMA3_X_MODIFY		0xFFC00C94	// DMA2 Channel 2 Inner Loop
-						// Addr Increment
-#define DMA3_Y_MODIFY		0xFFC00C9C	// DMA2 Channel 2 Outer Loop
-						// Addr Increment
-#define DMA3_CURR_DESC_PTR	0xFFC00CA0	// DMA2 Channel 2 Current
-						// Descriptor Pointer
-#define DMA3_CURR_ADDR		0xFFC00CA4	// DMA2 Channel 2 Current
-						// Address Pointer
-#define DMA3_CURR_X_COUNT	0xFFC00CB0	// DMA2 Channel 2 Current Inner
-						// Loop Count
-#define DMA3_CURR_Y_COUNT	0xFFC00CB8	// DMA2 Channel 2 Current Outer
-						// Loop Count
-#define DMA3_IRQ_STATUS		0xFFC00CA8	// DMA2 Channel 2 Interrupt
-						// /Status Register
-#define DMA3_PERIPHERAL_MAP	0xFFC00CAC	// DMA2 Channel 2 Peripheral
-						// Map Register
-
-#define DMA4_CONFIG		0xFFC00CC8	// DMA2 Channel 3 Configuration
-						// register
-#define DMA4_NEXT_DESC_PTR	0xFFC00CC0	// DMA2 Channel 3 Next
-						// Descripter Ptr Reg
-#define DMA4_START_ADDR		0xFFC00CC4	// DMA2 Channel 3 Start Address
-#define DMA4_X_COUNT		0xFFC00CD0	// DMA2 Channel 3 Inner Loop
-						// Count
-#define DMA4_Y_COUNT		0xFFC00CD8	// DMA2 Channel 3 Outer Loop
-						// Count
-#define DMA4_X_MODIFY		0xFFC00CD4	// DMA2 Channel 3 Inner Loop
-						// Addr Increment
-#define DMA4_Y_MODIFY		0xFFC00CDC	// DMA2 Channel 3 Outer Loop
-						// Addr Increment
-#define DMA4_CURR_DESC_PTR	0xFFC00CE0	// DMA2 Channel 3 Current
-						// Descriptor Pointer
-#define DMA4_CURR_ADDR		0xFFC00CE4	// DMA2 Channel 3 Current
-						// Address Pointer
-#define DMA4_CURR_X_COUNT	0xFFC00CF0	// DMA2 Channel 3 Current Inner
-						// Loop Count
-#define DMA4_CURR_Y_COUNT	0xFFC00CF8	// DMA2 Channel 3 Current Outer
-						// Loop Count
-#define DMA4_IRQ_STATUS		0xFFC00CE8	// DMA2 Channel 3 Interrupt
-						// /Status Register
-#define DMA4_PERIPHERAL_MAP	0xFFC00CEC	// DMA2 Channel 3 Peripheral
-						// Map Register
-
-#define DMA5_CONFIG		0xFFC00D08	// DMA2 Channel 4 Configuration
-						// register
-#define DMA5_NEXT_DESC_PTR	0xFFC00D00	// DMA2 Channel 4 Next
-						// Descripter Ptr Reg
-#define DMA5_START_ADDR		0xFFC00D04	// DMA2 Channel 4 Start Address
-#define DMA5_X_COUNT		0xFFC00D10	// DMA2 Channel 4 Inner Loop
-						// Count
-#define DMA5_Y_COUNT		0xFFC00D18	// DMA2 Channel 4 Outer Loop
-						// Count
-#define DMA5_X_MODIFY		0xFFC00D14	// DMA2 Channel 4 Inner Loop
-						// Addr Increment
-#define DMA5_Y_MODIFY		0xFFC00D1C	// DMA2 Channel 4 Outer Loop
-						// Addr Increment
-#define DMA5_CURR_DESC_PTR	0xFFC00D20	// DMA2 Channel 4 Current
-						// Descriptor Pointer
-#define DMA5_CURR_ADDR		0xFFC00D24	// DMA2 Channel 4 Current
-						// Address Pointer
-#define DMA5_CURR_X_COUNT	0xFFC00D30	// DMA2 Channel 4 Current Inner
-						// Loop Count
-#define DMA5_CURR_Y_COUNT	0xFFC00D38	// DMA2 Channel 4 Current Outer
-						// Loop Count
-#define DMA5_IRQ_STATUS		0xFFC00D28	// DMA2 Channel 4 Interrupt
-						// /Status Register
-#define DMA5_PERIPHERAL_MAP	0xFFC00D2C	// DMA2 Channel 4 Peripheral
-						// Map Register
-
-#define DMA6_CONFIG		0xFFC00D48	// DMA2 Channel 5 Configuration
-						// register
-#define DMA6_NEXT_DESC_PTR	0xFFC00D40	// DMA2 Channel 5 Next
-						// Descripter Ptr Reg
-#define DMA6_START_ADDR		0xFFC00D44	// DMA2 Channel 5 Start Address
-#define DMA6_X_COUNT		0xFFC00D50	// DMA2 Channel 5 Inner Loop
-						// Count
-#define DMA6_Y_COUNT		0xFFC00D58	// DMA2 Channel 5 Outer Loop
-						// Count
-#define DMA6_X_MODIFY		0xFFC00D54	// DMA2 Channel 5 Inner Loop
-						// Addr Increment
-#define DMA6_Y_MODIFY		0xFFC00D5C	// DMA2 Channel 5 Outer Loop
-						// Addr Increment
-#define DMA6_CURR_DESC_PTR	0xFFC00D60	// DMA2 Channel 5 Current
-						// Descriptor Pointer
-#define DMA6_CURR_ADDR		0xFFC00D64	// DMA2 Channel 5 Current
-						// Address Pointer
-#define DMA6_CURR_X_COUNT	0xFFC00D70	// DMA2 Channel 5 Current Inner
-						// Loop Count
-#define DMA6_CURR_Y_COUNT	0xFFC00D78	// DMA2 Channel 5 Current Outer
-						// Loop Count
-#define DMA6_IRQ_STATUS		0xFFC00D68	// DMA2 Channel 5 Interrupt
-						// /Status Register
-#define DMA6_PERIPHERAL_MAP	0xFFC00D6C	// DMA2 Channel 5 Peripheral
-						// Map Register
-
-#define DMA7_CONFIG		0xFFC00D88	// DMA2 Channel 6 Configuration
-						// register
-#define DMA7_NEXT_DESC_PTR	0xFFC00D80	// DMA2 Channel 6 Next
-						// Descripter Ptr Reg
-#define DMA7_START_ADDR		0xFFC00D84	// DMA2 Channel 6 Start Address
-#define DMA7_X_COUNT		0xFFC00D90	// DMA2 Channel 6 Inner Loop
-						// Count
-#define DMA7_Y_COUNT		0xFFC00D98	// DMA2 Channel 6 Outer Loop
-						// Count
-#define DMA7_X_MODIFY		0xFFC00D94	// DMA2 Channel 6 Inner Loop
-						// Addr Increment
-#define DMA7_Y_MODIFY		0xFFC00D9C	// DMA2 Channel 6 Outer Loop
-						// Addr Increment
-#define DMA7_CURR_DESC_PTR	0xFFC00DA0	// DMA2 Channel 6 Current
-						// Descriptor Pointer
-#define DMA7_CURR_ADDR		0xFFC00DA4	// DMA2 Channel 6 Current
-						// Address Pointer
-#define DMA7_CURR_X_COUNT	0xFFC00DB0	// DMA2 Channel 6 Current Inner
-						// Loop Count
-#define DMA7_CURR_Y_COUNT	0xFFC00DB8	// DMA2 Channel 6 Current Outer
-						// Loop Count
-#define DMA7_IRQ_STATUS		0xFFC00DA8	// DMA2 Channel 6 Interrupt
-						// /Status Register
-#define DMA7_PERIPHERAL_MAP	0xFFC00DAC	// DMA2 Channel 6 Peripheral
-						// Map Register
-
-#define TIMER_ENABLE 		0xFFC00680	// Timer Enable Register
-#define TIMER_DISABLE 		0xFFC00684	// Timer Disable register
-#define TIMER_STATUS 		0xFFC00688	// Timer Status register
-
-// DMAx_CONFIG, MDMA_yy_CONFIG, IMDMA_yy_CONFIG Masks
-#define WDSIZE8			0x00000000	// Word Size 8 bits
-#define WDSIZE16		0x00000004	// Word Size 16 bits
-#define WDSIZE32		0x00000008	// Word Size 32 bits
-#endif	/* comment by mhfan */
-
-#endif /* _DEF_BF561_H */
diff --git a/arch/blackfin/include/asm/cpu/defBF561_extn.h b/arch/blackfin/include/asm/cpu/defBF561_extn.h
deleted file mode 100644
index 8112c3fe1e..0000000000
--- a/arch/blackfin/include/asm/cpu/defBF561_extn.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- * defBF533_extn.h
- *
- * This file is subject to the terms and conditions of the GNU Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Non-GPL License also available as part of VisualDSP++
- *
- * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html
- *
- * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved
- *
- * This file under source code control, please send bugs or changes to:
- * dsptools.support@xxxxxxxxxx
- *
- */
-
-#ifndef _DEF_BF533_EXTN_H
-#define _DEF_BF533_EXTN_H
-
-#define OFFSET_( x )		((x) & 0x0000FFFF) /* define macro for offset */
-/* Delay inserted for PLL transition */
-#define PLL_DELAY			0x1000
-
-#define L1_ISRAM		0xFFA00000
-#define L1_ISRAM_END		0xFFA10000
-#define DATA_BANKA_SRAM		0xFF800000
-#define DATA_BANKA_SRAM_END	0xFF808000
-#define DATA_BANKB_SRAM		0xFF900000
-#define DATA_BANKB_SRAM_END	0xFF908000
-#define SYSMMR_BASE		0xFFC00000
-#define WDSIZE16		0x00000004
-
-/* Event Vector Table Address */
-#define EVT_EMULATION_ADDR	0xffe02000
-#define EVT_RESET_ADDR		0xffe02004
-#define EVT_NMI_ADDR		0xffe02008
-#define EVT_EXCEPTION_ADDR	0xffe0200c
-#define EVT_GLOBAL_INT_ENB_ADDR	0xffe02010
-#define EVT_HARDWARE_ERROR_ADDR	0xffe02014
-#define EVT_TIMER_ADDR		0xffe02018
-#define EVT_IVG7_ADDR		0xffe0201c
-#define EVT_IVG8_ADDR		0xffe02020
-#define EVT_IVG9_ADDR		0xffe02024
-#define EVT_IVG10_ADDR		0xffe02028
-#define EVT_IVG11_ADDR		0xffe0202c
-#define EVT_IVG12_ADDR		0xffe02030
-#define EVT_IVG13_ADDR		0xffe02034
-#define EVT_IVG14_ADDR		0xffe02038
-#define EVT_IVG15_ADDR		0xffe0203c
-#define EVT_OVERRIDE_ADDR	0xffe02100
-
-/* IMASK Bit values */
-#define IVG15_POS		0x00008000
-#define IVG14_POS		0x00004000
-#define IVG13_POS		0x00002000
-#define IVG12_POS		0x00001000
-#define IVG11_POS		0x00000800
-#define IVG10_POS		0x00000400
-#define IVG9_POS		0x00000200
-#define IVG8_POS		0x00000100
-#define IVG7_POS		0x00000080
-#define IVGTMR_POS		0x00000040
-#define IVGHW_POS		0x00000020
-
-#define WDOG_TMR_DISABLE	(0xAD << 4)
-#define ICTL_RST		0x00000000
-#define ICTL_NMI		0x00000002
-#define ICTL_GP			0x00000004
-#define ICTL_DISABLE		0x00000003
-
-/* Watch Dog timer values setup */
-#define WATCHDOG_DISABLE	WDOG_TMR_DISABLE | ICTL_DISABLE
-
-#endif	/* _DEF_BF533_EXTN_H */
diff --git a/arch/blackfin/include/asm/cpu/def_LPBlackfin.h b/arch/blackfin/include/asm/cpu/def_LPBlackfin.h
deleted file mode 100644
index e183b0299e..0000000000
--- a/arch/blackfin/include/asm/cpu/def_LPBlackfin.h
+++ /dev/null
@@ -1,445 +0,0 @@
-/*
- * def_LPBlackfin.h
- *
- * This file is subject to the terms and conditions of the GNU Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Non-GPL License also available as part of VisualDSP++
- *
- * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html
- *
- * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved
- *
- * This file under source code control, please send bugs or changes to:
- * dsptools.support@xxxxxxxxxx
- *
- */
-
-/* LP Blackfin CORE REGISTER BIT & ADDRESS DEFINITIONS FOR ADSP-BF532 */
-
-#ifndef _DEF_LPBLACKFIN_H
-#define _DEF_LPBLACKFIN_H
-
-/*
- * #if !defined(__ADSPLPBLACKFIN__)
- * #warning def_LPBlackfin.h should only be included for 532 compatible chips.
- * #endif
- */
-
-#define MK_BMSK_( x ) (1<<x)	/* Make a bit mask from a bit position */
-
-/*
- * System Register Bits
- */
-
-/*
- * ASTAT register
- */
-
-/* definitions of ASTAT bit positions */
-#define ASTAT_AZ_P		0x00000000	/* Result of last ALU0 or shifter operation is zero */
-#define ASTAT_AN_P		0x00000001	/* Result of last ALU0 or shifter operation is negative */
-#define ASTAT_CC_P		0x00000005	/* Condition Code, used for holding comparison results */
-#define ASTAT_AQ_P		0x00000006	/* Quotient Bit */
-#define ASTAT_RND_MOD_P		0x00000008	/* Rounding mode, set for biased, clear for unbiased */
-#define ASTAT_AC0_P		0x0000000C	/* Result of last ALU0 operation generated a carry */
-#define ASTAT_AC0_COPY_P	0x00000002	/* Result of last ALU0 operation generated a carry */
-#define ASTAT_AC1_P		0x0000000D	/* Result of last ALU1 operation generated a carry */
-#define ASTAT_AV0_P		0x00000010	/* Result of last ALU0 or MAC0 operation overflowed, sticky for MAC */
-#define ASTAT_AV0S_P		0x00000011	/* Sticky version of ASTAT_AV0  */
-#define ASTAT_AV1_P		0x00000012	/* Result of last MAC1 operation overflowed, sticky for MAC */
-#define ASTAT_AV1S_P		0x00000013	/* Sticky version of ASTAT_AV1  */
-#define ASTAT_V_P		0x00000018	/* Result of last ALU0 or MAC0 operation overflowed */
-#define ASTAT_V_COPY_P		0x00000003	/* Result of last ALU0 or MAC0 operation overflowed */
-#define ASTAT_VS_P		0x00000019	/* Sticky version of ASTAT_V */
-
-/* ** Masks */
-#define ASTAT_AZ		MK_BMSK_(ASTAT_AZ_P)	/* Result of last ALU0 or shifter operation is zero */
-#define ASTAT_AN		MK_BMSK_(ASTAT_AN_P)	/* Result of last ALU0 or shifter operation is negative */
-#define ASTAT_AC0		MK_BMSK_(ASTAT_AC0_P)	/* Result of last ALU0 operation generated a carry */
-#define ASTAT_AC0_COPY		MK_BMSK_(ASTAT_AC0_COPY_P)	/* Result of last ALU0 operation generated a carry */
-#define ASTAT_AC1		MK_BMSK_(ASTAT_AC1_P)	/* Result of last ALU0 operation generated a carry */
-#define ASTAT_AV0		MK_BMSK_(ASTAT_AV0_P)	/* Result of last ALU0 or MAC0 operation overflowed, sticky for MAC */
-#define ASTAT_AV1		MK_BMSK_(ASTAT_AV1_P)	/* Result of last MAC1 operation overflowed, sticky for MAC */
-#define ASTAT_CC		MK_BMSK_(ASTAT_CC_P)	/* Condition Code, used for holding comparison results */
-#define ASTAT_AQ		MK_BMSK_(ASTAT_AQ_P)	/* Quotient Bit */
-#define ASTAT_RND_MOD		MK_BMSK_(ASTAT_RND_MOD_P)	/* Rounding mode, set for biased, clear for unbiased */
-#define ASTAT_V			MK_BMSK_(ASTAT_V_P)	/* Overflow Bit */
-#define ASTAT_V_COPY		MK_BMSK_(ASTAT_V_COPY_P)	/* Overflow Bit */
-
-/*
- * SEQSTAT register
- */
-
-/* ** Bit Positions */
-#define SEQSTAT_EXCAUSE0_P	0x00000000	/* Last exception cause bit 0 */
-#define SEQSTAT_EXCAUSE1_P	0x00000001	/* Last exception cause bit 1 */
-#define SEQSTAT_EXCAUSE2_P	0x00000002	/* Last exception cause bit 2 */
-#define SEQSTAT_EXCAUSE3_P	0x00000003	/* Last exception cause bit 3 */
-#define SEQSTAT_EXCAUSE4_P	0x00000004	/* Last exception cause bit 4 */
-#define SEQSTAT_EXCAUSE5_P	0x00000005	/* Last exception cause bit 5 */
-#define SEQSTAT_IDLE_REQ_P	0x0000000C	/* Pending idle mode request, set by IDLE instruction */
-#define SEQSTAT_SFTRESET_P	0x0000000D	/* Indicates whether the last reset was a software reset (=1) */
-#define SEQSTAT_HWERRCAUSE0_P	0x0000000E	/* Last hw error cause bit 0 */
-#define SEQSTAT_HWERRCAUSE1_P	0x0000000F	/* Last hw error cause bit 1 */
-#define SEQSTAT_HWERRCAUSE2_P	0x00000010	/* Last hw error cause bit 2 */
-#define SEQSTAT_HWERRCAUSE3_P	0x00000011	/* Last hw error cause bit 3 */
-#define SEQSTAT_HWERRCAUSE4_P	0x00000012	/* Last hw error cause bit 4 */
-#define SEQSTAT_HWERRCAUSE5_P	0x00000013	/* Last hw error cause bit 5 */
-#define SEQSTAT_HWERRCAUSE6_P	0x00000014	/* Last hw error cause bit 6 */
-#define SEQSTAT_HWERRCAUSE7_P	0x00000015	/* Last hw error cause bit 7 */
-
-/* ** Masks */
-/* Exception cause */
-#define SEQSTAT_EXCAUSE		(MK_BMSK_(SEQSTAT_EXCAUSE0_P ) | \
-				 MK_BMSK_(SEQSTAT_EXCAUSE1_P ) | \
-				 MK_BMSK_(SEQSTAT_EXCAUSE2_P ) | \
-				 MK_BMSK_(SEQSTAT_EXCAUSE3_P ) | \
-				 MK_BMSK_(SEQSTAT_EXCAUSE4_P ) | \
-				 MK_BMSK_(SEQSTAT_EXCAUSE5_P ) | \
-				 0)
-
-/* Indicates whether the last reset was a software reset (=1) */
-#define SEQSTAT_SFTRESET	MK_BMSK_(SEQSTAT_SFTRESET_P )
-
-/* Last hw error cause */
-#define SEQSTAT_HWERRCAUSE	(MK_BMSK_(SEQSTAT_HWERRCAUSE0_P ) | \
-				 MK_BMSK_(SEQSTAT_HWERRCAUSE1_P ) | \
-				 MK_BMSK_(SEQSTAT_HWERRCAUSE2_P ) | \
-				 MK_BMSK_(SEQSTAT_HWERRCAUSE3_P ) | \
-				 MK_BMSK_(SEQSTAT_HWERRCAUSE4_P ) | \
-				 0)
-
-/*
- * SYSCFG register
- */
-
-/* ** Bit Positions */
-#define SYSCFG_SSSTEP_P		0x00000000	/* Supervisor single step, when set it forces an exception for each instruction executed */
-#define SYSCFG_CCEN_P		0x00000001	/* Enable cycle counter (=1) */
-#define SYSCFG_SNEN_P		0x00000002	/* Self nesting Interrupt Enable */
-
-/* ** Masks */
-#define SYSCFG_SSSTEP		MK_BMSK_(SYSCFG_SSSTEP_P)	/* Supervisor single step, when set it forces an exception for each instruction executed */
-#define SYSCFG_CCEN		MK_BMSK_(SYSCFG_CCEN_P)		/* Enable cycle counter (=1) */
-#define SYSCFG_SNEN		MK_BMSK_(SYSCFG_SNEN_P		/* Self Nesting Interrupt Enable */
-
-/* Backward-compatibility for typos in prior releases */
-#define SYSCFG_SSSSTEP		SYSCFG_SSSTEP
-#define SYSCFG_CCCEN		SYSCFG_CCEN
-
-/*
- * Core MMR Register Map
- */
-
-/* Data Cache & SRAM Memory  (0xFFE00000 - 0xFFE00404) */
-#define SRAM_BASE_ADDRESS	0xFFE00000	/* SRAM Base Address Register */
-#define DMEM_CONTROL		0xFFE00004	/* Data memory control */
-#define DCPLB_STATUS		0xFFE00008	/* Data Cache Programmable Look-Aside Buffer Status */
-#define DCPLB_FAULT_STATUS	0xFFE00008	/* "" (older define) */
-#define DCPLB_FAULT_ADDR	0xFFE0000C	/* Data Cache Programmable Look-Aside Buffer Fault Address */
-#define DCPLB_ADDR0		0xFFE00100	/* Data Cache Protection Lookaside Buffer 0 */
-#define DCPLB_ADDR1		0xFFE00104	/* Data Cache Protection Lookaside Buffer 1 */
-#define DCPLB_ADDR2		0xFFE00108	/* Data Cache Protection Lookaside Buffer 2 */
-#define DCPLB_ADDR3		0xFFE0010C	/* Data Cacheability Protection Lookaside Buffer 3 */
-#define DCPLB_ADDR4		0xFFE00110	/* Data Cacheability Protection Lookaside Buffer 4 */
-#define DCPLB_ADDR5		0xFFE00114	/* Data Cacheability Protection Lookaside Buffer 5 */
-#define DCPLB_ADDR6		0xFFE00118	/* Data Cacheability Protection Lookaside Buffer 6 */
-#define DCPLB_ADDR7		0xFFE0011C	/* Data Cacheability Protection Lookaside Buffer 7 */
-#define DCPLB_ADDR8		0xFFE00120	/* Data Cacheability Protection Lookaside Buffer 8 */
-#define DCPLB_ADDR9		0xFFE00124	/* Data Cacheability Protection Lookaside Buffer 9 */
-#define DCPLB_ADDR10		0xFFE00128	/* Data Cacheability Protection Lookaside Buffer 10 */
-#define DCPLB_ADDR11		0xFFE0012C	/* Data Cacheability Protection Lookaside Buffer 11 */
-#define DCPLB_ADDR12		0xFFE00130	/* Data Cacheability Protection Lookaside Buffer 12 */
-#define DCPLB_ADDR13		0xFFE00134	/* Data Cacheability Protection Lookaside Buffer 13 */
-#define DCPLB_ADDR14		0xFFE00138	/* Data Cacheability Protection Lookaside Buffer 14 */
-#define DCPLB_ADDR15		0xFFE0013C	/* Data Cacheability Protection Lookaside Buffer 15 */
-#define DCPLB_DATA0		0xFFE00200	/* Data Cache 0 Status */
-#define DCPLB_DATA1		0xFFE00204	/* Data Cache 1 Status */
-#define DCPLB_DATA2		0xFFE00208	/* Data Cache 2 Status */
-#define DCPLB_DATA3		0xFFE0020C	/* Data Cache 3 Status */
-#define DCPLB_DATA4		0xFFE00210	/* Data Cache 4 Status */
-#define DCPLB_DATA5		0xFFE00214	/* Data Cache 5 Status */
-#define DCPLB_DATA6		0xFFE00218	/* Data Cache 6 Status */
-#define DCPLB_DATA7		0xFFE0021C	/* Data Cache 7 Status */
-#define DCPLB_DATA8		0xFFE00220	/* Data Cache 8 Status */
-#define DCPLB_DATA9		0xFFE00224	/* Data Cache 9 Status */
-#define DCPLB_DATA10		0xFFE00228	/* Data Cache 10 Status */
-#define DCPLB_DATA11		0xFFE0022C	/* Data Cache 11 Status */
-#define DCPLB_DATA12		0xFFE00230	/* Data Cache 12 Status */
-#define DCPLB_DATA13		0xFFE00234	/* Data Cache 13 Status */
-#define DCPLB_DATA14		0xFFE00238	/* Data Cache 14 Status */
-#define DCPLB_DATA15		0xFFE0023C	/* Data Cache 15 Status */
-#define DTEST_COMMAND		0xFFE00300	/* Data Test Command Register */
-#define DTEST_DATA0		0xFFE00400	/* Data Test Data Register */
-#define DTEST_DATA1		0xFFE00404	/* Data Test Data Register */
-
-/* Instruction Cache & SRAM Memory  (0xFFE01004 - 0xFFE01404) */
-#define IMEM_CONTROL		0xFFE01004	/* Instruction Memory Control */
-#define ICPLB_STATUS		0xFFE01008	/* Instruction Cache miss status */
-#define CODE_FAULT_STATUS	0xFFE01008	/* "" (older define) */
-#define ICPLB_FAULT_ADDR	0xFFE0100C	/* Instruction Cache miss address */
-#define CODE_FAULT_ADDR		0xFFE0100C	/* "" (older define) */
-#define ICPLB_ADDR0		0xFFE01100	/* Instruction Cacheability Protection Lookaside Buffer 0 */
-#define ICPLB_ADDR1		0xFFE01104	/* Instruction Cacheability Protection Lookaside Buffer 1 */
-#define ICPLB_ADDR2		0xFFE01108	/* Instruction Cacheability Protection Lookaside Buffer 2 */
-#define ICPLB_ADDR3		0xFFE0110C	/* Instruction Cacheability Protection Lookaside Buffer 3 */
-#define ICPLB_ADDR4		0xFFE01110	/* Instruction Cacheability Protection Lookaside Buffer 4 */
-#define ICPLB_ADDR5		0xFFE01114	/* Instruction Cacheability Protection Lookaside Buffer 5 */
-#define ICPLB_ADDR6		0xFFE01118	/* Instruction Cacheability Protection Lookaside Buffer 6 */
-#define ICPLB_ADDR7		0xFFE0111C	/* Instruction Cacheability Protection Lookaside Buffer 7 */
-#define ICPLB_ADDR8		0xFFE01120	/* Instruction Cacheability Protection Lookaside Buffer 8 */
-#define ICPLB_ADDR9		0xFFE01124	/* Instruction Cacheability Protection Lookaside Buffer 9 */
-#define ICPLB_ADDR10		0xFFE01128	/* Instruction Cacheability Protection Lookaside Buffer 10 */
-#define ICPLB_ADDR11		0xFFE0112C	/* Instruction Cacheability Protection Lookaside Buffer 11 */
-#define ICPLB_ADDR12		0xFFE01130	/* Instruction Cacheability Protection Lookaside Buffer 12 */
-#define ICPLB_ADDR13		0xFFE01134	/* Instruction Cacheability Protection Lookaside Buffer 13 */
-#define ICPLB_ADDR14		0xFFE01138	/* Instruction Cacheability Protection Lookaside Buffer 14 */
-#define ICPLB_ADDR15		0xFFE0113C	/* Instruction Cacheability Protection Lookaside Buffer 15 */
-#define ICPLB_DATA0		0xFFE01200	/* Instruction Cache 0 Status */
-#define ICPLB_DATA1		0xFFE01204	/* Instruction Cache 1 Status */
-#define ICPLB_DATA2		0xFFE01208	/* Instruction Cache 2 Status */
-#define ICPLB_DATA3		0xFFE0120C	/* Instruction Cache 3 Status */
-#define ICPLB_DATA4		0xFFE01210	/* Instruction Cache 4 Status */
-#define ICPLB_DATA5		0xFFE01214	/* Instruction Cache 5 Status */
-#define ICPLB_DATA6		0xFFE01218	/* Instruction Cache 6 Status */
-#define ICPLB_DATA7		0xFFE0121C	/* Instruction Cache 7 Status */
-#define ICPLB_DATA8		0xFFE01220	/* Instruction Cache 8 Status */
-#define ICPLB_DATA9		0xFFE01224	/* Instruction Cache 9 Status */
-#define ICPLB_DATA10		0xFFE01228	/* Instruction Cache 10 Status */
-#define ICPLB_DATA11		0xFFE0122C	/* Instruction Cache 11 Status */
-#define ICPLB_DATA12		0xFFE01230	/* Instruction Cache 12 Status */
-#define ICPLB_DATA13		0xFFE01234	/* Instruction Cache 13 Status */
-#define ICPLB_DATA14		0xFFE01238	/* Instruction Cache 14 Status */
-#define ICPLB_DATA15		0xFFE0123C	/* Instruction Cache 15 Status */
-#define ITEST_COMMAND		0xFFE01300	/* Instruction Test Command Register */
-#define ITEST_DATA0		0xFFE01400	/* Instruction Test Data Register */
-#define ITEST_DATA1		0xFFE01404	/* Instruction Test Data Register */
-
-/* Event/Interrupt Controller Registers (0xFFE02000 - 0xFFE02110) */
-#define EVT0			0xFFE02000	/* Event Vector 0 ESR Address */
-#define EVT1			0xFFE02004	/* Event Vector 1 ESR Address */
-#define EVT2			0xFFE02008	/* Event Vector 2 ESR Address */
-#define EVT3			0xFFE0200C	/* Event Vector 3 ESR Address */
-#define EVT4			0xFFE02010	/* Event Vector 4 ESR Address */
-#define EVT5			0xFFE02014	/* Event Vector 5 ESR Address */
-#define EVT6			0xFFE02018	/* Event Vector 6 ESR Address */
-#define EVT7			0xFFE0201C	/* Event Vector 7 ESR Address */
-#define EVT8			0xFFE02020	/* Event Vector 8 ESR Address */
-#define EVT9			0xFFE02024	/* Event Vector 9 ESR Address */
-#define EVT10			0xFFE02028	/* Event Vector 10 ESR Address */
-#define EVT11			0xFFE0202C	/* Event Vector 11 ESR Address */
-#define EVT12			0xFFE02030	/* Event Vector 12 ESR Address */
-#define EVT13			0xFFE02034	/* Event Vector 13 ESR Address */
-#define EVT14			0xFFE02038	/* Event Vector 14 ESR Address */
-#define EVT15			0xFFE0203C	/* Event Vector 15 ESR Address */
-#define IMASK			0xFFE02104	/* Interrupt Mask Register */
-#define IPEND			0xFFE02108	/* Interrupt Pending Register */
-#define ILAT			0xFFE0210C	/* Interrupt Latch Register */
-#define IPRIO			0xFFE02110	/* Core Interrupt Priority Register */
-
-/* Core Timer Registers     (0xFFE03000 - 0xFFE0300C) */
-#define TCNTL			0xFFE03000	/* Core Timer Control Register */
-#define TPERIOD			0xFFE03004	/* Core Timer Period Register */
-#define TSCALE			0xFFE03008	/* Core Timer Scale Register */
-#define TCOUNT			0xFFE0300C	/* Core Timer Count Register */
-
-/* Debug/MP/Emulation Registers (0xFFE05000 - 0xFFE05008) */
-#define DSPID			0xFFE05000	/* DSP Processor ID Register for MP implementations */
-#define DBGSTAT			0xFFE05008	/* Debug Status Register */
-
-/* Trace Buffer Registers (0xFFE06000 - 0xFFE06100) */
-#define TBUFCTL			0xFFE06000	/* Trace Buffer Control Register */
-#define TBUFSTAT		0xFFE06004	/* Trace Buffer Status Register */
-#define TBUF			0xFFE06100	/* Trace Buffer */
-
-/* Watchpoint Control Registers (0xFFE07000 - 0xFFE07200) */
-#define WPIACTL			0xFFE07000	/* Watchpoint Instruction Address Control Register */
-#define WPIA0			0xFFE07040	/* Watchpoint Instruction Address Register 0 */
-#define WPIA1			0xFFE07044	/* Watchpoint Instruction Address Register 1 */
-#define WPIA2			0xFFE07048	/* Watchpoint Instruction Address Register 2 */
-#define WPIA3			0xFFE0704C	/* Watchpoint Instruction Address Register 3 */
-#define WPIA4			0xFFE07050	/* Watchpoint Instruction Address Register 4 */
-#define WPIA5			0xFFE07054	/* Watchpoint Instruction Address Register 5 */
-#define WPIACNT0		0xFFE07080	/* Watchpoint Instruction Address Count Register 0 */
-#define WPIACNT1		0xFFE07084	/* Watchpoint Instruction Address Count Register 1 */
-#define WPIACNT2		0xFFE07088	/* Watchpoint Instruction Address Count Register 2 */
-#define WPIACNT3		0xFFE0708C	/* Watchpoint Instruction Address Count Register 3 */
-#define WPIACNT4		0xFFE07090	/* Watchpoint Instruction Address Count Register 4 */
-#define WPIACNT5		0xFFE07094	/* Watchpoint Instruction Address Count Register 5 */
-#define WPDACTL			0xFFE07100	/* Watchpoint Data Address Control Register */
-#define WPDA0			0xFFE07140	/* Watchpoint Data Address Register 0 */
-#define WPDA1			0xFFE07144	/* Watchpoint Data Address Register 1 */
-#define WPDACNT0		0xFFE07180	/* Watchpoint Data Address Count Value Register 0 */
-#define WPDACNT1		0xFFE07184	/* Watchpoint Data Address Count Value Register 1 */
-#define WPSTAT			0xFFE07200	/* Watchpoint Status Register */
-
-/* Performance Monitor Registers (0xFFE08000 - 0xFFE08104) */
-#define PFCTL			0xFFE08000	/* Performance Monitor Control Register */
-#define PFCNTR0			0xFFE08100	/* Performance Monitor Counter Register 0 */
-#define PFCNTR1			0xFFE08104	/* Performance Monitor Counter Register 1 */
-
-/*
- * Core MMR Register Bits
- */
-
-/*
- * EVT registers (ILAT, IMASK, and IPEND).
- */
-
-/* ** Bit Positions */
-#define EVT_EMU_P		0x00000000	/* Emulator interrupt bit position */
-#define EVT_RST_P		0x00000001	/* Reset interrupt bit position */
-#define EVT_NMI_P		0x00000002	/* Non Maskable interrupt bit position */
-#define EVT_EVX_P		0x00000003	/* Exception bit position */
-#define EVT_IRPTEN_P		0x00000004	/* Global interrupt enable bit position */
-#define EVT_IVHW_P		0x00000005	/* Hardware Error interrupt bit position */
-#define EVT_IVTMR_P		0x00000006	/* Timer interrupt bit position */
-#define EVT_IVG7_P		0x00000007	/* IVG7 interrupt bit position */
-#define EVT_IVG8_P		0x00000008	/* IVG8 interrupt bit position */
-#define EVT_IVG9_P		0x00000009	/* IVG9 interrupt bit position */
-#define EVT_IVG10_P		0x0000000a	/* IVG10 interrupt bit position */
-#define EVT_IVG11_P		0x0000000b	/* IVG11 interrupt bit position */
-#define EVT_IVG12_P		0x0000000c	/* IVG12 interrupt bit position */
-#define EVT_IVG13_P		0x0000000d	/* IVG13 interrupt bit position */
-#define EVT_IVG14_P		0x0000000e	/* IVG14 interrupt bit position */
-#define EVT_IVG15_P		0x0000000f	/* IVG15 interrupt bit position */
-
-/* ** Masks */
-#define EVT_EMU			MK_BMSK_(EVT_EMU_P   )	/* Emulator interrupt mask */
-#define EVT_RST			MK_BMSK_(EVT_RST_P   )	/* Reset interrupt mask */
-#define EVT_NMI			MK_BMSK_(EVT_NMI_P   )	/* Non Maskable interrupt mask */
-#define EVT_EVX			MK_BMSK_(EVT_EVX_P   )	/* Exception mask */
-#define EVT_IRPTEN		MK_BMSK_(EVT_IRPTEN_P)	/* Global interrupt enable mask */
-#define EVT_IVHW		MK_BMSK_(EVT_IVHW_P  )	/* Hardware Error interrupt mask */
-#define EVT_IVTMR		MK_BMSK_(EVT_IVTMR_P )	/* Timer interrupt mask */
-#define EVT_IVG7		MK_BMSK_(EVT_IVG7_P  )	/* IVG7 interrupt mask */
-#define EVT_IVG8		MK_BMSK_(EVT_IVG8_P  )	/* IVG8 interrupt mask */
-#define EVT_IVG9		MK_BMSK_(EVT_IVG9_P  )	/* IVG9 interrupt mask */
-#define EVT_IVG10		MK_BMSK_(EVT_IVG10_P )	/* IVG10 interrupt mask */
-#define EVT_IVG11		MK_BMSK_(EVT_IVG11_P )	/* IVG11 interrupt mask */
-#define EVT_IVG12		MK_BMSK_(EVT_IVG12_P )	/* IVG12 interrupt mask */
-#define EVT_IVG13		MK_BMSK_(EVT_IVG13_P )	/* IVG13 interrupt mask */
-#define EVT_IVG14		MK_BMSK_(EVT_IVG14_P )	/* IVG14 interrupt mask */
-#define EVT_IVG15		MK_BMSK_(EVT_IVG15_P )	/* IVG15 interrupt mask */
-
-/*
- * DMEM_CONTROL Register
- */
-
-/* ** Bit Positions */
-#define ENDM_P			0x00	/* (doesn't really exist) Enable Data Memory L1 */
-#define DMCTL_ENDM_P		0x00	/* "" (older define) */
-#define DMC0_P			0x01	/* Data Memory Configuration, 00 - A SRAM, B SRAM */
-#define DMCTL_DMC0_P		0x01	/* "" (older define) */
-#define DMC1_P			0x02	/* Data Memory Configuration, 10 - A SRAM, B SRAM */
-#define DMCTL_DMC1_P		0x02	/* "" (older define) */
-#define DMC2_P			0x03	/* Data Memory Configuration, 11 - A CACHE, B CACHE */
-#define DMCTL_DMC2_P		0x03	/* "" (older define) */
-#define DCBS_P			0x04	/* L1 Data Cache Bank Select */
-#define PORT_PREF0_P		0x12	/* DAG0 Port Preference */
-#define PORT_PREF1_P		0x13	/* DAG1 Port Preference */
-
-/* ** Masks */
-#define ENDM			0x00000001	/* (doesn't really exist) Enable Data Memory L1 */
-#define ENDCPLB			0x00000002	/* Enable DCPLB */
-#define ASRAM_BSRAM		0x00000000
-#define ACACHE_BSRAM		0x00000008
-#define ACACHE_BCACHE		0x0000000C
-#define DCBS			0x00000010	/*  L1 Data Cache Bank Select */
-#define PORT_PREF0		0x00001000	/* DAG0 Port Preference */
-#define PORT_PREF1		0x00002000	/* DAG1 Port Preference */
-
-/* IMEM_CONTROL Register */
-/* ** Bit Positions */
-#define ENIM_P			0x00	/* Enable L1 Code Memory */
-#define IMCTL_ENIM_P		0x00	/* "" (older define) */
-#define ENICPLB_P		0x01	/* Enable ICPLB */
-#define IMCTL_ENICPLB_P		0x01	/* "" (older define) */
-#define IMC_P			0x02	/* Enable */
-#define IMCTL_IMC_P		0x02	/* Configure L1 code memory as cache (0=SRAM) */
-#define ILOC0_P			0x03	/* Lock Way 0 */
-#define ILOC1_P			0x04	/* Lock Way 1 */
-#define ILOC2_P			0x05	/* Lock Way 2 */
-#define ILOC3_P			0x06	/* Lock Way 3 */
-#define LRUPRIORST_P		0x0D	/* Least Recently Used Replacement Priority */
-
-/* ** Masks */
-#define ENIM			0x00000001	/* Enable L1 Code Memory */
-#define ENICPLB			0x00000002	/* Enable ICPLB */
-#define IMC			0x00000004	/* Configure L1 code memory as cache (0=SRAM) */
-#define ILOC0			0x00000008	/* Lock Way 0 */
-#define ILOC1			0x00000010	/* Lock Way 1 */
-#define ILOC2			0x00000020	/* Lock Way 2 */
-#define ILOC3			0x00000040	/* Lock Way 3 */
-#define LRUPRIORST		0x00002000	/* Least Recently Used Replacement Priority */
-
-/* TCNTL Masks */
-#define TMPWR			0x00000001	/* Timer Low Power Control, 0=low power mode, 1=active state */
-#define TMREN			0x00000002	/* Timer enable, 0=disable, 1=enable */
-#define TAUTORLD		0x00000004	/* Timer auto reload */
-#define TINT			0x00000008	/* Timer generated interrupt 0=no interrupt has been generated, 1=interrupt has been generated (sticky) */
-
-/* TCNTL Bit Positions */
-#define TMPWR_P			0x00000000	/* Timer Low Power Control, 0=low power mode, 1=active state */
-#define TMREN_P			0x00000001	/* Timer enable, 0=disable, 1=enable */
-#define TAUTORLD_P		0x00000002	/* Timer auto reload */
-#define TINT_P			0x00000003	/* Timer generated interrupt 0=no interrupt has been generated, 1=interrupt has been generated (sticky) */
-
-/* DCPLB_DATA and ICPLB_DATA Registers */
-/* ** Bit Positions */
-#define CPLB_VALID_P		0x00000000	/* 0=invalid entry, 1=valid entry */
-#define CPLB_LOCK_P		0x00000001	/* 0=entry may be replaced, 1=entry locked */
-#define CPLB_USER_RD_P		0x00000002	/* 0=no read access, 1=read access allowed (user mode) */
-
-/* ** Masks */
-#define CPLB_VALID		0x00000001	/* 0=invalid entry, 1=valid entry */
-#define CPLB_LOCK		0x00000002	/* 0=entry may be replaced, 1=entry locked */
-#define CPLB_USER_RD		0x00000004	/* 0=no read access, 1=read access allowed (user mode) */
-#define PAGE_SIZE_1KB		0x00000000	/* 1 KB page size */
-#define PAGE_SIZE_4KB		0x00010000	/* 4 KB page size */
-#define PAGE_SIZE_1MB		0x00020000	/* 1 MB page size */
-#define PAGE_SIZE_4MB		0x00030000	/* 4 MB page size */
-#define CPLB_L1SRAM		0x00000020	/* 0=SRAM mapped in L1, 0=SRAM not mapped to L1 */
-#define CPLB_PORTPRIO		0x00000200	/* 0=low priority port, 1= high priority port */
-#define CPLB_L1_CHBL		0x00001000	/* 0=non-cacheable in L1, 1=cacheable in L1 */
-
-/* ICPLB_DATA only */
-#define CPLB_LRUPRIO		0x00000100	/* 0=can be replaced by any line, 1=priority for non-replacement */
-
-/* DCPLB_DATA only */
-#define CPLB_USER_WR		0x00000008	/* 0=no write access, 0=write access allowed (user mode) */
-#define CPLB_SUPV_WR		0x00000010	/* 0=no write access, 0=write access allowed (supervisor mode) */
-#define CPLB_DIRTY		0x00000080	/* 1=dirty, 0=clean */
-#define CPLB_L1_AOW		0x00008000	/* 0=do not allocate cache lines on write-through writes */
-						/* 1= allocate cache lines on write-through writes. */
-#define CPLB_WT			0x00004000	/* 0=write-back, 1=write-through */
-
-/* ITEST_COMMAND and DTEST_COMMAND Registers */
-/* ** Masks */
-#define TEST_READ		0x00000000	/* Read Access */
-#define TEST_WRITE		0x00000002	/* Write Access */
-#define TEST_TAG		0x00000000	/* Access TAG */
-#define TEST_DATA		0x00000004	/* Access DATA */
-#define TEST_DW0		0x00000000	/* Select Double Word 0 */
-#define TEST_DW1		0x00000008	/* Select Double Word 1 */
-#define TEST_DW2		0x00000010	/* Select Double Word 2 */
-#define TEST_DW3		0x00000018	/* Select Double Word 3 */
-#define TEST_MB0		0x00000000	/* Select Mini-Bank 0 */
-#define TEST_MB1		0x00010000	/* Select Mini-Bank 1 */
-#define TEST_MB2		0x00020000	/* Select Mini-Bank 2 */
-#define TEST_MB3		0x00030000	/* Select Mini-Bank 3 */
-#define TEST_SET(x)		((x << 5) & 0x03E0)	/* Set Index 0->31 */
-#define TEST_WAY0		0x00000000	/* Access Way0 */
-#define TEST_WAY1		0x04000000	/* Access Way1 */
-
-/* ** ITEST_COMMAND only */
-#define TEST_WAY2		0x08000000	/* Access Way2 */
-#define TEST_WAY3		0x0C000000	/* Access Way3 */
-
-/* ** DTEST_COMMAND only */
-#define TEST_BNKSELA		0x00000000	/* Access SuperBank A */
-#define TEST_BNKSELB		0x00800000	/* Access SuperBank B */
-
-#endif	/* _DEF_LPBLACKFIN_H */
diff --git a/arch/blackfin/include/asm/current.h b/arch/blackfin/include/asm/current.h
deleted file mode 100644
index 0f9b60ccba..0000000000
--- a/arch/blackfin/include/asm/current.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * barebox - current.h
- *
- * Copyright (c) 2005 blackfin.uclinux.org
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef _BLACKFIN_CURRENT_H
-#define _BLACKFIN_CURRENT_H
-/*
- *	current.h
- *	(C) Copyright 2000, Lineo, David McCullough <davidm@xxxxxxxxx>
- *
- *	rather than dedicate a register (as the m68k source does), we
- *	just keep a global,  we should probably just change it all to be
- *	current and lose _current_task.
- */
-
-extern struct task_struct *_current_task;
-#define get_current()	_current_task
-#define current 	_current_task
-
-#endif
diff --git a/arch/blackfin/include/asm/dma.h b/arch/blackfin/include/asm/dma.h
deleted file mode 100644
index 27d269f491..0000000000
--- a/arch/blackfin/include/asm/dma.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/*
- * Copyright (C) 2012 by Marc Kleine-Budde <mkl@xxxxxxxxxxxxxx>
- *
- * This file is released under the GPLv2
- *
- */
-
-#ifndef __ASM_DMA_H
-#define __ASM_DMA_H
-
-/* empty */
-
-#endif /* __ASM_DMA_H */
diff --git a/arch/blackfin/include/asm/elf.h b/arch/blackfin/include/asm/elf.h
deleted file mode 100644
index 1238a826b0..0000000000
--- a/arch/blackfin/include/asm/elf.h
+++ /dev/null
@@ -1,127 +0,0 @@
-/* Changes made by  LG Soft Oct 2004*/
-
-#ifndef __ASMBFIN_ELF_H
-#define __ASMBFIN_ELF_H
-
-/*
- * ELF register definitions..
- */
-
-//#include <asm/ptrace.h>
-//#include <asm/user.h>
-
-/* Processor specific flags for the ELF header e_flags field.  */
-#define EF_BFIN_PIC		0x00000001	/* -fpic */
-#define EF_BFIN_FDPIC		0x00000002	/* -mfdpic */
-#define EF_BFIN_CODE_IN_L1	0x00000010	/* --code-in-l1 */
-#define EF_BFIN_DATA_IN_L1	0x00000020	/* --data-in-l1 */
-
-typedef unsigned long elf_greg_t;
-
-//#define ELF_NGREG (sizeof(struct user_regs_struct) / sizeof(elf_greg_t))
-//typedef elf_greg_t elf_gregset_t[ELF_NGREG];
-
-typedef struct user_bfinfp_struct elf_fpregset_t;
-/*
- * This is used to ensure we don't load something for the wrong architecture.
- */
-#define elf_check_arch(x) ((x)->e_machine == EM_BLACKFIN)
-
-#define elf_check_fdpic(x) ((x)->e_flags & EF_BFIN_FDPIC /* && !((x)->e_flags & EF_FRV_NON_PIC_RELOCS) */)
-#define elf_check_const_displacement(x) ((x)->e_flags & EF_BFIN_PIC)
-
-/* EM_BLACKFIN defined in linux/elf.h	*/
-
-/*
- * These are used to set parameters in the core dumps.
- */
-#define ELF_CLASS	ELFCLASS32
-#define ELF_DATA	ELFDATA2LSB
-#define ELF_ARCH	EM_BLACKFIN
-
-#define ELF_PLAT_INIT(_r)	_r->p1 = 0
-
-#define ELF_FDPIC_PLAT_INIT(_regs, _exec_map_addr, _interp_map_addr, _dynamic_addr)	\
-do {											\
-	_regs->r7	= 0;						\
-	_regs->p0	= _exec_map_addr;				\
-	_regs->p1	= _interp_map_addr;				\
-	_regs->p2	= _dynamic_addr;				\
-} while(0)
-
-#define USE_ELF_CORE_DUMP
-#define ELF_FDPIC_CORE_EFLAGS	EF_BFIN_FDPIC
-#define ELF_EXEC_PAGESIZE	4096
-
-#define	R_unused0	0	/* relocation type 0 is not defined */
-#define R_pcrel5m2	1	/*LSETUP part a */
-#define R_unused1	2	/* relocation type 2 is not defined */
-#define R_pcrel10	3	/* type 3, if cc jump <target>  */
-#define R_pcrel12_jump	4	/* type 4, jump <target> */
-#define R_rimm16	5	/* type 0x5, rN = <target> */
-#define R_luimm16	6	/* # 0x6, preg.l=<target> Load imm 16 to lower half */
-#define R_huimm16  	7	/* # 0x7, preg.h=<target> Load imm 16 to upper half */
-#define R_pcrel12_jump_s 8	/* # 0x8 jump.s <target> */
-#define R_pcrel24_jump_x 9	/* # 0x9 jump.x <target> */
-#define R_pcrel24       10	/* # 0xa call <target> , not expandable */
-#define R_unusedb       11	/* # 0xb not generated */
-#define R_unusedc       12	/* # 0xc  not used */
-#define R_pcrel24_jump_l 13	/*0xd jump.l <target> */
-#define R_pcrel24_call_x 14	/* 0xE, call.x <target> if <target> is above 24 bit limit call through P1 */
-#define R_var_eq_symb    15	/* 0xf, linker should treat it same as 0x12 */
-#define R_byte_data      16	/* 0x10, .byte var = symbol */
-#define R_byte2_data     17	/* 0x11, .byte2 var = symbol */
-#define R_byte4_data     18	/* 0x12, .byte4 var = symbol and .var var=symbol */
-#define R_pcrel11        19	/* 0x13, lsetup part b */
-#define R_unused14      20	/* 0x14, undefined */
-#define R_unused15       21	/* not generated by VDSP 3.5 */
-
-/* arithmetic relocations */
-#define R_push		 0xE0
-#define R_const		 0xE1
-#define R_add		 0xE2
-#define R_sub		 0xE3
-#define R_mult		 0xE4
-#define R_div		 0xE5
-#define R_mod		 0xE6
-#define R_lshift	 0xE7
-#define R_rshift	 0xE8
-#define R_and		 0xE9
-#define R_or		 0xEA
-#define R_xor		 0xEB
-#define R_land		 0xEC
-#define R_lor		 0xED
-#define R_len		 0xEE
-#define R_neg		 0xEF
-#define R_comp		 0xF0
-#define R_page		 0xF1
-#define R_hwpage	 0xF2
-#define R_addr		 0xF3
-
-/* This is the location that an ET_DYN program is loaded if exec'ed.  Typical
-   use of this is to invoke "./ld.so someprog" to test out a new version of
-   the loader.  We need to make sure that it is out of the way of the program
-   that it will "exec", and that there is sufficient room for the brk.  */
-
-#define ELF_ET_DYN_BASE         0xD0000000UL
-
-#define ELF_CORE_COPY_REGS(pr_reg, regs)	\
-        memcpy((char *) &pr_reg, (char *)regs,  \
-               sizeof(struct pt_regs));
-
-/* This yields a mask that user programs can use to figure out what
-   instruction set this cpu supports.  */
-
-#define ELF_HWCAP	(0)
-
-/* This yields a string that ld.so will use to load implementation
-   specific libraries for optimization.  This is more specific in
-   intent than poking at uname or /proc/cpuinfo.  */
-
-#define ELF_PLATFORM  (NULL)
-
-#ifdef __KERNEL__
-#define SET_PERSONALITY(ex, ibcs2) set_personality((ibcs2)?PER_SVR4:PER_LINUX)
-#endif
-
-#endif
diff --git a/arch/blackfin/include/asm/entry.h b/arch/blackfin/include/asm/entry.h
deleted file mode 100644
index e20d73fce0..0000000000
--- a/arch/blackfin/include/asm/entry.h
+++ /dev/null
@@ -1,380 +0,0 @@
-/*
- * barebox - entry.h Routines for context saving and restoring
- *
- * Copyright (c) 2005 blackfin.uclinux.org
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __BLACKFIN_ENTRY_H
-#define __BLACKFIN_ENTRY_H
-
-#include <asm/setup.h>
-#include <asm/page.h>
-
-/*
- * Stack layout in 'ret_from_exception':
- *
- */
-
-/*
- * Register %p2 is now set to the current task throughout
- * the whole kernel.
- */
-
-#ifdef __ASSEMBLY__
-
-#define	LFLUSH_I_AND_D	0x00000808
-#define	LSIGTRAP	5
-
-/* process bits for task_struct.flags */
-#define	PF_TRACESYS_OFF	3
-#define	PF_TRACESYS_BIT	5
-#define	PF_PTRACED_OFF	3
-#define	PF_PTRACED_BIT	4
-#define	PF_DTRACE_OFF	1
-#define	PF_DTRACE_BIT	5
-
-#define NEW_PT_REGS
-
-#if defined(NEW_PT_REGS)
-
-#define SAVE_ALL_INT		save_context_no_interrupts
-#define SAVE_ALL_SYS		save_context_no_interrupts
-#define SAVE_CONTEXT		save_context_with_interrupts
-
-#define RESTORE_ALL		restore_context_no_interrupts
-#define RESTORE_ALL_SYS		restore_context_no_interrupts
-#define RESTORE_CONTEXT		restore_context_with_interrupts
-
-#else
-
-#define SAVE_ALL_INT		save_all_int
-#define SAVE_ALL_SYS		save_all_sys
-#define SAVE_CONTEXT		save_context
-#define RESTORE_ALL		restore_context
-#define RESTORE_CONTEXT		restore_context
-
-#endif
-
-/*
- * Code to save processor context.
- * We even save the register which are preserved by a function call
- * - r4, r5, r6, r7, p3, p4, p5
- */
-.macro save_context_with_interrupts
-	[--sp] = R0;
-	[--sp] = ( R7:0, P5:0 );
-	[--sp] = fp;
-	[--sp] = usp;
-
-	[--sp] = i0;
-	[--sp] = i1;
-	[--sp] = i2;
-	[--sp] = i3;
-
-	[--sp] = m0;
-	[--sp] = m1;
-	[--sp] = m2;
-	[--sp] = m3;
-
-	[--sp] = l0;
-	[--sp] = l1;
-	[--sp] = l2;
-	[--sp] = l3;
-
-	[--sp] = b0;
-	[--sp] = b1;
-	[--sp] = b2;
-	[--sp] = b3;
-	[--sp] = a0.x;
-	[--sp] = a0.w;
-	[--sp] = a1.x;
-	[--sp] = a1.w;
-
-	[--sp] = LC0;
-	[--sp] = LC1;
-	[--sp] = LT0;
-	[--sp] = LT1;
-	[--sp] = LB0;
-	[--sp] = LB1;
-
-	[--sp] = ASTAT;
-
-	[--sp] = r0;	/* Skip reserved */
-	[--sp] = RETS;
-	[--sp] = RETI;
-	[--sp] = RETX;
-	[--sp] = RETN;
-	[--sp] = RETE;
-	[--sp] = SEQSTAT;
-	[--sp] = SYSCFG;
-	[--sp] = r0;	/* Skip IPEND as well. */
-.endm
-
-.macro save_context_no_interrupts
-	[--sp] = R0;
-	[--sp] = ( R7:0, P5:0 );
-	[--sp] = fp;
-	[--sp] = usp;
-
-	[--sp] = i0;
-	[--sp] = i1;
-	[--sp] = i2;
-	[--sp] = i3;
-
-	[--sp] = m0;
-	[--sp] = m1;
-	[--sp] = m2;
-	[--sp] = m3;
-
-	[--sp] = l0;
-	[--sp] = l1;
-	[--sp] = l2;
-	[--sp] = l3;
-
-	[--sp] = b0;
-	[--sp] = b1;
-	[--sp] = b2;
-	[--sp] = b3;
-	[--sp] = a0.x;
-	[--sp] = a0.w;
-	[--sp] = a1.x;
-	[--sp] = a1.w;
-
-	[--sp] = LC0;
-	[--sp] = LC1;
-	[--sp] = LT0;
-	[--sp] = LT1;
-	[--sp] = LB0;
-	[--sp] = LB1;
-
-	[--sp] = ASTAT;
-
-	[--sp] = r0;	/* Skip reserved */
-	[--sp] = RETS;
-	r0 = RETI;
-	[--sp] = r0;
-	[--sp] = RETX;
-	[--sp] = RETN;
-	[--sp] = RETE;
-	[--sp] = SEQSTAT;
-	[--sp] = SYSCFG;
-	[--sp] = r0;	/* Skip IPEND as well. */
-.endm
-
-.macro restore_context_no_interrupts
-	sp += 4;
-	SYSCFG = [sp++];
-	SEQSTAT = [sp++];
-	RETE = [sp++];
-	RETN = [sp++];
-	RETX = [sp++];
-	r0 = [sp++];
-	RETI = r0;
-	RETS = [sp++];
-
-	sp += 4;
-
-	ASTAT = [sp++];
-
-	LB1 = [sp++];
-	LB0 = [sp++];
-	LT1 = [sp++];
-	LT0 = [sp++];
-	LC1 = [sp++];
-	LC0 = [sp++];
-
-	a1.w = [sp++];
-	a1.x = [sp++];
-	a0.w = [sp++];
-	a0.x = [sp++];
-	b3 = [sp++];
-	b2 = [sp++];
-	b1 = [sp++];
-	b0 = [sp++];
-
-	l3 = [sp++];
-	l2 = [sp++];
-	l1 = [sp++];
-	l0 = [sp++];
-
-	m3 = [sp++];
-	m2 = [sp++];
-	m1 = [sp++];
-	m0 = [sp++];
-
-	i3 = [sp++];
-	i2 = [sp++];
-	i1 = [sp++];
-	i0 = [sp++];
-
-	sp += 4;
-	fp = [sp++];
-
-	( R7 : 0, P5 : 0) = [ SP ++ ];
-	sp += 4;
-.endm
-
-.macro restore_context_with_interrupts
-	sp += 4;
-	SYSCFG = [sp++];
-	SEQSTAT = [sp++];
-	RETE = [sp++];
-	RETN = [sp++];
-	RETX = [sp++];
-	RETI = [sp++];
-	RETS = [sp++];
-
-	sp += 4;
-
-	ASTAT = [sp++];
-
-	LB1 = [sp++];
-	LB0 = [sp++];
-	LT1 = [sp++];
-	LT0 = [sp++];
-	LC1 = [sp++];
-	LC0 = [sp++];
-
-	a1.w = [sp++];
-	a1.x = [sp++];
-	a0.w = [sp++];
-	a0.x = [sp++];
-	b3 = [sp++];
-	b2 = [sp++];
-	b1 = [sp++];
-	b0 = [sp++];
-
-	l3 = [sp++];
-	l2 = [sp++];
-	l1 = [sp++];
-	l0 = [sp++];
-
-	m3 = [sp++];
-	m2 = [sp++];
-	m1 = [sp++];
-	m0 = [sp++];
-
-	i3 = [sp++];
-	i2 = [sp++];
-	i1 = [sp++];
-	i0 = [sp++];
-
-	sp += 4;
-	fp = [sp++];
-
-	( R7 : 0, P5 : 0) = [ SP ++ ];
-	sp += 4;
-.endm
-
-#if !defined(NEW_PT_REGS)
-/*
- * a -1 in the orig_r0 field signifies
- * that the stack frame is NOT for syscall
- */
-.macro	save_all_int
-/* reserved and disable the single step of SYSCFG, by Steven Chen 03/07/10 */
-	[--sp] = r0;
-	r0.l = 0x30;		/* Errata for BF533 */
-	r0.h = 0x0;
-	syscfg = r0;		/* disable single step flag in SYSCFG */
-	r0 = [sp++];
-	[--sp] = syscfg;	/* store SYSCFG */
-
-	[--sp] = r0;	/* Reserved for IPEND */
-	[--sp] = fp;
-	[--sp] = usp;
-	[--sp] = r0;
-
-	[--sp] = r0;
-	r0 = [sp + 8];
-	[--sp] = a0.x;
-	[--sp] = a1.x;
-	[--sp] = a0.w;
-	[--sp] = a1.w;
-	[--sp] = rets;
-	[--sp] = astat;
-	[--sp] = seqstat;
-	[--sp] = retx;	/* current pc when exception happens */
-	[--sp] = ( r7:5, p5:0 );
-	[--sp] = r1;
-	[--sp] = r2;
-	[--sp] = r4;
-	[--sp] = r3;
-.endm
-
-.macro	save_all_sys
-	[--sp] = r0;
-	[--sp] = r0;
-	[--sp] = a0.x;
-	[--sp] = a1.x;
-	[--sp] = a0.w;
-	[--sp] = a1.w;
-	[--sp] = rets;
-	[--sp] = astat;
-	[--sp] = seqstat;
-	[--sp] = retx;	/* current pc when exception happens */
-	[--sp] = ( r7:5, p5:0 );
-	[--sp] = r1;
-	[--sp] = r2;
-	[--sp] = r4;
-	[--sp] = r3;
-.endm
-
-.macro	restore_all
-	r3 = [sp++];
-	r4 = [sp++];
-	r2 = [sp++];
-	r1 = [sp++];
-	( r7:5, p5:0 ) = [sp++];
-	retx = [sp++];
-	seqstat = [sp++];
-	astat = [sp++];
-	rets = [sp++];
-	a1.w = [sp++];
-	a0.w = [sp++];
-	a1.x = [sp++];
-	a0.x = [sp++];
-	sp += 4;	/* orig r0 */
-	r0 = [sp++];
-
-	sp += 4;
-	fp = [sp++];
-	sp +=4;		/* Skip the IPEND */
-
-	syscfg = [sp++];
-
-.endm
-
-#endif
-
-#define STR(X) 			STR1(X)
-#define STR1(X) 		#X
-
-#if defined(NEW_PT_REGS)
-
-#define PT_OFF_ORIG_R0		208
-#define PT_OFF_SR		8
-
-#else
-
-#define PT_OFF_ORIG_R0		0x54
-#define PT_OFF_SR		0x38	/* seqstat in pt_regs */
-
-#endif
-#endif
-
-#endif
diff --git a/arch/blackfin/include/asm/hw_irq.h b/arch/blackfin/include/asm/hw_irq.h
deleted file mode 100644
index 275f3e815d..0000000000
--- a/arch/blackfin/include/asm/hw_irq.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * barebox - hw_irq.h
- *
- * Copyright (c) 2005 blackfin.uclinux.org
- *
- * This file is based on
- * linux/arch/$(ARCH)/platform/$(PLATFORM)/hw_irq.h
- * BlackFin (ADI) assembler restricted values by Ted Ma <mated@xxxxxxxxxxxx>
- * Copyright (c) 2002 Arcturus Networks Inc. (www.arcturusnetworks.com)
- * Copyright (c) 2002 Lineo, Inc <mattw@xxxxxxxxx>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifdef CONFIG_EZKIT533
-#include <asm/board/bf533_irq.h>
-#endif
-#ifdef CONFIG_STAMP
-#include <asm/board/bf533_irq.h>
-#endif
diff --git a/arch/blackfin/include/asm/io.h b/arch/blackfin/include/asm/io.h
deleted file mode 100644
index 703104e1b8..0000000000
--- a/arch/blackfin/include/asm/io.h
+++ /dev/null
@@ -1,120 +0,0 @@
-/*
- * barebox - io.h IO routines
- *
- * Copyright (c) 2005 blackfin.uclinux.org
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef _BLACKFIN_IO_H
-#define _BLACKFIN_IO_H
-
-/* function prototypes for CF support */
-extern void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words);
-extern void cf_insw(unsigned short *sect_buf, unsigned short *addr, int words);
-extern unsigned char cf_inb(volatile unsigned char *addr);
-extern void cf_outb(unsigned char val, volatile unsigned char* addr);
-
-/*
- * These are for ISA/PCI shared memory _only_ and should never be used
- * on any other type of memory, including Zorro memory. They are meant to
- * access the bus in the bus byte order which is little-endian!.
- *
- * readX/writeX() are used to access memory mapped devices. On some
- * architectures the memory mapped IO stuff needs to be accessed
- * differently. On the m68k architecture, we just read/write the
- * memory location directly.
- */
-
-
-#define readb(addr)		({ unsigned char __v = (*(volatile unsigned char *) (addr));asm("ssync;"); __v; })
-#define readw(addr)		({ unsigned short __v = (*(volatile unsigned short *) (addr)); asm("ssync;");__v; })
-#define readl(addr)		({ unsigned int __v = (*(volatile unsigned int *) (addr));asm("ssync;"); __v; })
-
-#define writeb(b,addr)		{((*(volatile unsigned char *) (addr)) = (b)); asm("ssync;");}
-#define writew(b,addr)		{((*(volatile unsigned short *) (addr)) = (b)); asm("ssync;");}
-#define writel(b,addr)		{((*(volatile unsigned int *) (addr)) = (b)); asm("ssync;");}
-
-#define __raw_readb readb
-#define __raw_readw readw
-#define __raw_readl readl
-#define __raw_writeb writeb
-#define __raw_writew writew
-#define __raw_writel writel
-
-#define memset_io(a,b,c)	memset((void *)(a),(b),(c))
-#define memcpy_fromio(a,b,c)	memcpy((a),(void *)(b),(c))
-#define memcpy_toio(a,b,c)	memcpy((void *)(a),(b),(c))
-
-#define inb_p(addr)		readb((addr) + BF533_PCIIO_BASE)
-#define inb(addr)		cf_inb((volatile unsigned char*)(addr))
-
-#define outb(x,addr)		cf_outb((unsigned char)(x), (volatile unsigned char*)(addr))
-#define outb_p(x,addr)		outb(x, (addr) + BF533_PCIIO_BASE)
-
-#define inw(addr)		readw((addr) + BF533_PCIIO_BASE)
-#define inl(addr)		readl((addr) + BF533_PCIIO_BASE)
-
-#define outw(x,addr)		writew(x, (addr) + BF533_PCIIO_BASE)
-#define outl(x,addr)		writel(x, (addr) + BF533_PCIIO_BASE)
-
-#define insb(port, addr, count)	memcpy((void*)addr, (void*)(BF533_PCIIO_BASE + port), count)
-#define insw(port, addr, count)	cf_insw((unsigned short*)addr, (unsigned short*)(port), (count))
-#define insl(port, addr, count)	memcpy((void*)addr, (void*)(BF533_PCIIO_BASE + port), (4*count))
-
-#define outsb(port,addr,count)	memcpy((void*)(BF533_PCIIO_BASE + port), (void*)addr, count)
-#define outsw(port,addr,count)	cf_outsw((unsigned short*)(port), (unsigned short*)addr, (count))
-#define outsl(port,addr,count)	memcpy((void*)(BF533_PCIIO_BASE + port), (void*)addr, (4*count))
-
-#define IO_SPACE_LIMIT		0xffff
-
-/* Values for nocacheflag and cmode */
-#define IOMAP_FULL_CACHING	0
-#define IOMAP_NOCACHE_SER	1
-#define IOMAP_NOCACHE_NONSER	2
-#define IOMAP_WRITETHROUGH	3
-
-extern void *__ioremap(unsigned long physaddr, unsigned long size,
-		       int cacheflag);
-extern void __iounmap(void *addr, unsigned long size);
-
-static inline void *ioremap(unsigned long physaddr, unsigned long size)
-{
-	return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
-}
-static inline void *ioremap_nocache(unsigned long physaddr,
-				    unsigned long size)
-{
-	return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
-}
-static inline void *ioremap_writethrough(unsigned long physaddr,
-					 unsigned long size)
-{
-	return __ioremap(physaddr, size, IOMAP_WRITETHROUGH);
-}
-static inline void *ioremap_fullcache(unsigned long physaddr,
-				      unsigned long size)
-{
-	return __ioremap(physaddr, size, IOMAP_FULL_CACHING);
-}
-
-extern void iounmap(void *addr);
-
-extern void blkfin_inv_cache_all(void);
-#define dma_cache_inv(_start,_size)		do { blkfin_inv_cache_all();} while (0)
-#define dma_cache_wback(_start,_size)		do { } while (0)
-#define dma_cache_wback_inv(_start,_size)	do { blkfin_inv_cache_all();} while (0)
-
-#endif
diff --git a/arch/blackfin/include/asm/irq.h b/arch/blackfin/include/asm/irq.h
deleted file mode 100644
index 27da595425..0000000000
--- a/arch/blackfin/include/asm/irq.h
+++ /dev/null
@@ -1,8 +0,0 @@
-
-#define IRQ_EMU                 0       /* Emulation */
-#define IRQ_RST                 1       /* reset */
-#define IRQ_NMI                 2       /* Non Maskable */
-#define IRQ_EVX                 3       /* Exception */
-#define IRQ_UNUSED              4       /*  - unused interrupt */
-#define IRQ_HWERR               5       /* Hardware Error */
-#define IRQ_CORETMR             6       /* Core timer */
diff --git a/arch/blackfin/include/asm/linkage.h b/arch/blackfin/include/asm/linkage.h
deleted file mode 100644
index f7d6d47a04..0000000000
--- a/arch/blackfin/include/asm/linkage.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ASM_LINKAGE_H
-#define __ASM_LINKAGE_H
-
-#define __ALIGN .align 4
-#define __ALIGN_STR ".align 4"
-
-#endif
diff --git a/arch/blackfin/include/asm/mem_init.h b/arch/blackfin/include/asm/mem_init.h
deleted file mode 100644
index d7038ad24f..0000000000
--- a/arch/blackfin/include/asm/mem_init.h
+++ /dev/null
@@ -1,283 +0,0 @@
-/*
- * barebox - mem_init.h Header file for memory initialization
- *
- * Copyright (c) 2005 blackfin.uclinux.org
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#if ( CONFIG_MEM_MT48LC16M16A2TG_75  ||  CONFIG_MEM_MT48LC64M4A2FB_7E )
-	#if ( CONFIG_SCLK_HZ > 119402985 )
-		#define SDRAM_tRP	TRP_2
-		#define SDRAM_tRP_num	2
-		#define SDRAM_tRAS	TRAS_7
-		#define SDRAM_tRAS_num	7
-		#define SDRAM_tRCD	TRCD_2
-		#define SDRAM_tWR	TWR_2
-	#endif
-	#if ( CONFIG_SCLK_HZ > 104477612 ) && ( CONFIG_SCLK_HZ <= 119402985 )
-		#define SDRAM_tRP	TRP_2
-		#define SDRAM_tRP_num	2
-		#define SDRAM_tRAS	TRAS_6
-		#define SDRAM_tRAS_num	6
-		#define SDRAM_tRCD	TRCD_2
-		#define SDRAM_tWR	TWR_2
-	#endif
-	#if ( CONFIG_SCLK_HZ >  89552239 ) && ( CONFIG_SCLK_HZ <= 104477612 )
-		#define SDRAM_tRP	TRP_2
-		#define SDRAM_tRP_num	2
-		#define SDRAM_tRAS	TRAS_5
-		#define SDRAM_tRAS_num	5
-		#define SDRAM_tRCD	TRCD_2
-		#define SDRAM_tWR	TWR_2
-	#endif
-	#if ( CONFIG_SCLK_HZ >  74626866 ) && ( CONFIG_SCLK_HZ <=  89552239 )
-		#define SDRAM_tRP	TRP_2
-		#define SDRAM_tRP_num	2
-		#define SDRAM_tRAS	TRAS_4
-		#define SDRAM_tRAS_num	4
-		#define SDRAM_tRCD	TRCD_2
-		#define SDRAM_tWR	TWR_2
-	#endif
-	#if ( CONFIG_SCLK_HZ >  66666667 ) && ( CONFIG_SCLK_HZ <= 74626866 )
-		#define SDRAM_tRP	TRP_2
-		#define SDRAM_tRP_num	2
-		#define SDRAM_tRAS	TRAS_3
-		#define SDRAM_tRAS_num	3
-		#define SDRAM_tRCD	TRCD_2
-		#define SDRAM_tWR	TWR_2
-	#endif
-	#if ( CONFIG_SCLK_HZ >  59701493 ) && ( CONFIG_SCLK_HZ <= 66666667 )
-		#define SDRAM_tRP	TRP_1
-		#define SDRAM_tRP_num	1
-		#define SDRAM_tRAS	TRAS_4
-		#define SDRAM_tRAS_num	3
-		#define SDRAM_tRCD	TRCD_1
-		#define SDRAM_tWR	TWR_2
-	#endif
-	#if ( CONFIG_SCLK_HZ >  44776119 ) && ( CONFIG_SCLK_HZ <=  59701493 )
-		#define SDRAM_tRP	TRP_1
-		#define SDRAM_tRP_num	1
-		#define SDRAM_tRAS	TRAS_3
-		#define SDRAM_tRAS_num	3
-		#define SDRAM_tRCD	TRCD_1
-		#define SDRAM_tWR	TWR_2
-	#endif
-	#if ( CONFIG_SCLK_HZ >  29850746 ) && ( CONFIG_SCLK_HZ <=  44776119 )
-		#define SDRAM_tRP	TRP_1
-		#define SDRAM_tRP_num	1
-		#define SDRAM_tRAS	TRAS_2
-		#define SDRAM_tRAS_num	2
-		#define SDRAM_tRCD	TRCD_1
-		#define SDRAM_tWR	TWR_2
-	#endif
-	#if ( CONFIG_SCLK_HZ <=  29850746 )
-		#define SDRAM_tRP	TRP_1
-		#define SDRAM_tRP_num	1
-		#define SDRAM_tRAS	TRAS_1
-		#define SDRAM_tRAS_num	1
-		#define SDRAM_tRCD	TRCD_1
-		#define SDRAM_tWR	TWR_2
-	#endif
-#endif
-
-#if (CONFIG_MEM_MT48LC16M16A2TG_75)
-	/*SDRAM INFORMATION: */
-	#define SDRAM_Tref	64       /* Refresh period in milliseconds   */
-	#define SDRAM_NRA	8192     /* Number of row addresses in SDRAM */
-	#define SDRAM_CL	CL_3
-#endif
-
-#if (CONFIG_MEM_MT48LC64M4A2FB_7E)
-	/*SDRAM INFORMATION: */
-	#define SDRAM_Tref	64       /* Refresh period in milliseconds   */
-	#define SDRAM_NRA	8192     /* Number of row addresses in SDRAM */
-	#define SDRAM_CL	CL_2
-#endif
-
-#if ( CONFIG_MEM_SIZE == 128 )
-	#define SDRAM_SIZE	EBSZ_128
-#endif
-#if ( CONFIG_MEM_SIZE == 64 )
-	#define SDRAM_SIZE	EBSZ_64
-#endif
-#if (  CONFIG_MEM_SIZE == 32 )
-	#define SDRAM_SIZE	EBSZ_32
-#endif
-#if ( CONFIG_MEM_SIZE == 16 )
-	#define SDRAM_SIZE	EBSZ_16
-#endif
-#if ( CONFIG_MEM_ADD_WDTH == 11 )
-	#define SDRAM_WIDTH	EBCAW_11
-#endif
-#if ( CONFIG_MEM_ADD_WDTH == 10 )
-	#define SDRAM_WIDTH	EBCAW_10
-#endif
-#if ( CONFIG_MEM_ADD_WDTH == 9 )
-	#define SDRAM_WIDTH	EBCAW_9
-#endif
-#if ( CONFIG_MEM_ADD_WDTH == 8 )
-	#define SDRAM_WIDTH	EBCAW_8
-#endif
-
-#define mem_SDBCTL	SDRAM_WIDTH | SDRAM_SIZE | EBE
-
-/* Equation from section 17 (p17-46) of BF533 HRM */
-#define mem_SDRRC	((( CONFIG_SCLK_HZ / 1000) * SDRAM_Tref)  / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num)
-
-/* Enable SCLK Out */
-#define mem_SDGCTL	( SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS )
-
-#define flash_EBIU_AMBCTL_WAT	( ( CONFIG_FLASH_SPEED_BWAT * 4 )  / ( 4000000000 / CONFIG_SCLK_HZ ) ) + 1
-#define flash_EBIU_AMBCTL_RAT	( ( CONFIG_FLASH_SPEED_BRAT * 4 )  / ( 4000000000 / CONFIG_SCLK_HZ ) ) + 1
-#define flash_EBIU_AMBCTL_HT	( ( CONFIG_FLASH_SPEED_BHT  * 4 )  / ( 4000000000 / CONFIG_SCLK_HZ ) )
-#define flash_EBIU_AMBCTL_ST	( ( CONFIG_FLASH_SPEED_BST  * 4 )  / ( 4000000000 / CONFIG_SCLK_HZ ) ) + 1
-#define flash_EBIU_AMBCTL_TT	( ( CONFIG_FLASH_SPEED_BTT  * 4 )  / ( 4000000000 / CONFIG_SCLK_HZ ) ) + 1
-
-#if (flash_EBIU_AMBCTL_TT > 3 )
-	#define flash_EBIU_AMBCTL0_TT	B0TT_4
-#endif
-#if (flash_EBIU_AMBCTL_TT == 3 )
-	#define flash_EBIU_AMBCTL0_TT	B0TT_3
-#endif
-#if (flash_EBIU_AMBCTL_TT == 2 )
-	#define flash_EBIU_AMBCTL0_TT	B0TT_2
-#endif
-#if (flash_EBIU_AMBCTL_TT < 2 )
-	#define flash_EBIU_AMBCTL0_TT	B0TT_1
-#endif
-
-#if (flash_EBIU_AMBCTL_ST > 3 )
-	#define flash_EBIU_AMBCTL0_ST	B0ST_4
-#endif
-#if (flash_EBIU_AMBCTL_ST == 3 )
-	#define flash_EBIU_AMBCTL0_ST	B0ST_3
-#endif
-#if (flash_EBIU_AMBCTL_ST == 2 )
-	#define flash_EBIU_AMBCTL0_ST	B0ST_2
-#endif
-#if (flash_EBIU_AMBCTL_ST < 2 )
-	#define flash_EBIU_AMBCTL0_ST	B0ST_1
-#endif
-
-#if (flash_EBIU_AMBCTL_HT > 2 )
-	#define flash_EBIU_AMBCTL0_HT	B0HT_3
-#endif
-#if (flash_EBIU_AMBCTL_HT == 2 )
-	#define flash_EBIU_AMBCTL0_HT	B0HT_2
-#endif
-#if (flash_EBIU_AMBCTL_HT == 1 )
-	#define flash_EBIU_AMBCTL0_HT	B0HT_1
-#endif
-#if (flash_EBIU_AMBCTL_HT == 0  && CONFIG_FLASH_SPEED_BHT == 0)
-	#define flash_EBIU_AMBCTL0_HT	B0HT_0
-#endif
-#if (flash_EBIU_AMBCTL_HT == 0  && CONFIG_FLASH_SPEED_BHT != 0)
-	#define flash_EBIU_AMBCTL0_HT	B0HT_1
-#endif
-
-#if (flash_EBIU_AMBCTL_WAT > 14)
-	#define flash_EBIU_AMBCTL0_WAT	B0WAT_15
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 14)
-	#define flash_EBIU_AMBCTL0_WAT	B0WAT_14
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 13)
-	#define flash_EBIU_AMBCTL0_WAT	B0WAT_13
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 12)
-	#define flash_EBIU_AMBCTL0_WAT	B0WAT_12
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 11)
-	#define flash_EBIU_AMBCTL0_WAT	B0WAT_11
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 10)
-	#define flash_EBIU_AMBCTL0_WAT	B0WAT_10
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 9)
-	#define flash_EBIU_AMBCTL0_WAT	B0WAT_9
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 8)
-	#define flash_EBIU_AMBCTL0_WAT	B0WAT_8
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 7)
-	#define flash_EBIU_AMBCTL0_WAT	B0WAT_7
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 6)
-	#define flash_EBIU_AMBCTL0_WAT	B0WAT_6
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 5)
-	#define flash_EBIU_AMBCTL0_WAT	B0WAT_5
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 4)
-	#define flash_EBIU_AMBCTL0_WAT	B0WAT_4
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 3)
-	#define flash_EBIU_AMBCTL0_WAT	B0WAT_3
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 2)
-	#define flash_EBIU_AMBCTL0_WAT	B0WAT_2
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 1)
-	#define flash_EBIU_AMBCTL0_WAT	B0WAT_1
-#endif
-
-#if (flash_EBIU_AMBCTL_RAT > 14)
-	#define flash_EBIU_AMBCTL0_RAT	B0RAT_15
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 14)
-	#define flash_EBIU_AMBCTL0_RAT	B0RAT_14
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 13)
-	#define flash_EBIU_AMBCTL0_RAT	B0RAT_13
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 12)
-	#define flash_EBIU_AMBCTL0_RAT	B0RAT_12
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 11)
-	#define flash_EBIU_AMBCTL0_RAT	B0RAT_11
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 10)
-	#define flash_EBIU_AMBCTL0_RAT	B0RAT_10
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 9)
-	#define flash_EBIU_AMBCTL0_RAT	B0RAT_9
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 8)
-	#define flash_EBIU_AMBCTL0_RAT	B0RAT_8
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 7)
-	#define flash_EBIU_AMBCTL0_RAT	B0RAT_7
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 6)
-	#define flash_EBIU_AMBCTL0_RAT	B0RAT_6
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 5)
-	#define flash_EBIU_AMBCTL0_RAT	B0RAT_5
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 4)
-	#define flash_EBIU_AMBCTL0_RAT	B0RAT_4
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 3)
-	#define flash_EBIU_AMBCTL0_RAT	B0RAT_3
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 2)
-	#define flash_EBIU_AMBCTL0_RAT	B0RAT_2
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 1)
-	#define flash_EBIU_AMBCTL0_RAT	B0RAT_1
-#endif
-
-#define flash_EBIU_AMBCTL0	flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN
diff --git a/arch/blackfin/include/asm/mmu.h b/arch/blackfin/include/asm/mmu.h
deleted file mode 100644
index 95af871420..0000000000
--- a/arch/blackfin/include/asm/mmu.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __ASM_MMU_H
-#define __ASM_MMU_H
-
-#define MAP_ARCH_DEFAULT MAP_UNCACHED
-
-#endif /* __ASM_MMU_H */
diff --git a/arch/blackfin/include/asm/module.h b/arch/blackfin/include/asm/module.h
deleted file mode 100644
index 99c8848e68..0000000000
--- a/arch/blackfin/include/asm/module.h
+++ /dev/null
@@ -1,14 +0,0 @@
-#ifndef _ASM_BFIN_MODULE_H
-#define _ASM_BFIN_MODULE_H
-
-#define MODULE_SYMBOL_PREFIX "_"
-
-#define Elf_Shdr        Elf32_Shdr
-#define Elf_Sym         Elf32_Sym
-#define Elf_Ehdr        Elf32_Ehdr
-#define FLG_CODE_IN_L1	0x10
-#define FLG_DATA_IN_L1	0x20
-
-struct mod_arch_specific {
-};
-#endif				/* _ASM_BFIN_MODULE_H */
diff --git a/arch/blackfin/include/asm/page.h b/arch/blackfin/include/asm/page.h
deleted file mode 100644
index 320ecaaa8f..0000000000
--- a/arch/blackfin/include/asm/page.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * barebox -  page.h
- *
- * Copyright (c) 2005 blackfin.uclinux.org
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef _BLACKFIN_PAGE_H
-#define _BLACKFIN_PAGE_H
-
-#endif
diff --git a/arch/blackfin/include/asm/page_offset.h b/arch/blackfin/include/asm/page_offset.h
deleted file mode 100644
index 6668c356df..0000000000
--- a/arch/blackfin/include/asm/page_offset.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * barebox - page_offset.h
- *
- * Copyright (c) 2005 blackfin.uclinux.org
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-/* This handles the memory map.. */
-
-#ifdef CONFIG_BLACKFIN
-#define PAGE_OFFSET_RAW		0x00000000
-#endif
diff --git a/arch/blackfin/include/asm/posix_types.h b/arch/blackfin/include/asm/posix_types.h
deleted file mode 100644
index 22cae6230c..0000000000
--- a/arch/blackfin/include/asm/posix_types.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/posix_types.h>
diff --git a/arch/blackfin/include/asm/processor.h b/arch/blackfin/include/asm/processor.h
deleted file mode 100644
index f46363732a..0000000000
--- a/arch/blackfin/include/asm/processor.h
+++ /dev/null
@@ -1,161 +0,0 @@
-/*
- * barebox - processor.h
- *
- * Copyright (c) 2005 blackfin.uclinux.org
- *
- * This file is based on
- * include/asm-m68k/processor.h
- * Changes made by Akbar Hussain Lineo, Inc, May 2001 for BLACKFIN
- * Copyright (C) 1995 Hamish Macdonald
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __ASM_BLACKFIN_PROCESSOR_H
-#define __ASM_BLACKFIN_PROCESSOR_H
-
-/*
- * Default implementation of macro that returns current
- * instruction pointer ("program counter").
- */
-#define current_text_addr()	({ __label__ _l; _l: &&_l;})
-
-#include <asm/segment.h>
-#include <asm/ptrace.h>
-#include <asm/current.h>
-
-static inline unsigned long rdusp(void)
-{
-	unsigned long usp;
-
-	__asm__ __volatile__("%0 = usp;\n\t":"=da"(usp));
-	return usp;
-}
-
-static inline void wrusp(unsigned long usp)
-{
-	__asm__ __volatile__("usp = %0;\n\t"::"da"(usp));
-}
-
-/*
- * User space process size: 3.75GB. This is hardcoded into a few places,
- * so don't change it unless you know what you are doing.
- */
-#define TASK_SIZE		(0xF0000000UL)
-
-/*
- * Bus types
- */
-#define EISA_bus		0
-#define MCA_bus			0
-
-/*  There is no pc register avaliable for BLACKFIN, so we are going to get
- *  it indirectly
- */
-
-
-/*
- * if you change this structure, you must change the code and offsets
- * in m68k/machasm.S
- */
-
-struct thread_struct {
-	unsigned long ksp;	/* kernel stack pointer */
-	unsigned long usp;	/* user stack pointer */
-	unsigned short seqstat;	/* saved status register */
-	unsigned long esp0;	/* points to SR of stack frame pt_regs */
-	unsigned long pc;	/* instruction pointer */
-};
-
-#define INIT_MMAP { &init_mm, 0, 0x40000000, NULL, __pgprot(_PAGE_PRESENT|_PAGE_ACCESSED), VM_READ | VM_WRITE | VM_EXEC, 1, NULL, NULL }
-
-#define INIT_THREAD  { \
-	sizeof(init_stack) + (unsigned long) init_stack, 0, \
-	PS_S, 0\
-}
-
-/*
- * Do necessary setup to start up a newly executed thread.
- *
- * pass the data segment into user programs if it exists,
- * it can't hurt anything as far as I can tell
- */
-#define start_thread(_regs, _pc, _usp)           \
-do {                                             \
-	set_fs(USER_DS); /* reads from user space */ \
-	(_regs)->pc = (_pc);                         \
-	if (current->mm)                             \
-		(_regs)->r5 = current->mm->start_data;   \
-	(_regs)->seqstat &= ~0x0c00;                      \
-	wrusp(_usp);                                 \
-	/* Adde by HuTao, May 26, 2003 3:39PM */\
-	if ((_regs)->ipend & 0x8000) /* check whether system in supper mode - StChen */\
-		(_regs)->ipend = 0x0;\
-} while(0)
-
-/* Forward declaration, a strange C thing */
-struct task_struct;
-
-/* Free all resources held by a thread. */
-static inline void release_thread(struct task_struct *dead_task)
-{
-}
-
-extern int kernel_thread(int (*fn) (void *), void *arg,
-			 unsigned long flags);
-
-#define copy_segments(tsk, mm)		do { } while (0)
-#define release_segments(mm)		do { } while (0)
-#define forget_segments()		do { } while (0)
-
-/*
- * Free current thread data structures etc..
- */
-static inline void exit_thread(void)
-{
-}
-
-/*
- * Return saved PC of a blocked thread.
- */
-static inline unsigned long thread_saved_pc(struct thread_struct *t)
-{
-	extern void scheduling_functions_start_here(void);
-	extern void scheduling_functions_end_here(void);
-	return 0;
-}
-
-unsigned long get_wchan(struct task_struct *p);
-
-#define	KSTK_EIP(tsk)	\
-	({			\
-	unsigned long eip = 0;	 \
-	if ((tsk)->thread.esp0 > PAGE_SIZE && \
-		MAP_NR((tsk)->thread.esp0) < max_mapnr) \
-		eip = ((struct pt_regs *) (tsk)->thread.esp0)->pc; \
-	eip; })
-#define	KSTK_ESP(tsk)	((tsk) == current ? rdusp() : (tsk)->thread.usp)
-#define THREAD_SIZE	(2*PAGE_SIZE)
-
-/* Allocation and freeing of basic task resources. */
-#define alloc_task_struct() \
-	((struct task_struct *) __get_free_pages(GFP_KERNEL,1))
-#define free_task_struct(p)	free_pages((unsigned long)(p),1)
-#define get_task_struct(tsk)	atomic_inc(&mem_map[MAP_NR(tsk)].count)
-
-#define init_task		(init_task_union.task)
-#define init_stack		(init_task_union.stack)
-
-#endif
diff --git a/arch/blackfin/include/asm/ptrace.h b/arch/blackfin/include/asm/ptrace.h
deleted file mode 100644
index c064362837..0000000000
--- a/arch/blackfin/include/asm/ptrace.h
+++ /dev/null
@@ -1,265 +0,0 @@
-/*
- * barebox - ptrace.h
- *
- * Copyright (c) 2005 blackfin.uclinux.org
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef _BLACKFIN_PTRACE_H
-#define _BLACKFIN_PTRACE_H
-
-#define NEW_PT_REGS
-
-/*
- * GCC defines register number like this:
- * -----------------------------
- *       0 - 7 are data registers R0-R7
- *       8 - 15 are address registers P0-P7
- *      16 - 31 dsp registers I/B/L0 -- I/B/L3 & M0--M3
- *      32 - 33 A registers A0 & A1
- *      34 -    status register
- *
- * We follows above, except:
- *      32-33 --- Low 32-bit of A0&1
- *      34-35 --- High 8-bit of A0&1
- */
-
-#if defined(NEW_PT_REGS)
-
-#define PT_IPEND	0
-#define PT_SYSCFG	(PT_IPEND+4)
-#define PT_SEQSTAT	(PT_SYSCFG+4)
-#define PT_RETE		(PT_SEQSTAT+4)
-#define PT_RETN		(PT_RETE+4)
-#define PT_RETX		(PT_RETN+4)
-#define PT_RETI		(PT_RETX+4)
-#define PT_PC		PT_RETI
-#define PT_RETS		(PT_RETI+4)
-#define PT_RESERVED	(PT_RETS+4)
-#define PT_ASTAT	(PT_RESERVED+4)
-#define PT_LB1		(PT_ASTAT+4)
-#define PT_LB0		(PT_LB1+4)
-#define PT_LT1		(PT_LB0+4)
-#define PT_LT0		(PT_LT1+4)
-#define PT_LC1		(PT_LT0+4)
-#define PT_LC0		(PT_LC1+4)
-#define PT_A1W		(PT_LC0+4)
-#define PT_A1X		(PT_A1W+4)
-#define PT_A0W		(PT_A1X+4)
-#define PT_A0X		(PT_A0W+4)
-#define PT_B3		(PT_A0X+4)
-#define PT_B2		(PT_B3+4)
-#define PT_B1		(PT_B2+4)
-#define PT_B0		(PT_B1+4)
-#define PT_L3		(PT_B0+4)
-#define PT_L2		(PT_L3+4)
-#define PT_L1		(PT_L2+4)
-#define PT_L0		(PT_L1+4)
-#define PT_M3		(PT_L0+4)
-#define PT_M2		(PT_M3+4)
-#define PT_M1		(PT_M2+4)
-#define PT_M0		(PT_M1+4)
-#define PT_I3		(PT_M0+4)
-#define PT_I2		(PT_I3+4)
-#define PT_I1		(PT_I2+4)
-#define PT_I0		(PT_I1+4)
-#define PT_USP		(PT_I0+4)
-#define PT_FP		(PT_USP+4)
-#define PT_P5		(PT_FP+4)
-#define PT_P4		(PT_P5+4)
-#define PT_P3		(PT_P4+4)
-#define PT_P2		(PT_P3+4)
-#define PT_P1		(PT_P2+4)
-#define PT_P0		(PT_P1+4)
-#define PT_R7		(PT_P0+4)
-#define PT_R6		(PT_R7+4)
-#define PT_R5		(PT_R6+4)
-#define PT_R4		(PT_R5+4)
-#define PT_R3		(PT_R4+4)
-#define PT_R2		(PT_R3+4)
-#define PT_R1		(PT_R2+4)
-#define PT_R0		(PT_R1+4)
-#define PT_ORIG_R0	(PT_R0+4)
-#define PT_SR		PT_SEQSTAT
-
-#else
-/*
- * Here utilize blackfin : dpregs = [pregs + imm16s4]
- *                     [pregs + imm16s4] = dpregs
- * to access defferent saved reg in stack
- */
-#define PT_R3		0
-#define PT_R4		4
-#define PT_R2		8
-#define PT_R1		12
-#define PT_P5		16
-#define PT_P4		20
-#define PT_P3		24
-#define PT_P2		28
-#define PT_P1		32
-#define PT_P0		36
-#define PT_R7		40
-#define PT_R6		44
-#define PT_R5		48
-#define PT_PC		52
-#define PT_SEQSTAT	56	/* so-called SR reg */
-#define PT_SR		PT_SEQSTAT
-#define PT_ASTAT	60
-#define PT_RETS		64
-#define PT_A1w		68
-#define PT_A0w		72
-#define PT_A1x		76
-#define PT_A0x		80
-#define PT_ORIG_R0	84
-#define PT_R0		88
-#define PT_USP		92
-#define PT_FP		96
-#define PT_SP		100
-
-/* Added by HuTao, May26 2003 3:18PM */
-#define PT_IPEND	100
-
-/* Add SYSCFG register for single stepping support */
-#define PT_SYSCFG	104
-
-#endif
-
-#ifndef __ASSEMBLY__
-
-#if defined(NEW_PT_REGS)
-/* this struct defines the way the registers are stored on the
- * stack during a system call.
- */
-struct pt_regs {
-	long ipend;
-	long syscfg;
-	long seqstat;
-	long rete;
-	long retn;
-	long retx;
-	long pc;
-	long rets;
-	long reserved;
-	long astat;
-	long lb1;
-	long lb0;
-	long lt1;
-	long lt0;
-	long lc1;
-	long lc0;
-	long a1w;
-	long a1x;
-	long a0w;
-	long a0x;
-	long b3;
-	long b2;
-	long b1;
-	long b0;
-	long l3;
-	long l2;
-	long l1;
-	long l0;
-	long m3;
-	long m2;
-	long m1;
-	long m0;
-	long i3;
-	long i2;
-	long i1;
-	long i0;
-	long usp;
-	long fp;
-	long p5;
-	long p4;
-	long p3;
-	long p2;
-	long p1;
-	long p0;
-	long r7;
-	long r6;
-	long r5;
-	long r4;
-	long r3;
-	long r2;
-	long r1;
-	long r0;
-	long orig_r0;
-};
-
-#else
-/* now we don't know what regs the system call will use	*/
-struct pt_regs {
-	long r3;
-	long r4;
-	long r2;
-	long r1;
-	long p5;
-	long p4;
-	long p3;
-	long p2;
-	long p1;
-	long p0;
-	long r7;
-	long r6;
-	long r5;
-	unsigned long pc;
-	unsigned long seqstat;
-	unsigned long astat;
-	unsigned long rets;
-	long a1w;
-	long a0w;
-	long a1x;
-	long a0x;
-	long orig_r0;
-	long r0;
-	long usp;
-	long fp;
-/*
- * Added for supervisor/user mode switch.
- *
- * HuTao May26 03 3:23PM
- */
-	long ipend;
-	long syscfg;
-};
-
-#endif
-
-/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */
-#define PTRACE_GETREGS		12
-#define PTRACE_SETREGS		13	/* ptrace signal */
-
-#ifdef __KERNEL__
-
-#ifndef PS_S
-#define PS_S			(0x0c00)
-
-/* Bit 11:10 of SEQSTAT defines user/supervisor/debug mode
- *        00: user
- *        01: supervisor
- *        1x: debug
- */
-
-#define PS_M			(0x1000)	/* I am not sure why this is required here Akbar */
-#endif
-
-#define user_mode(regs)			(!((regs)->seqstat & PS_S))
-#define instruction_pointer(regs)	((regs)->pc)
-extern void show_regs(struct pt_regs *);
-
-#endif
-#endif
-#endif
diff --git a/arch/blackfin/include/asm/sections.h b/arch/blackfin/include/asm/sections.h
deleted file mode 100644
index 2b8c516038..0000000000
--- a/arch/blackfin/include/asm/sections.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/sections.h>
diff --git a/arch/blackfin/include/asm/segment.h b/arch/blackfin/include/asm/segment.h
deleted file mode 100644
index 27e47f37e3..0000000000
--- a/arch/blackfin/include/asm/segment.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * barebox - segment.h
- *
- * Copyright (c) 2005 blackfin.uclinux.org
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef _BLACKFIN_SEGMENT_H
-#define _BLACKFIN_SEGMENT_H
-
-/* define constants */
-typedef unsigned long mm_segment_t;	/* domain register */
-
-#define KERNEL_CS		0x0
-#define KERNEL_DS		0x0
-#define __KERNEL_CS		0x0
-#define __KERNEL_DS		0x0
-
-#define USER_CS			0x1
-#define USER_DS			0x1
-#define __USER_CS		0x1
-#define __USER_DS		0x1
-
-#define get_ds()		(KERNEL_DS)
-#define get_fs()		(__USER_DS)
-#define segment_eq(a,b)		((a) == (b))
-#define set_fs(val)
-
-#endif
diff --git a/arch/blackfin/include/asm/setup.h b/arch/blackfin/include/asm/setup.h
deleted file mode 100644
index 1cc8bfbf9b..0000000000
--- a/arch/blackfin/include/asm/setup.h
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * barebox - setup.h
- *
- * Copyright (c) 2005 blackfin.uclinux.org
- *
- * This file is based on
- * asm/setup.h -- Definition of the Linux/Blackfin setup information
- * Copyright Lineo, Inc 2001 Tony Kou
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef _BLACKFIN_SETUP_H
-#define _BLACKFIN_SETUP_H
-
-/*
- * Linux/Blackfin Architectures
- */
-
-#define MACH_BFIN	1
-
-#ifdef __KERNEL__
-
-#ifndef __ASSEMBLY__
-extern unsigned long blackfin_machtype;
-#endif
-
-#if defined(CONFIG_BFIN)
-#define MACH_IS_BFIN (blackfin_machtype == MACH_BFIN)
-#endif
-
-#ifndef MACH_TYPE
-#define MACH_TYPE (blackfin_machtype)
-#endif
-
-#endif
-
-/*
- * CPU, FPU and MMU types
- *
- * Note: we don't need now:
- *
- */
-
-#ifndef __ASSEMBLY__
-extern unsigned long blackfin_cputype;
-#ifdef CONFIG_VME
-extern unsigned long vme_brdtype;
-#endif
-
-/*
- *  Miscellaneous
- */
-
-#define NUM_MEMINFO	4
-#define CL_SIZE		256
-
-extern int blackfin_num_memory;	/* # of memory blocks found (and used) */
-extern int blackfin_realnum_memory;	/* real # of memory blocks found */
-
-struct mem_info {
-	unsigned long addr;	/* physical address of memory chunk */
-	unsigned long size;	/* length of memory chunk (in bytes) */
-};
-
-extern struct mem_info blackfin_memory[NUM_MEMINFO];	/* memory description */
-
-#endif
-
-#endif
diff --git a/arch/blackfin/include/asm/string.h b/arch/blackfin/include/asm/string.h
deleted file mode 100644
index 1dc4a50517..0000000000
--- a/arch/blackfin/include/asm/string.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * barebox - string.h String functions
- *
- * Copyright (c) 2005 blackfin.uclinux.org
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-/* Changed by Lineo Inc. May 2001 */
-
-#ifndef _BLACKFINNOMMU_STRING_H_
-#define _BLACKFINNOMMU_STRING_H_
-
-#endif				/* _BLACKFIN_STRING_H_ */
diff --git a/arch/blackfin/include/asm/swab.h b/arch/blackfin/include/asm/swab.h
deleted file mode 100644
index 1f645db374..0000000000
--- a/arch/blackfin/include/asm/swab.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * Copyright 2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BLACKFIN_SWAB_H
-#define _BLACKFIN_SWAB_H
-
-#include <linux/types.h>
-#include <asm-generic/swab.h>
-
-#ifdef __GNUC__
-
-static inline __attribute_const__ __u32 __arch_swahb32(__u32 xx)
-{
-	__u32 tmp;
-	__asm__("%1 = %0 >> 8 (V);\n\t"
-		"%0 = %0 << 8 (V);\n\t"
-		"%0 = %0 | %1;\n\t"
-		: "+d"(xx), "=&d"(tmp));
-	return xx;
-}
-#define __arch_swahb32 __arch_swahb32
-
-static inline __attribute_const__ __u32 __arch_swahw32(__u32 xx)
-{
-	__u32 rv;
-	__asm__("%0 = PACK(%1.L, %1.H);\n\t": "=d"(rv): "d"(xx));
-	return rv;
-}
-#define __arch_swahw32 __arch_swahw32
-
-static inline __attribute_const__ __u32 __arch_swab32(__u32 xx)
-{
-	return __arch_swahb32(__arch_swahw32(xx));
-}
-#define __arch_swab32 __arch_swab32
-
-static inline __attribute_const__ __u16 __arch_swab16(__u16 xx)
-{
-	__u32 xw = xx;
-	__asm__("%0 <<= 8;\n	%0.L = %0.L + %0.H (NS);\n": "+d"(xw));
-	return (__u16)xw;
-}
-#define __arch_swab16 __arch_swab16
-
-#endif /* __GNUC__ */
-
-#endif				/* _BLACKFIN_SWAB_H */
diff --git a/arch/blackfin/include/asm/system.h b/arch/blackfin/include/asm/system.h
deleted file mode 100644
index f11dd4ebf1..0000000000
--- a/arch/blackfin/include/asm/system.h
+++ /dev/null
@@ -1,177 +0,0 @@
-/*
- * barebox - system.h
- *
- * Copyright (c) 2005 blackfin.uclinux.org
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef _BLACKFIN_SYSTEM_H
-#define _BLACKFIN_SYSTEM_H
-
-#include <linux/linkage.h>
-#include <asm/blackfin.h>
-#include <asm/segment.h>
-#include <asm/entry.h>
-
-#define prepare_to_switch()	do { } while(0)
-
-/*
- * switch_to(n) should switch tasks to task ptr, first checking that
- * ptr isn't the current task, in which case it does nothing.  This
- * also clears the TS-flag if the task we switched to has used the
- * math co-processor latest.
- *
- * 05/25/01 - Tony Kou (tonyko@xxxxxxxx)
- *
- * Adapted for BlackFin (ADI) by Ted Ma, Metrowerks, and Motorola GSG
- * Copyright (c) 2002 Arcturus Networks Inc. (www.arcturusnetworks.com)
- * Copyright (c) 2003 Metrowerks (www.metrowerks.com)
- */
-
-asmlinkage void resume(void);
-
-#define switch_to(prev,next,last)	{					\
-	void *_last;								\
-	__asm__ __volatile__(							\
-  			"r0 = %1;\n\t"						\
-			"r1 = %2;\n\t"						\
-			"call resume;\n\t" 					\
-			"%0 = r0;\n\t"						\
-			: "=d" (_last)						\
-			: "d" (prev),						\
-			"d" (next)						\
-			: "CC", "R0", "R1", "R2", "R3", "R4", "R5", "P0", "P1");\
-			(last) = _last;						\
-}
-
-/* Force kerenl switch to user mode -- Steven Chen */
-#define switch_to_user_mode()	{						\
-	__asm__ __volatile__(							\
-			"call kernel_to_user_mode;\n\t"				\
-			::							\
-			: "CC", "R0", "R1", "R2", "R3", "R4", "R5", "P0", "P1");\
-}
-
-/*
- * Interrupt configuring macros.
- */
-
-extern int irq_flags;
-
-#define __sti()	{			\
-	__asm__ __volatile__ (		\
-		"r3 = %0;"		\
-		"sti r3;"		\
-		::"m"(irq_flags):"R3");	\
-}
-
-#define __cli()	{			\
-	__asm__ __volatile__ (		\
-		"cli r3;"		\
-		:::"R3");		\
-}
-
-#define __save_flags(x)	{		\
-	__asm__ __volatile__ (		\
-		"cli r3;"		\
-		"%0 = r3;"		\
-		"sti r3;"		\
-		::"m"(x):"R3");		\
-}
-
-#define __save_and_cli(x)	{	\
-	__asm__ __volatile__ (          \
-		"cli r3;"		\
-		"%0 = r3;"		\
-		::"m"(x):"R3");		\
-}
-
-#define __restore_flags(x) {		\
-	__asm__ __volatile__ (		\
-		"r3 = %0;"		\
-		"sti r3;"		\
-		::"m"(x):"R3");		\
-}
-
-/* For spinlocks etc */
-#define local_irq_save(x)	__save_and_cli(x)
-#define local_irq_restore(x)	__restore_flags(x)
-#define local_irq_disable()	__cli()
-#define local_irq_enable()	__sti()
-
-#define cli()			__cli()
-#define sti()			__sti()
-#define save_flags(x)		__save_flags(x)
-#define restore_flags(x)	__restore_flags(x)
-#define save_and_cli(x)		__save_and_cli(x)
-
-/*
- * Force strict CPU ordering.
- */
-#define nop()			asm volatile ("nop;\n\t"::)
-#define mb()			asm volatile (""   : : :"memory")
-#define rmb()			asm volatile (""   : : :"memory")
-#define wmb()			asm volatile (""   : : :"memory")
-#define set_rmb(var, value)	do { xchg(&var, value); } while (0)
-#define set_mb(var, value)	set_rmb(var, value)
-#define set_wmb(var, value)	do { var = value; wmb(); } while (0)
-
-#ifdef CONFIG_SMP
-#define smp_mb()		mb()
-#define smp_rmb()		rmb()
-#define smp_wmb()		wmb()
-#else
-#define smp_mb()		barrier()
-#define smp_rmb()		barrier()
-#define smp_wmb()		barrier()
-#endif
-
-#define xchg(ptr,x)		((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
-#define tas(ptr)		(xchg((ptr),1))
-
-struct __xchg_dummy {
-	unsigned long a[100];
-};
-#define __xg(x)			((volatile struct __xchg_dummy *)(x))
-
-static inline unsigned long __xchg(unsigned long x, volatile void *ptr,
-				   int size)
-{
-	unsigned long tmp;
-	unsigned long flags = 0;
-
-	save_and_cli(flags);
-
-	switch (size) {
-	case 1:
-	      __asm__ __volatile__("%0 = %2;\n\t" "%2 = %1;\n\t": "=&d"(tmp): "d"(x), "m"(*__xg(ptr)):"memory");
-		break;
-	case 2:
-	      __asm__ __volatile__("%0 = %2;\n\t" "%2 = %1;\n\t": "=&d"(tmp): "d"(x), "m"(*__xg(ptr)):"memory");
-		break;
-	case 4:
-	      __asm__ __volatile__("%0 = %2;\n\t" "%2 = %1;\n\t": "=&d"(tmp): "d"(x), "m"(*__xg(ptr)):"memory");
-		break;
-	}
-	restore_flags(flags);
-	return tmp;
-}
-
-/* Depend on whether Blackfin has hard reset function */
-/* YES it does, but it is tricky to implement - FIXME later ...MaTed--- */
-#define HARD_RESET_NOW() ({})
-
-#endif	/* _BLACKFIN_SYSTEM_H */
diff --git a/arch/blackfin/include/asm/traps.h b/arch/blackfin/include/asm/traps.h
deleted file mode 100644
index 4415a30841..0000000000
--- a/arch/blackfin/include/asm/traps.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * barebox - traps.h
- *
- * Copyright (c) 2005 blackfin.uclinux.org
- *
- * This file is based on
- * linux/include/asm/traps.h
- * Copyright (C) 1993        Hamish Macdonald
- * Lineo, Inc    Jul 2001    Tony Kou
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef _BLACKFIN_TRAPS_H
-#define _BLACKFIN_TRAPS_H
-
-#define VEC_SYS		(0)
-#define VEC_EXCPT01	(1)
-#define VEC_EXCPT02	(2)
-#define VEC_EXCPT03	(3)
-#define VEC_EXCPT04	(4)
-#define VEC_EXCPT05	(5)
-#define VEC_EXCPT06	(6)
-#define VEC_EXCPT07	(7)
-#define VEC_EXCPT08	(8)
-#define VEC_EXCPT09	(9)
-#define VEC_EXCPT10	(10)
-#define VEC_EXCPT11	(11)
-#define VEC_EXCPT12	(12)
-#define VEC_EXCPT13	(13)
-#define VEC_EXCPT14	(14)
-#define VEC_EXCPT15	(15)
-#define VEC_STEP	(16)
-#define VEC_OVFLOW	(17)
-#define VEC_UNDEF_I	(33)
-#define VEC_ILGAL_I	(34)
-#define VEC_CPLB_VL	(35)
-#define VEC_MISALI_D	(36)
-#define VEC_UNCOV	(37)
-#define VEC_CPLB_M	(38)
-#define VEC_CPLB_MHIT	(39)
-#define VEC_WATCH	(40)
-#define VEC_ISTRU_VL	(41)
-#define VEC_MISALI_I	(42)
-#define VEC_CPLB_I_VL	(43)
-#define VEC_CPLB_I_M	(44)
-#define VEC_CPLB_I_MHIT	(45)
-#define VEC_ILL_RES	(46)	/* including unvalid supervisor mode insn */
-
-#define VECOFF(vec)	((vec)<<2)
-
-#ifndef __ASSEMBLY__
-
-/* Status register bits */
-#define PS_T  (0x8000)
-#define PS_S  (0x0c00)		/*  Supervisor mode = 0b01      */
-#define PS_D  (0x0c00)		/*  Debug mode = 0b1x           */
-#define PS_M  (0x1000)
-#define PS_C  (0x0001)
-
-#endif
-#endif
diff --git a/arch/blackfin/include/asm/types.h b/arch/blackfin/include/asm/types.h
deleted file mode 100644
index 086da34d7f..0000000000
--- a/arch/blackfin/include/asm/types.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- * barebox - types.h
- *
- * Copyright (c) 2005 blackfin.uclinux.org
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef _BLACKFIN_TYPES_H
-#define _BLACKFIN_TYPES_H
-
-/*
- * This file is never included by application software unless
- * explicitly requested (e.g., via linux/types.h) in which case the
- * application is Linux specific so (user-) name space pollution is
- * not a major issue.  However, for interoperability, libraries still
- * need to be careful to avoid a name clashes.
- */
-#ifndef __ASSEMBLY__
-
-/*
- * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the
- * header files exported to user space
- */
-
-typedef __signed__ char __s8;
-typedef unsigned char __u8;
-
-typedef __signed__ short __s16;
-typedef unsigned short __u16;
-
-typedef __signed__ int __s32;
-typedef unsigned int __u32;
-
-/* HK0617   -- Changes to unsigned long temporarily */
-#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
-typedef __signed__ long long __s64;
-typedef unsigned long long __u64;
-#endif
-
-/*
- * These aren't exported outside the kernel to avoid name space clashes
- */
-#ifdef __KERNEL__
-
-typedef signed char s8;
-typedef unsigned char u8;
-
-typedef signed short s16;
-typedef unsigned short u16;
-
-typedef signed int s32;
-typedef unsigned int u32;
-
-typedef signed long long s64;
-typedef unsigned long long u64;
-
-#endif
-
-#endif /* __ASSEMBLY__ */
-
-#include <asm/bitsperlong.h>
-
-#endif
diff --git a/arch/blackfin/include/asm/unaligned.h b/arch/blackfin/include/asm/unaligned.h
deleted file mode 100644
index 0f6c0987f2..0000000000
--- a/arch/blackfin/include/asm/unaligned.h
+++ /dev/null
@@ -1,11 +0,0 @@
-#ifndef _ASM_BLACKFIN_UNALIGNED_H
-#define _ASM_BLACKFIN_UNALIGNED_H
-
-#include <linux/unaligned/le_struct.h>
-#include <linux/unaligned/be_byteshift.h>
-#include <linux/unaligned/generic.h>
-
-#define get_unaligned __get_unaligned_le
-#define put_unaligned __put_unaligned_le
-
-#endif /* _ASM_BLACKFIN_UNALIGNED_H */
diff --git a/arch/blackfin/lib/Makefile b/arch/blackfin/lib/Makefile
deleted file mode 100644
index cefb4dc89f..0000000000
--- a/arch/blackfin/lib/Makefile
+++ /dev/null
@@ -1,18 +0,0 @@
-obj-y += blackfin_linux.o
-obj-y += board.o
-obj-y += clock.o
-obj-y += muldi3.o
-obj-y += udivsi3.o
-obj-y += umulsi3_highpart.o
-obj-y += smulsi3_highpart.o
-obj-y += umodsi3.o
-obj-y += lshrdi3.o
-obj-y += ashldi3.o
-obj-y += ashrdi3.o
-obj-y += divsi3.o
-obj-y += modsi3.o
-obj-y += cpu.o
-obj-y += flush.o
-obj-y += interrupt.o
-obj-y += traps.o
-obj-$(CONFIG_MODULES) += module.o
diff --git a/arch/blackfin/lib/ashldi3.c b/arch/blackfin/lib/ashldi3.c
deleted file mode 100644
index 1b8c4c2efb..0000000000
--- a/arch/blackfin/lib/ashldi3.c
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * File:         arch/blackfin/lib/ashldi3.c
- * Based on:
- * Author:
- *
- * Created:
- * Description:
- *
- * Rev:          $Id: ashldi3.c 2775 2007-02-21 13:58:44Z hennerich $
- *
- * Modified:
- *               Copyright 2004-2006 Analog Devices Inc.
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include "gcclib.h"
-
-#ifdef CONFIG_ARITHMETIC_OPS_L1
-DItype __ashldi3(DItype u, word_type b)__attribute__((l1_text));
-#endif
-
-DItype __ashldi3(DItype u, word_type b)
-{
-	DIunion w;
-	word_type bm;
-	DIunion uu;
-
-	if (b == 0)
-		return u;
-
-	uu.ll = u;
-
-	bm = (sizeof(SItype) * BITS_PER_UNIT) - b;
-	if (bm <= 0) {
-		w.s.low = 0;
-		w.s.high = (USItype) uu.s.low << -bm;
-	} else {
-		USItype carries = (USItype) uu.s.low >> bm;
-		w.s.low = (USItype) uu.s.low << b;
-		w.s.high = ((USItype) uu.s.high << b) | carries;
-	}
-
-	return w.ll;
-}
diff --git a/arch/blackfin/lib/ashrdi3.c b/arch/blackfin/lib/ashrdi3.c
deleted file mode 100644
index b5b351e82e..0000000000
--- a/arch/blackfin/lib/ashrdi3.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include "gcclib.h"
-
-#ifdef CONFIG_ARITHMETIC_OPS_L1
-DItype __ashrdi3(DItype u, word_type b)__attribute__((l1_text));
-#endif
-
-DItype __ashrdi3(DItype u, word_type b)
-{
-	DIunion w;
-	word_type bm;
-	DIunion uu;
-
-	if (b == 0)
-		return u;
-
-	uu.ll = u;
-
-	bm = (sizeof(SItype) * BITS_PER_UNIT) - b;
-	if (bm <= 0) {
-		/* w.s.high = 1..1 or 0..0 */
-		w.s.high = uu.s.high >> (sizeof(SItype) * BITS_PER_UNIT - 1);
-		w.s.low = uu.s.high >> -bm;
-	} else {
-		USItype carries = (USItype) uu.s.high << bm;
-		w.s.high = uu.s.high >> b;
-		w.s.low = ((USItype) uu.s.low >> b) | carries;
-	}
-
-	return w.ll;
-}
diff --git a/arch/blackfin/lib/asm-offsets.c b/arch/blackfin/lib/asm-offsets.c
deleted file mode 100644
index 9003c736ff..0000000000
--- a/arch/blackfin/lib/asm-offsets.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/*
- * generate definitions needed by assembly language modules
- *
- * Licensed under the GPL-2 or later
- */
-
-#include <linux/kbuild.h>
-
-int main(void)
-{
-	return 0;
-}
diff --git a/arch/blackfin/lib/bf533_string.c b/arch/blackfin/lib/bf533_string.c
deleted file mode 100644
index 860ee921c8..0000000000
--- a/arch/blackfin/lib/bf533_string.c
+++ /dev/null
@@ -1,181 +0,0 @@
-/*
- * barebox - bf533_string.c Contains library routines.
- *
- * Copyright (c) 2005 blackfin.uclinux.org
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@xxxxxxx.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <common.h>
-#include <asm/setup.h>
-#include <asm/page.h>
-#include <asm/cpu/defBF533.h>
-
-void *dma_memcpy(void *,const void *,size_t);
-
-char *strcpy(char *dest, const char *src)
-{
-	char *xdest = dest;
-	char temp = 0;
-
-	__asm__ __volatile__
-		("1:\t%2 = B [%1++] (Z);\n\t"
-		"B [%0++] = %2;\n\t"
-		"CC = %2;\n\t"
-		"if cc jump 1b (bp);\n":"=a"(dest), "=a"(src), "=d"(temp)
-		:"0"(dest), "1"(src), "2"(temp):"memory");
-
-	return xdest;
-}
-
-char *strncpy(char *dest, const char *src, size_t n)
-{
-	char *xdest = dest;
-	char temp = 0;
-
-	if (n == 0)
-		return xdest;
-
-	__asm__ __volatile__
-		("1:\t%3 = B [%1++] (Z);\n\t"
-		"B [%0++] = %3;\n\t"
-		"CC = %3;\n\t"
-		"if ! cc jump 2f;\n\t"
-		"%2 += -1;\n\t"
-		"CC = %2 == 0;\n\t"
-		"if ! cc jump 1b (bp);\n"
-		"2:\n":"=a"(dest), "=a"(src), "=da"(n), "=d"(temp)
-		:"0"(dest), "1"(src), "2"(n), "3"(temp)
-		:"memory");
-
-	return xdest;
-}
-
-int strcmp(const char *cs, const char *ct)
-{
-	char __res1, __res2;
-
-	__asm__
-		("1:\t%2 = B[%0++] (Z);\n\t"	/* get *cs */
-		"%3 = B[%1++] (Z);\n\t"		/* get *ct */
-		"CC = %2 == %3;\n\t"		/* compare a byte */
-		"if ! cc jump 2f;\n\t"		/* not equal, break out */
-		"CC = %2;\n\t"			/* at end of cs? */
-		"if cc jump 1b (bp);\n\t"	/* no, keep going */
-		"jump.s 3f;\n"			/* strings are equal */
-		"2:\t%2 = %2 - %3;\n"		/* *cs - *ct */
-		"3:\n":	"=a"(cs), "=a"(ct), "=d"(__res1),
-		"=d"(__res2)
-		: "0"(cs), "1"(ct));
-
-	return __res1;
-}
-
-int strncmp(const char *cs, const char *ct, size_t count)
-{
-	char __res1, __res2;
-
-	if (!count)
-		return 0;
-
-	__asm__
-		("1:\t%3 = B[%0++] (Z);\n\t"	/* get *cs */
-		"%4 = B[%1++] (Z);\n\t"		/* get *ct */
-		"CC = %3 == %4;\n\t"		/* compare a byte */
-		"if ! cc jump 3f;\n\t"		/* not equal, break out */
-		"CC = %3;\n\t"			/* at end of cs? */
-		"if ! cc jump 4f;\n\t"		/* yes, all done */
-		"%2 += -1;\n\t"			/* no, adjust count */
-		"CC = %2 == 0;\n\t" "if ! cc jump 1b;\n"	/* more to do, keep going */
-		"2:\t%3 = 0;\n\t"		/* strings are equal */
-		"jump.s    4f;\n" "3:\t%3 = %3 - %4;\n"	/* *cs - *ct */
- 		"4:":	"=a"(cs), "=a"(ct), "=da"(count), "=d"(__res1),
-		"=d"(__res2)
-		: "0"(cs), "1"(ct), "2"(count));
-
-	return __res1;
-}
-
-/*
- * memcpy - Copy one area of memory to another
- * @dest: Where to copy to
- * @src: Where to copy from
- * @count: The size of the area.
- *
- * You should not use this function to access IO space, use memcpy_toio()
- * or memcpy_fromio() instead.
- */
-void * memcpy(void * dest,const void *src,size_t count)
-{
-	char *tmp = (char *) dest, *s = (char *) src;
-
-/* Turn off the cache, if destination in the L1 memory */
-	if ( (tmp >= (char *)L1_ISRAM) && (tmp < (char *)L1_ISRAM_END)
-		|| (tmp >= (char *)DATA_BANKA_SRAM) && (tmp < DATA_BANKA_SRAM_END)
-	    || (tmp >= (char *)DATA_BANKB_SRAM) && (tmp < DATA_BANKB_SRAM_END) ){
-			if(icache_status()){
-					blackfin_icache_flush_range(src, src+count);
-					icache_disable();
-			}
-			if(dcache_status()){
-					blackfin_dcache_flush_range(src, src+count);
-					dcache_disable();
-			}
-			dma_memcpy(dest,src,count);
-	}else{
-		while(count--)
-			*tmp++ = *s++;
-	}
-	return dest;
-}
-
-void *dma_memcpy(void * dest,const void *src,size_t count)
-{
-
-		*pMDMA_D0_IRQ_STATUS = DMA_DONE | DMA_ERR;
-
-		/* Copy sram functions from sdram to sram */
-		/* Setup destination start address */
-		*pMDMA_D0_START_ADDR = (volatile void **)dest;
-		/* Setup destination xcount */
-		*pMDMA_D0_X_COUNT = count ;
-		/* Setup destination xmodify */
-		*pMDMA_D0_X_MODIFY = 1;
-
-		/* Setup Source start address */
-		*pMDMA_S0_START_ADDR = (volatile void **)src;
-		/* Setup Source xcount */
-		*pMDMA_S0_X_COUNT = count;
-		/* Setup Source xmodify */
-		*pMDMA_S0_X_MODIFY = 1;
-
-		/* Enable source DMA */
-		*pMDMA_S0_CONFIG = (DMAEN);
-		asm("ssync;");
-
-		*pMDMA_D0_CONFIG = ( WNR | DMAEN);
-
-		while(*pMDMA_D0_IRQ_STATUS & DMA_RUN){
-			*pMDMA_D0_IRQ_STATUS |= (DMA_DONE | DMA_ERR);
-		}
-		*pMDMA_D0_IRQ_STATUS |= (DMA_DONE | DMA_ERR);
-
-		dest += count;
-
-		return dest;
-}
diff --git a/arch/blackfin/lib/blackfin_linux.c b/arch/blackfin/lib/blackfin_linux.c
deleted file mode 100644
index 5ebd284d16..0000000000
--- a/arch/blackfin/lib/blackfin_linux.c
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * barebox - blackfin_linux.c
- *
- * Copyright (c) 2005 blackfin.uclinux.org
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@xxxxxxx.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-/* Dummy functions, currently not in Use */
-
-#include <common.h>
-#include <command.h>
-#include <image.h>
-#include <environment.h>
-#include <asm/byteorder.h>
-#include <asm/cpu.h>
-#include <asm/blackfin.h>
-#include <errno.h>
-#include <init.h>
-#include <boot.h>
-#include <bootm.h>
-
-#define CMD_LINE_ADDR 0xFF900000  /* L1 scratchpad */
-
-static int do_bootm_linux(struct image_data *idata)
-{
-	int (*appl)(char *cmdline);
-	const char *cmdline = linux_bootargs_get();
-	char *cmdlinedest = (char *) CMD_LINE_ADDR;
-	int ret;
-
-	ret = bootm_load_os(idata, idata->os_address);
-	if (ret)
-		return ret;
-
-	appl = (void *)(idata->os_address + idata->os_entry);
-	printf("Starting Kernel at 0x%p\n", appl);
-
-	if (idata->dryrun)
-		return 0;
-
-	icache_disable();
-
-	strncpy(cmdlinedest, cmdline, 0x1000);
-	cmdlinedest[0xfff] = 0;
-
-	*(volatile unsigned long *) IMASK = 0x1f;
-
-	(*appl)(cmdlinedest);
-
-	return -1;
-}
-
-static struct image_handler handler = {
-	.name = "Blackfin Linux",
-	.bootm = do_bootm_linux,
-	.filetype = filetype_uimage,
-	.ih_os = IH_OS_LINUX,
-};
-
-static int bfinlinux_register_image_handler(void)
-{
-	return register_image_handler(&handler);
-}
-
-late_initcall(bfinlinux_register_image_handler);
-
diff --git a/arch/blackfin/lib/board.c b/arch/blackfin/lib/board.c
deleted file mode 100644
index 3a04f28caf..0000000000
--- a/arch/blackfin/lib/board.c
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * barebox - board.c First C file to be called contains init routines
- *
- * Copyright (c) 2005 blackfin.uclinux.org
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@xxxxxxx.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <common.h>
-#include <command.h>
-#include <malloc.h>
-#include <net.h>
-#include <init.h>
-#include <environment.h>
-#include <memory.h>
-#include <asm/cpu.h>
-#include <asm-generic/memory_layout.h>
-
-void __noreturn blackfin_start_barebox(void)
-{
-	mem_malloc_init((void *)(MALLOC_BASE),
-			(void *)(MALLOC_BASE + MALLOC_SIZE - 1));
-	start_barebox();
-}
-
-/* We have to disable instruction cache before
- * executing an external program
- */
-static void arch_shutdown(void)
-{
-	icache_disable();
-}
-archshutdown_exitcall(arch_shutdown);
diff --git a/arch/blackfin/lib/clock.c b/arch/blackfin/lib/clock.c
deleted file mode 100644
index aaa042a33a..0000000000
--- a/arch/blackfin/lib/clock.c
+++ /dev/null
@@ -1,77 +0,0 @@
-
-#include <common.h>
-#include <clock.h>
-#include <init.h>
-#include <asm/blackfin.h>
-#include <asm/cpu/cdef_LPBlackfin.h>
-
-static ulong get_vco(void)
-{
-	ulong msel;
-	ulong vco;
-
-	msel = (*pPLL_CTL >> 9) & 0x3F;
-	if (0 == msel)
-		msel = 64;
-
-	vco = CONFIG_CLKIN_HZ;
-	vco >>= (1 & *pPLL_CTL);	/* DF bit */
-	vco = msel * vco;
-	return vco;
-}
-
-/* Get the Core clock */
-ulong get_cclk(void)
-{
-	ulong csel, ssel;
-	if (*pPLL_STAT & 0x1)
-		return CONFIG_CLKIN_HZ;
-
-	ssel = *pPLL_DIV;
-	csel = ((ssel >> 4) & 0x03);
-	ssel &= 0xf;
-	if (ssel && ssel < (1 << csel))	/* SCLK > CCLK */
-		return get_vco() / ssel;
-	return get_vco() >> csel;
-}
-
-/* Get the System clock */
-ulong get_sclk(void)
-{
-	ulong ssel;
-
-	if (*pPLL_STAT & 0x1)
-		return CONFIG_CLKIN_HZ;
-
-	ssel = (*pPLL_DIV & 0xf);
-
-	return get_vco() / ssel;
-}
-
-static uint64_t blackfin_clocksource_read(void)
-{
-	return ~(*pTCOUNT);
-}
-
-static struct clocksource cs = {
-	.read	= blackfin_clocksource_read,
-	.mask	= CLOCKSOURCE_MASK(32),
-	.shift	= 10,
-};
-
-static int clocksource_init (void)
-{
-	*pTCNTL = 0x1;
-	*pTSCALE = 0x0;
-	*pTCOUNT  = ~0;
-	*pTPERIOD = ~0;
-	*pTCNTL = 0x7;
-	asm("CSYNC;");
-
-        cs.mult = clocksource_hz2mult(get_cclk(), cs.shift);
-
-	return init_clock(&cs);
-}
-
-core_initcall(clocksource_init);
-
diff --git a/arch/blackfin/lib/cpu.c b/arch/blackfin/lib/cpu.c
deleted file mode 100644
index 34b93e78ac..0000000000
--- a/arch/blackfin/lib/cpu.c
+++ /dev/null
@@ -1,140 +0,0 @@
-/*
- * barebox - cpu.c CPU specific functions
- *
- * Copyright (c) 2005 blackfin.uclinux.org
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@xxxxxxx.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <common.h>
-#include <asm/blackfin.h>
-#include <command.h>
-#include <asm/entry.h>
-#include <asm/cpu.h>
-#include <init.h>
-#include <restart.h>
-
-static void __noreturn blackfin_restart_cpu(struct restart_handler *rst)
-{
-	icache_disable();
-
-	__asm__ __volatile__
-	("cli r3;"
-	"P0 = %0;"
-	"JUMP (P0);"
-	:
-	: "r" (L1_ISRAM)
-	);
-
-	/* Not reached */
-	hang();
-}
-
-static int restart_register_feature(void)
-{
-	restart_handler_register_fn(blackfin_restart_cpu);
-
-	return 0;
-}
-coredevice_initcall(restart_register_feature);
-
-void icache_disable(void)
-{
-#ifdef __ADSPBF537__
-	if ((*pCHIPID >> 28) < 2)
-		return;
-#endif
-	__builtin_bfin_ssync();
-	asm(" .align 8; ");
-	*(unsigned int *)IMEM_CONTROL &= ~(IMC | ENICPLB);
-	__builtin_bfin_ssync();
-}
-
-void icache_enable(void)
-{
-	unsigned int *I0, *I1;
-	int j = 0;
-#ifdef __ADSPBF537__
-	if ((*pCHIPID >> 28) < 2)
-		return;
-#endif
-	/* Before enable icache, disable it first */
-	icache_disable();
-
-	I0 = (unsigned int *)ICPLB_ADDR0;
-	I1 = (unsigned int *)ICPLB_DATA0;
-
-	/* We only setup instruction caching for barebox itself.
-	 * This has the nice side effect that we trigger an
-	 * exception when barebox goes crazy.
-	 */
-	*I0++ = TEXT_BASE & ~((1 << 20) - 1);
-	*I1++ = PAGE_SIZE_1MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK;
-	j++;
-
-	/* Fill the rest with invalid entry */
-	for ( ; j < 16 ; j++) {
-		debug("filling %i with 0\n",j);
-		*I1++ = 0x0;
-	}
-
-	__builtin_bfin_ssync();
-	asm(" .align 8; ");
-	*(unsigned int *)IMEM_CONTROL = IMC | ENICPLB;
-	__builtin_bfin_ssync();
-}
-
-int icache_status(void)
-{
-	unsigned int value;
-	value = *(unsigned int *)IMEM_CONTROL;
-
-	if (value & (IMC | ENICPLB))
-		return 1;
-	else
-		return 0;
-}
-
-static void blackfin_init_exceptions(void)
-{
-	*(unsigned volatile long *) (SIC_IMASK) = SIC_UNMASK_ALL;
-#ifndef CONFIG_KGDB
-	*(unsigned volatile long *) (EVT_EMULATION_ADDR) = 0x0;
-#endif
-	*(unsigned volatile long *) (EVT_NMI_ADDR) =
-		(unsigned volatile long) evt_nmi;
-	*(unsigned volatile long *) (EVT_EXCEPTION_ADDR) =
-		(unsigned volatile long) trap;
-	*(unsigned volatile long *) (EVT_HARDWARE_ERROR_ADDR) =
-		(unsigned volatile long) evt_ivhw;
-	*(volatile unsigned long *) ILAT = 0;
-	asm("csync;");
-	*(volatile unsigned long *) IMASK = 0x3f;
-	asm("csync;");
-}
-
-static int blackfin_init_core(void)
-{
-	blackfin_init_exceptions();
-	icache_enable();
-
-	return 0;
-}
-
-core_initcall(blackfin_init_core);
-
diff --git a/arch/blackfin/lib/divsi3.S b/arch/blackfin/lib/divsi3.S
deleted file mode 100644
index 32eb7c8de1..0000000000
--- a/arch/blackfin/lib/divsi3.S
+++ /dev/null
@@ -1,212 +0,0 @@
-/*
- * File:         arch/blackfin/lib/divsi3.S
- * Based on:
- * Author:
- *
- * Created:
- * Description:  16 / 32 bit signed division.
- *                 Special cases :
- *                      1)  If(numerator == 0)
- *                             return 0
- *                      2)  If(denominator ==0)
- *                             return positive max = 0x7fffffff
- *                      3)  If(numerator == denominator)
- *                             return 1
- *                      4)  If(denominator ==1)
- *                             return numerator
- *                      5)  If(denominator == -1)
- *                             return -numerator
- *
- *                 Operand         : R0 - Numerator   (i)
- *                                   R1 - Denominator (i)
- *                                   R0 - Quotient    (o)
- *                 Registers Used : R2-R7,P0-P2
- * Rev:          $Id: divsi3.S 2794 2007-03-05 05:27:47Z cooloney $
- *
- * Modified:
- *               Copyright 2004-2006 Analog Devices Inc.
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-.global   ___divsi3;
-
-#ifdef CONFIG_ARITHMETIC_OPS_L1
-.section .l1.text
-#else
-.text
-#endif
-
-.align 2;
-___divsi3 :
-
-
-  R3 = R0 ^ R1;
-  R0 = ABS R0;
-
-  CC = V;
-
-  r3 = rot r3 by -1;
-  r1 = abs r1;      /* now both positive, r3.30 means "negate result",
-                    ** r3.31 means overflow, add one to result
-                    */
-  cc = r0 < r1;
-  if cc jump .Lret_zero;
-  r2 = r1 >> 15;
-  cc = r2;
-  if cc jump .Lidents;
-  r2 = r1 << 16;
-  cc = r2 <= r0;
-  if cc jump .Lidents;
-
-  DIVS(R0, R1);
-  DIVQ(R0, R1);
-  DIVQ(R0, R1);
-  DIVQ(R0, R1);
-  DIVQ(R0, R1);
-  DIVQ(R0, R1);
-  DIVQ(R0, R1);
-  DIVQ(R0, R1);
-  DIVQ(R0, R1);
-  DIVQ(R0, R1);
-  DIVQ(R0, R1);
-  DIVQ(R0, R1);
-  DIVQ(R0, R1);
-  DIVQ(R0, R1);
-  DIVQ(R0, R1);
-  DIVQ(R0, R1);
-  DIVQ(R0, R1);
-
-  R0 = R0.L (Z);
-  r1 = r3 >> 31;    /* add overflow issue back in */
-  r0 = r0 + r1;
-  r1 = -r0;
-  cc = bittst(r3, 30);
-  if cc r0 = r1;
-  RTS;
-
-/* Can't use the primitives. Test common identities.
-** If the identity is true, return the value in R2.
-*/
-
-.Lidents:
-  CC = R1 == 0;                   /* check for divide by zero */
-  IF CC JUMP .Lident_return;
-
-  CC = R0 == 0;                   /* check for division of zero */
-  IF CC JUMP .Lzero_return;
-
-  CC = R0 == R1;                  /* check for identical operands */
-  IF CC JUMP .Lident_return;
-
-  CC = R1 == 1;                   /* check for divide by 1 */
-  IF CC JUMP .Lident_return;
-
-  R2.L = ONES R1;
-  R2 = R2.L (Z);
-  CC = R2 == 1;
-  IF CC JUMP .Lpower_of_two;
-
-  /* Identities haven't helped either.
-  ** Perform the full division process.
-  */
-
-  P1 = 31;                        /* Set loop counter   */
-
-  [--SP] = (R7:5);                /* Push registers R5-R7 */
-  R2 = -R1;
-  [--SP] = R2;
-  R2 = R0 << 1;                   /* R2 lsw of dividend  */
-  R6 = R0 ^ R1;                   /* Get sign */
-  R5 = R6 >> 31;                  /* Shift sign to LSB */
-
-  R0 = 0 ;                        /* Clear msw partial remainder */
-  R2 = R2 | R5;                   /* Shift quotient bit */
-  R6 = R0 ^ R1;                   /* Get new quotient bit */
-
-  LSETUP(.Llst,.Llend)  LC0 = P1;   /* Setup loop */
-.Llst:   R7 = R2 >> 31;            /* record copy of carry from R2 */
-        R2 = R2 << 1;             /* Shift 64 bit dividend up by 1 bit */
-        R0 = R0 << 1 || R5 = [SP];
-        R0 = R0 | R7;             /* and add carry */
-        CC = R6 < 0;              /* Check quotient(AQ) */
-                                  /* we might be subtracting divisor (AQ==0) */
-        IF CC R5 = R1;            /* or we might be adding divisor  (AQ==1)*/
-        R0 = R0 + R5;             /* do add or subtract, as indicated by AQ */
-        R6 = R0 ^ R1;             /* Generate next quotient bit */
-        R5 = R6 >> 31;
-                                  /* Assume AQ==1, shift in zero */
-        BITTGL(R5,0);             /* tweak AQ to be what we want to shift in */
-.Llend:  R2 = R2 + R5;             /* and then set shifted-in value to
-                                  ** tweaked AQ.
-                                  */
-  r1 = r3 >> 31;
-  r2 = r2 + r1;
-  cc = bittst(r3,30);
-  r0 = -r2;
-  if !cc r0 = r2;
-  SP += 4;
-  (R7:5)= [SP++];                 /* Pop registers R6-R7 */
-  RTS;
-
-.Lident_return:
-  CC = R1 == 0;                   /* check for divide by zero  => 0x7fffffff */
-  R2 = -1 (X);
-  R2 >>= 1;
-  IF CC JUMP .Ltrue_ident_return;
-
-  CC = R0 == R1;                  /* check for identical operands => 1 */
-  R2 = 1 (Z);
-  IF CC JUMP .Ltrue_ident_return;
-
-  R2 = R0;                        /* assume divide by 1 => numerator */
-  /*FALLTHRU*/
-
-.Ltrue_ident_return:
-  R0 = R2;                        /* Return an identity value */
-  R2 = -R2;
-  CC = bittst(R3,30);
-  IF CC R0 = R2;
-.Lzero_return:
-  RTS;                            /* ...including zero */
-
-.Lpower_of_two:
-  /* Y has a single bit set, which means it's a power of two.
-  ** That means we can perform the division just by shifting
-  ** X to the right the appropriate number of bits
-  */
-
-  /* signbits returns the number of sign bits, minus one.
-  ** 1=>30, 2=>29, ..., 0x40000000=>0. Which means we need
-  ** to shift right n-signbits spaces. It also means 0x80000000
-  ** is a special case, because that *also* gives a signbits of 0
-  */
-
-  R2 = R0 >> 31;
-  CC = R1 < 0;
-  IF CC JUMP .Ltrue_ident_return;
-
-  R1.l = SIGNBITS R1;
-  R1 = R1.L (Z);
-  R1 += -30;
-  R0 = LSHIFT R0 by R1.L;
-  r1 = r3 >> 31;
-  r0 = r0 + r1;
-  R2 = -R0;                       // negate result if necessary
-  CC = bittst(R3,30);
-  IF CC R0 = R2;
-  RTS;
-
-.Lret_zero:
-  R0 = 0;
-  RTS;
diff --git a/arch/blackfin/lib/flush.S b/arch/blackfin/lib/flush.S
deleted file mode 100644
index 4ee5d870ac..0000000000
--- a/arch/blackfin/lib/flush.S
+++ /dev/null
@@ -1,402 +0,0 @@
-/* Copyright (C) 2003 Analog Devices, Inc. All Rights Reserved.
- * Copyright (C) 2004 LG SOft India. All Rights Reserved.
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.
- *
- * Blackfin BF533/2.6 support : LG Soft India
- */
-#define ASSEMBLY
-
-#include <linux/linkage.h>
-#include <asm/cplb.h>
-#include <asm/blackfin.h>
-
-.text
-
-/* This is an external function being called by the user
- * application through __flush_cache_all. Currently this function
- * serves the purpose of flushing all the pending writes in
- * in the instruction cache.
- */
-
-ENTRY(_flush_instruction_cache)
-	[--SP] = ( R7:6, P5:4 );
-	LINK 12;
-	SP += -12;
-	P5.H = (ICPLB_ADDR0 >> 16);
-	P5.L = (ICPLB_ADDR0 & 0xFFFF);
-	P4.H = (ICPLB_DATA0 >> 16);
-	P4.L = (ICPLB_DATA0 & 0xFFFF);
-	R7 = CPLB_VALID | CPLB_L1_CHBL;
-	R6 = 16;
-inext:	R0 = [P5++];
-	R1 = [P4++];
-	[--SP] =  RETS;
-	CALL icplb_flush;	/* R0 = page, R1 = data*/
-	RETS = [SP++];
-iskip:	R6 += -1;
-	CC = R6;
-	IF CC JUMP inext;
-	SSYNC;
-	SP += 12;
-	UNLINK;
-	( R7:6, P5:4 ) = [SP++];
-	RTS;
-
-/* This is an internal function to flush all pending
- * writes in the cache associated with a particular ICPLB.
- *
- * R0 -  page's start address
- * R1 -  CPLB's data field.
- */
-
-.align 2
-ENTRY(icplb_flush)
-	[--SP] = ( R7:0, P5:0 );
-	[--SP] = LC0;
-	[--SP] = LT0;
-	[--SP] = LB0;
-	[--SP] = LC1;
-	[--SP] = LT1;
-	[--SP] = LB1;
-
-	/* If it's a 1K or 4K page, then it's quickest to
-	 * just systematically flush all the addresses in
-	 * the page, regardless of whether they're in the
-	 * cache, or dirty. If it's a 1M or 4M page, there
-	 * are too many addresses, and we have to search the
-	 * cache for lines corresponding to the page.
-	 */
-
-	CC = BITTST(R1, 17);	/* 1MB or 4MB */
-	IF !CC JUMP iflush_whole_page;
-
-	/* We're only interested in the page's size, so extract
-	 * this from the CPLB (bits 17:16), and scale to give an
-	 * offset into the page_size and page_prefix tables.
-	 */
-
-	R1 <<= 14;
-	R1 >>= 30;
-	R1 <<= 2;
-
-	/* We can also determine the sub-bank used, because this is
-	 * taken from bits 13:12 of the address.
-	 */
-
-	R3 = ((12<<8)|2);		/* Extraction pattern */
-	nop;				/*Anamoly 05000209*/
-	R4 = EXTRACT(R0, R3.L) (Z);	/* Extract bits*/
-	R3.H = R4.L << 0 ;		/* Save in extraction pattern for later deposit.*/
-
-
-	/* So:
-	 * R0 = Page start
-	 * R1 = Page length (actually, offset into size/prefix tables)
-	 * R3 = sub-bank deposit values
-  	 *
-	 * The cache has 2 Ways, and 64 sets, so we iterate through
-	 * the sets, accessing the tag for each Way, for our Bank and
-	 * sub-bank, looking for dirty, valid tags that match our
-	 * address prefix.
-	 */
-
-	P5.L = (ITEST_COMMAND & 0xFFFF);
-	P5.H = (ITEST_COMMAND >> 16);
-	P4.L = (ITEST_DATA0 & 0xFFFF);
-	P4.H = (ITEST_DATA0 >> 16);
-
-	P0.L = page_prefix_table;
-	P0.H = page_prefix_table;
-	P1 = R1;
-	R5 = 0;			/* Set counter*/
-	P0 = P1 + P0;
-	R4 = [P0];		/* This is the address prefix*/
-
-	/* We're reading (bit 1==0) the tag (bit 2==0), and we
-	 * don't care about which double-word, since we're only
-	 * fetching tags, so we only have to set Set, Bank,
-	 * Sub-bank and Way.
-	 */
-
-	P2 = 4;
-	LSETUP (ifs1, ife1) LC1 = P2;
-ifs1:	P0 = 32;		/* iterate over all sets*/
-	LSETUP (ifs0, ife0) LC0 = P0;
-ifs0:	R6 = R5 << 5;		/* Combine set*/
-	R6.H = R3.H << 0 ;	/* and sub-bank*/
-	[P5] = R6;		/* Issue Command*/
-	SSYNC;			/* CSYNC will not work here :(*/
-	R7 = [P4];		/* and read Tag.*/
-	CC = BITTST(R7, 0);	/* Check if valid*/
-	IF !CC JUMP ifskip;	/* and skip if not.*/
-
-	/* Compare against the page address. First, plant bits 13:12
-	 * into the tag, since those aren't part of the returned data.
-	 */
-
-	R7 = DEPOSIT(R7, R3);	/* set 13:12*/
-	R1 = R7 & R4;		/* Mask off lower bits*/
-	CC = R1 == R0;		/* Compare against page start.*/
-	IF !CC JUMP ifskip;	/* Skip it if it doesn't match.*/
-
-	/* Tag address matches against page, so this is an entry
-	 * we must flush.
-	 */
-
-	R7 >>= 10;		/* Mask off the non-address bits*/
-	R7 <<= 10;
-	P3 = R7;
-	IFLUSH [P3];		/* And flush the entry*/
-ifskip:
-ife0:	R5 += 1;		/* Advance to next Set*/
-ife1:	NOP;
-
-ifinished:
-	SSYNC;			/* Ensure the data gets out to mem.*/
-
-	/*Finished. Restore context.*/
-	LB1 = [SP++];
-	LT1 = [SP++];
-	LC1 = [SP++];
-	LB0 = [SP++];
-	LT0 = [SP++];
-	LC0 = [SP++];
-	( R7:0, P5:0 ) = [SP++];
-	RTS;
-
-iflush_whole_page:
-	/* It's a 1K or 4K page, so quicker to just flush the
-	 * entire page.
-	 */
-
-	P1 = 32;		/* For 1K pages*/
-	P2 = P1 << 2;		/* For 4K pages*/
-	P0 = R0;		/* Start of page*/
-	CC = BITTST(R1, 16);	/* Whether 1K or 4K*/
-	IF CC P1 = P2;
-	P1 += -1;		/* Unroll one iteration*/
-	SSYNC;
-	IFLUSH [P0++];		/* because CSYNC can't end loops.*/
-	LSETUP (isall, ieall) LC0 = P1;
-isall:IFLUSH [P0++];
-ieall: NOP;
-	SSYNC;
-	JUMP ifinished;
-
-/* This is an external function being called by the user
- * application through __flush_cache_all. Currently this function
- * serves the purpose of flushing all the pending writes in
- * in the data cache.
- */
-
-ENTRY(_flush_data_cache)
-	[--SP] = ( R7:6, P5:4 );
-	LINK 12;
-	SP += -12;
-	P5.H = (DCPLB_ADDR0 >> 16);
-	P5.L = (DCPLB_ADDR0 & 0xFFFF);
-	P4.H = (DCPLB_DATA0 >> 16);
-	P4.L = (DCPLB_DATA0 & 0xFFFF);
-	R7 = CPLB_VALID | CPLB_L1_CHBL | CPLB_DIRTY (Z);
-	R6 = 16;
-next:	R0 = [P5++];
-	R1 = [P4++];
-	CC = BITTST(R1, 14);	/* Is it write-through?*/
-	IF CC JUMP skip;	/* If so, ignore it.*/
-	R2 = R1 & R7;		/* Is it a dirty, cached page?*/
-	CC = R2;
-	IF !CC JUMP skip;	/* If not, ignore it.*/
-	[--SP] = RETS;
-	CALL dcplb_flush;	/* R0 = page, R1 = data*/
-	RETS = [SP++];
-skip:	R6 += -1;
-	CC = R6;
-	IF CC JUMP next;
-	SSYNC;
-	SP += 12;
-	UNLINK;
-	( R7:6, P5:4 ) = [SP++];
-	RTS;
-
-/* This is an internal function to flush all pending
- * writes in the cache associated with a particular DCPLB.
- *
- * R0 -  page's start address
- * R1 -  CPLB's data field.
- */
-
-.align 2
-ENTRY(dcplb_flush)
-	[--SP] = ( R7:0, P5:0 );
-	[--SP] = LC0;
-	[--SP] = LT0;
-	[--SP] = LB0;
-	[--SP] = LC1;
-	[--SP] = LT1;
-	[--SP] = LB1;
-
-	/* If it's a 1K or 4K page, then it's quickest to
-	 * just systematically flush all the addresses in
-	 * the page, regardless of whether they're in the
-	 * cache, or dirty. If it's a 1M or 4M page, there
-	 * are too many addresses, and we have to search the
-	 * cache for lines corresponding to the page.
-	 */
-
-	CC = BITTST(R1, 17);	/* 1MB or 4MB */
-	IF !CC JUMP dflush_whole_page;
-
-	/* We're only interested in the page's size, so extract
-	 * this from the CPLB (bits 17:16), and scale to give an
-	 * offset into the page_size and page_prefix tables.
-	 */
-
-	R1 <<= 14;
-	R1 >>= 30;
-	R1 <<= 2;
-
-	/* The page could be mapped into Bank A or Bank B, depending
-	 * on (a) whether both banks are configured as cache, and
-	 * (b) on whether address bit A[x] is set. x is determined
-	 * by DCBS in DMEM_CONTROL
-	 */
-
-	R2 = 0;			/* Default to Bank A (Bank B would be 1)*/
-
-	P0.L = (DMEM_CONTROL & 0xFFFF);
-	P0.H = (DMEM_CONTROL >> 16);
-
-	R3 = [P0];		/* If Bank B is not enabled as cache*/
-	CC = BITTST(R3, 2);	/* then Bank A is our only option.*/
-	IF CC JUMP bank_chosen;
-
-	R4 = 1<<14;		/* If DCBS==0, use A[14].*/
-	R5 = R4 << 7;		/* If DCBS==1, use A[23];*/
-	CC = BITTST(R3, 4);
-	IF CC R4 = R5;		/* R4 now has either bit 14 or bit 23 set.*/
-	R5 = R0 & R4;		/* Use it to test the Page address*/
-	CC = R5;		/* and if that bit is set, we use Bank B,*/
-	R2 = CC;		/* else we use Bank A.*/
-	R2 <<= 23;		/* The Bank selection's at posn 23.*/
-
-bank_chosen:
-
-	/* We can also determine the sub-bank used, because this is
-	 * taken from bits 13:12 of the address.
-	 */
-
-	R3 = ((12<<8)|2);		/* Extraction pattern */
-	nop;				/*Anamoly 05000209*/
-	R4 = EXTRACT(R0, R3.L) (Z);	/* Extract bits*/
-	R3.H = R4.L << 0 ;		/* Save in extraction pattern for later deposit.*/
-
-	/* So:
-	 * R0 = Page start
-	 * R1 = Page length (actually, offset into size/prefix tables)
-	 * R2 = Bank select mask
-	 * R3 = sub-bank deposit values
-  	 *
-	 * The cache has 2 Ways, and 64 sets, so we iterate through
-	 * the sets, accessing the tag for each Way, for our Bank and
-	 * sub-bank, looking for dirty, valid tags that match our
-	 * address prefix.
-	 */
-
-	P5.L = (DTEST_COMMAND & 0xFFFF);
-	P5.H = (DTEST_COMMAND >> 16);
-	P4.L = (DTEST_DATA0 & 0xFFFF);
-	P4.H = (DTEST_DATA0 >> 16);
-
-	P0.L = page_prefix_table;
-	P0.H = page_prefix_table;
-	P1 = R1;
-	R5 = 0;			/* Set counter*/
-	P0 = P1 + P0;
-	R4 = [P0];		/* This is the address prefix*/
-
-
-	/* We're reading (bit 1==0) the tag (bit 2==0), and we
-	 * don't care about which double-word, since we're only
-	 * fetching tags, so we only have to set Set, Bank,
-	 * Sub-bank and Way.
-	 */
-
-	P2 = 2;
-	LSETUP (fs1, fe1) LC1 = P2;
-fs1:	P0 = 64;		/* iterate over all sets*/
-	LSETUP (fs0, fe0) LC0 = P0;
-fs0:	R6 = R5 << 5;		/* Combine set*/
-	R6.H = R3.H << 0 ;	/* and sub-bank*/
-	R6 = R6 | R2;		/* and Bank. Leave Way==0 at first.*/
-	BITSET(R6,14);
-	[P5] = R6;		/* Issue Command*/
-	SSYNC;
-	R7 = [P4];		/* and read Tag.*/
-	CC = BITTST(R7, 0);	/* Check if valid*/
-	IF !CC JUMP fskip;	/* and skip if not.*/
-	CC = BITTST(R7, 1);	/* Check if dirty*/
-	IF !CC JUMP fskip;	/* and skip if not.*/
-
-	/* Compare against the page address. First, plant bits 13:12
-	 * into the tag, since those aren't part of the returned data.
-	 */
-
-	R7 = DEPOSIT(R7, R3);	/* set 13:12*/
-	R1 = R7 & R4;		/* Mask off lower bits*/
-	CC = R1 == R0;		/* Compare against page start.*/
-	IF !CC JUMP fskip;	/* Skip it if it doesn't match.*/
-
-	/* Tag address matches against page, so this is an entry
-	 * we must flush.
-	 */
-
-	R7 >>= 10;		/* Mask off the non-address bits*/
-	R7 <<= 10;
-	P3 = R7;
-	SSYNC;
-	FLUSHINV [P3];		/* And flush the entry*/
-fskip:
-fe0:	R5 += 1;		/* Advance to next Set*/
-fe1:	BITSET(R2, 26);		/* Go to next Way.*/
-
-dfinished:
-	SSYNC;			/* Ensure the data gets out to mem.*/
-
-	/*Finished. Restore context.*/
-	LB1 = [SP++];
-	LT1 = [SP++];
-	LC1 = [SP++];
-	LB0 = [SP++];
-	LT0 = [SP++];
-	LC0 = [SP++];
-	( R7:0, P5:0 ) = [SP++];
-	RTS;
-
-dflush_whole_page:
-
-	/* It's a 1K or 4K page, so quicker to just flush the
-	 * entire page.
-	 */
-
-	P1 = 32;		/* For 1K pages*/
-	P2 = P1 << 2;		/* For 4K pages*/
-	P0 = R0;		/* Start of page*/
-	CC = BITTST(R1, 16);	/* Whether 1K or 4K*/
-	IF CC P1 = P2;
-	P1 += -1;		/* Unroll one iteration*/
-    SSYNC;
-	FLUSHINV [P0++];	/* because CSYNC can't end loops.*/
-	LSETUP (eall, eall) LC0 = P1;
-eall:	FLUSHINV [P0++];
-	SSYNC;
-	JUMP dfinished;
-
-.align 4;
-page_prefix_table:
-.byte4 	0xFFFFFC00;	/* 1K */
-.byte4	0xFFFFF000;	/* 4K */
-.byte4	0xFFF00000;	/* 1M */
-.byte4	0xFFC00000;	/* 4M */
-.page_prefix_table.end:
diff --git a/arch/blackfin/lib/gcclib.h b/arch/blackfin/lib/gcclib.h
deleted file mode 100644
index 4583c09aa1..0000000000
--- a/arch/blackfin/lib/gcclib.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * File:         arch/blackfin/lib/gcclib.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:
- *
- * Rev:          $Id: gcclib.h 1942 2006-08-03 17:37:22Z vapier $
- *
- * Modified:
- *               Copyright 2004-2006 Analog Devices Inc.
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#define BITS_PER_UNIT  8
-#define SI_TYPE_SIZE (sizeof (SItype) * BITS_PER_UNIT)
-
-typedef unsigned int UQItype __attribute__ ((mode(QI)));
-typedef int SItype __attribute__ ((mode(SI)));
-typedef unsigned int USItype __attribute__ ((mode(SI)));
-typedef int DItype __attribute__ ((mode(DI)));
-typedef int word_type __attribute__ ((mode(__word__)));
-typedef unsigned int UDItype __attribute__ ((mode(DI)));
-
-struct DIstruct {
-	SItype low, high;
-};
-
-typedef union {
-	struct DIstruct s;
-	DItype ll;
-} DIunion;
diff --git a/arch/blackfin/lib/interrupt.S b/arch/blackfin/lib/interrupt.S
deleted file mode 100644
index 7a44f92e61..0000000000
--- a/arch/blackfin/lib/interrupt.S
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- * barebox - interrupt.S Processing of interrupts and exception handling
- *
- * Copyright (c) 2005 blackfin.uclinux.org
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@xxxxxxx.
- *
- * This file is based on interrupt.S
- *
- * Copyright (C) 2003  Metrowerks, Inc. <mwaddel@xxxxxxxxxxxxxx>
- * Copyright (C) 2002  Arcturus Networks Ltd. Ted Ma <mated@xxxxxxxxxxxx>
- * Copyright (C) 1998  D. Jeff Dionne <jeff@xxxxxxxxxxxxxxxxxxxx>,
- *                     Kenneth Albanowski <kjahds@xxxxxxxxxx>,
- *                     The Silver Hammer Group, Ltd.
- *
- * (c) 1995, Dionne & Associates
- * (c) 1995, DKG Display Tech.
- *
- * This file is also based on exception.asm
- * (C) Copyright 2001-2005 - Analog Devices, Inc.  All rights reserved.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#define ASSEMBLY
-#include <config.h>
-#include <asm/blackfin.h>
-#include <asm/hw_irq.h>
-#include <asm/entry.h>
-#include <asm/blackfin_defs.h>
-#include <asm/irq.h>
-
-.global _blackfin_irq_panic;
-
-.text
-.align 2
-
-#ifndef CONFIG_KGDB
-.global _evt_emulation
-_evt_emulation:
-	SAVE_CONTEXT
-	r0 = IRQ_EMU;
-	r1 = seqstat;
-	sp += -12;
-	call _blackfin_irq_panic;
-	sp += 12;
-	rte;
-#endif
-
-.global _evt_nmi
-_evt_nmi:
-	SAVE_CONTEXT
-	r0 = IRQ_NMI;
-	r1 = RETN;
-	sp += -12;
-	call _blackfin_irq_panic;
-	sp += 12;
-
-_evt_nmi_exit:
-	rtn;
-
-.global _trap
-_trap:
-	SAVE_ALL_SYS
-        r0 = sp;        /* stack frame pt_regs pointer argument ==> r0 */
-        sp += -12;
-        call _trap_c
-        sp += 12;
-        RESTORE_ALL_SYS
-        rtx;
-
-.global _evt_ivhw
-_evt_ivhw:
-	SAVE_CONTEXT
-	RAISE 14;
-
-_evt_ivhw_exit:
-	 rti;
-
diff --git a/arch/blackfin/lib/lshrdi3.c b/arch/blackfin/lib/lshrdi3.c
deleted file mode 100644
index 85bdd85f18..0000000000
--- a/arch/blackfin/lib/lshrdi3.c
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * File:         arch/blackfin/lib/lshrdi3.c
- * Based on:
- * Author:
- *
- * Created:
- * Description:
- *
- * Rev:          $Id: lshrdi3.c 2775 2007-02-21 13:58:44Z hennerich $
- *
- * Modified:
- *               Copyright 2004-2006 Analog Devices Inc.
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#define BITS_PER_UNIT 8
-
-typedef int SItype __attribute__ ((mode(SI)));
-typedef unsigned int USItype __attribute__ ((mode(SI)));
-typedef int DItype __attribute__ ((mode(DI)));
-typedef int word_type __attribute__ ((mode(__word__)));
-
-struct DIstruct {
-	SItype high, low;
-};
-
-typedef union {
-	struct DIstruct s;
-	DItype ll;
-} DIunion;
-
-#ifdef CONFIG_ARITHMETIC_OPS_L1
-DItype __lshrdi3(DItype u, word_type b)__attribute__((l1_text));
-#endif
-
-DItype __lshrdi3(DItype u, word_type b)
-{
-	DIunion w;
-	word_type bm;
-	DIunion uu;
-
-	if (b == 0)
-		return u;
-
-	uu.ll = u;
-
-	bm = (sizeof(SItype) * BITS_PER_UNIT) - b;
-	if (bm <= 0) {
-		w.s.high = 0;
-		w.s.low = (USItype) uu.s.high >> -bm;
-	} else {
-		USItype carries = (USItype) uu.s.high << bm;
-		w.s.high = (USItype) uu.s.high >> b;
-		w.s.low = ((USItype) uu.s.low >> b) | carries;
-	}
-
-	return w.ll;
-}
diff --git a/arch/blackfin/lib/modsi3.S b/arch/blackfin/lib/modsi3.S
deleted file mode 100644
index bbf4554a5a..0000000000
--- a/arch/blackfin/lib/modsi3.S
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- * File:         arch/blackfin/lib/modsi3.S
- * Based on:
- * Author:
- *
- * Created:
- * Description:  This program computes 32 bit signed remainder. It calls div32 function
- *               for quotient estimation.
- *
- *               Registers used :
- *               Numerator/ Denominator in  R0, R1
- *                 R0  -  returns remainder.
- *                 R2-R7
- *
- * Rev:          $Id: modsi3.S 2775 2007-02-21 13:58:44Z hennerich $
- *
- * Modified:
- *               Copyright 2004-2006 Analog Devices Inc.
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-.global ___modsi3;
-.type ___modsi3, STT_FUNC;
-.extern ___divsi3;
-.type ___divsi3, STT_FUNC;
-
-#ifdef CONFIG_ARITHMETIC_OPS_L1
-.section .l1.text
-#else
-.text
-#endif
-
-___modsi3:
-
-	CC=R0==0;
-	IF CC JUMP .LRETURN_R0;		/* Return 0, if numerator  == 0 */
-	CC=R1==0;
-	IF CC JUMP .LRETURN_ZERO;		/* Return 0, if denominator == 0 */
-	CC=R0==R1;
-	IF CC JUMP .LRETURN_ZERO;		/* Return 0, if numerator == denominator */
-	CC = R1 == 1;
-	IF CC JUMP .LRETURN_ZERO;		/* Return 0, if denominator ==  1 */
-	CC = R1 == -1;
-	IF CC JUMP .LRETURN_ZERO;		/* Return 0, if denominator == -1 */
-
-	/* Valid input. Use __divsi3() to compute the quotient, and then
-	 * derive the remainder from that. */
-
-	[--SP] = (R7:6);		/* Push  R7 and R6 */
-	[--SP] = RETS;			/* and return address */
-	R7 = R0;			/* Copy of R0 */
-	R6 = R1;			/* Save for later */
-	SP += -12;			/* Should always provide this space */
-	CALL ___divsi3;			/* Compute signed quotient using ___divsi3()*/
-	SP += 12;
-	R0 *= R6;			/* Quotient * divisor */
-	R0 = R7 - R0;			/* Dividend - (quotient * divisor) */
-	RETS = [SP++];			/* Get back return address */
-	(R7:6) = [SP++];		/* Pop registers R7 and R4 */
-	RTS;				/* Store remainder    */
-
-.LRETURN_ZERO:
-	R0 = 0;
-.LRETURN_R0:
-	RTS;
diff --git a/arch/blackfin/lib/module.c b/arch/blackfin/lib/module.c
deleted file mode 100644
index 094afc5b49..0000000000
--- a/arch/blackfin/lib/module.c
+++ /dev/null
@@ -1,306 +0,0 @@
-/*
- * File:         arch/blackfin/kernel/module.c
- * Based on:
- * Author:
- *
- * Created:
- * Description:
- *
- * Modified:
- *               Copyright 2004-2006 Analog Devices Inc.
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <common.h>
-#include <elf.h>
-#include <module.h>
-#include <malloc.h>
-#include <errno.h>
-
-/*
- * handle arithmetic relocations.
- * See binutils/bfd/elf32-bfin.c for more details
- */
-#define RELOC_STACK_SIZE 100
-static uint32_t reloc_stack[RELOC_STACK_SIZE];
-static unsigned int reloc_stack_tos;
-
-#define is_reloc_stack_empty() ((reloc_stack_tos > 0)?0:1)
-
-static void reloc_stack_push(uint32_t value)
-{
-	reloc_stack[reloc_stack_tos++] = value;
-}
-
-static uint32_t reloc_stack_pop(void)
-{
-	return reloc_stack[--reloc_stack_tos];
-}
-
-static uint32_t reloc_stack_operate(unsigned int oper, struct module *mod)
-{
-	uint32_t value;
-
-	switch (oper) {
-	case R_add:
-		value = reloc_stack[reloc_stack_tos - 2] +
-			reloc_stack[reloc_stack_tos - 1];
-		reloc_stack_tos -= 2;
-		break;
-	case R_sub:
-		value = reloc_stack[reloc_stack_tos - 2] -
-			reloc_stack[reloc_stack_tos - 1];
-		reloc_stack_tos -= 2;
-		break;
-	case R_mult:
-		value = reloc_stack[reloc_stack_tos - 2] *
-			reloc_stack[reloc_stack_tos - 1];
-		reloc_stack_tos -= 2;
-		break;
-	case R_div:
-		value = reloc_stack[reloc_stack_tos - 2] /
-			reloc_stack[reloc_stack_tos - 1];
-		reloc_stack_tos -= 2;
-		break;
-	case R_mod:
-		value = reloc_stack[reloc_stack_tos - 2] %
-			reloc_stack[reloc_stack_tos - 1];
-		reloc_stack_tos -= 2;
-		break;
-	case R_lshift:
-		value = reloc_stack[reloc_stack_tos - 2] <<
-			reloc_stack[reloc_stack_tos - 1];
-		reloc_stack_tos -= 2;
-		break;
-	case R_rshift:
-		value = reloc_stack[reloc_stack_tos - 2] >>
-			reloc_stack[reloc_stack_tos - 1];
-		reloc_stack_tos -= 2;
-		break;
-	case R_and:
-		value = reloc_stack[reloc_stack_tos - 2] &
-			reloc_stack[reloc_stack_tos - 1];
-		reloc_stack_tos -= 2;
-		break;
-	case R_or:
-		value = reloc_stack[reloc_stack_tos - 2] |
-			reloc_stack[reloc_stack_tos - 1];
-		reloc_stack_tos -= 2;
-		break;
-	case R_xor:
-		value = reloc_stack[reloc_stack_tos - 2] ^
-			reloc_stack[reloc_stack_tos - 1];
-		reloc_stack_tos -= 2;
-		break;
-	case R_land:
-		value = reloc_stack[reloc_stack_tos - 2] &&
-			reloc_stack[reloc_stack_tos - 1];
-		reloc_stack_tos -= 2;
-		break;
-	case R_lor:
-		value = reloc_stack[reloc_stack_tos - 2] ||
-			reloc_stack[reloc_stack_tos - 1];
-		reloc_stack_tos -= 2;
-		break;
-	case R_neg:
-		value = -reloc_stack[reloc_stack_tos - 1];
-		reloc_stack_tos--;
-		break;
-	case R_comp:
-		value = ~reloc_stack[reloc_stack_tos - 1];
-		reloc_stack_tos -= 1;
-		break;
-	default:
-		printf("module %s: unhandled reloction\n",
-				mod->name);
-		return 0;
-	}
-
-	/* now push the new value back on stack */
-	reloc_stack_push(value);
-
-	return value;
-}
-
-int
-apply_relocate(Elf_Shdr * sechdrs, const char *strtab,
-	       unsigned int symindex, unsigned int relsec, struct module *me)
-{
-	printf("module %s: .rel unsupported\n", me->name);
-	return -ENOEXEC;
-}
-
-/*************************************************************************/
-/* FUNCTION : apply_relocate_add                                         */
-/* ABSTRACT : Blackfin specific relocation handling for the loadable     */
-/*            modules. Modules are expected to be .o files.              */
-/*            Arithmetic relocations are handled.                        */
-/*            We do not expect LSETUP to be split and hence is not       */
-/*            handled.                                                   */
-/*            R_byte and R_byte2 are also not handled as the gas         */
-/*            does not generate it.                                      */
-/*************************************************************************/
-int
-apply_relocate_add(Elf_Shdr * sechdrs, const char *strtab,
-		   unsigned int symindex, unsigned int relsec,
-		   struct module *mod)
-{
-	unsigned int i;
-	unsigned short tmp;
-	Elf32_Rela *rel = (void *)sechdrs[relsec].sh_addr;
-	Elf32_Sym *sym;
-	uint32_t *location32;
-	uint16_t *location16;
-	uint32_t value;
-
-	debug("Applying relocate section %u to %u\n", relsec,
-	       sechdrs[relsec].sh_info);
-	for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) {
-		/* This is where to make the change */
-		location16 =
-		    (uint16_t *) (sechdrs[sechdrs[relsec].sh_info].sh_addr +
-				  rel[i].r_offset);
-		location32 = (uint32_t *) location16;
-		/* This is the symbol it is referring to. Note that all
-		   undefined symbols have been resolved. */
-		sym = (Elf32_Sym *) sechdrs[symindex].sh_addr
-		    + ELF32_R_SYM(rel[i].r_info);
-		if (is_reloc_stack_empty()) {
-			value = sym->st_value;
-		} else {
-			value = reloc_stack_pop();
-		}
-		value += rel[i].r_addend;
-		debug("location is %x, value is %x type is %d \n",
-			 (unsigned int) location32, value,
-			 ELF32_R_TYPE(rel[i].r_info));
-
-		switch (ELF32_R_TYPE(rel[i].r_info)) {
-
-		case R_pcrel24:
-		case R_pcrel24_jump_l:
-			/* Add the value, subtract its postition */
-			location16 =
-			    (uint16_t *) (sechdrs[sechdrs[relsec].sh_info].
-					  sh_addr + rel[i].r_offset - 2);
-			location32 = (uint32_t *) location16;
-			value -= (uint32_t) location32;
-			value >>= 1;
-			debug("value is %x, before %x-%x after %x-%x\n", value,
-			       *location16, *(location16 + 1),
-			       (*location16 & 0xff00) | (value >> 16 & 0x00ff),
-			       value & 0xffff);
-			*location16 =
-			    (*location16 & 0xff00) | (value >> 16 & 0x00ff);
-			*(location16 + 1) = value & 0xffff;
-			break;
-		case R_pcrel12_jump:
-		case R_pcrel12_jump_s:
-			value -= (uint32_t) location32;
-			value >>= 1;
-			*location16 = (value & 0xfff);
-			break;
-		case R_pcrel10:
-			value -= (uint32_t) location32;
-			value >>= 1;
-			*location16 = (value & 0x3ff);
-			break;
-		case R_luimm16:
-			debug("before %x after %x\n", *location16,
-				       (value & 0xffff));
-			tmp = (value & 0xffff);
-			*location16 = tmp;
-			break;
-		case R_huimm16:
-			debug("before %x after %x\n", *location16,
-				       ((value >> 16) & 0xffff));
-			tmp = ((value >> 16) & 0xffff);
-			*location16 = tmp;
-			break;
-		case R_rimm16:
-			*location16 = (value & 0xffff);
-			break;
-		case R_byte4_data:
-			debug("before %x after %x\n", *location32, value);
-			*location32 = value;
-			break;
-		case R_push:
-			reloc_stack_push(value);
-			break;
-		case R_const:
-			reloc_stack_push(rel[i].r_addend);
-			break;
-		case R_add:
-		case R_sub:
-		case R_mult:
-		case R_div:
-		case R_mod:
-		case R_lshift:
-		case R_rshift:
-		case R_and:
-		case R_or:
-		case R_xor:
-		case R_land:
-		case R_lor:
-		case R_neg:
-		case R_comp:
-			reloc_stack_operate(ELF32_R_TYPE(rel[i].r_info), mod);
-			break;
-		default:
-			printf("module %s: Unknown relocation: %u\n",
-			       mod->name, ELF32_R_TYPE(rel[i].r_info));
-			return -ENOEXEC;
-		}
-	}
-	return 0;
-}
-
-#if 0
-int
-module_finalize(const Elf_Ehdr * hdr,
-		const Elf_Shdr * sechdrs, struct module *mod)
-{
-	unsigned int i, strindex = 0, symindex = 0;
-	char *secstrings;
-
-	secstrings = (void *)hdr + sechdrs[hdr->e_shstrndx].sh_offset;
-
-	for (i = 1; i < hdr->e_shnum; i++) {
-		/* Internal symbols and strings. */
-		if (sechdrs[i].sh_type == SHT_SYMTAB) {
-			symindex = i;
-			strindex = sechdrs[i].sh_link;
-		}
-	}
-
-	for (i = 1; i < hdr->e_shnum; i++) {
-		const char *strtab = (char *)sechdrs[strindex].sh_addr;
-		unsigned int info = sechdrs[i].sh_info;
-
-		/* Not a valid relocation section? */
-		if (info >= hdr->e_shnum)
-			continue;
-
-		if ((sechdrs[i].sh_type == SHT_RELA) &&
-		    ((strcmp(".rela.l1.text", secstrings + sechdrs[i].sh_name) == 0) ||
-		    ((strcmp(".rela.text", secstrings + sechdrs[i].sh_name) == 0) &&
-			 (hdr->e_flags & FLG_CODE_IN_L1)))) {
-			apply_relocate_add((Elf_Shdr *) sechdrs, strtab,
-					   symindex, i, mod);
-		}
-	}
-	return 0;
-}
-#endif
-
diff --git a/arch/blackfin/lib/muldi3.c b/arch/blackfin/lib/muldi3.c
deleted file mode 100644
index 17c303b953..0000000000
--- a/arch/blackfin/lib/muldi3.c
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * barebox - muldi3.c contains routines for mult and div
- *
- * Copyright (c) 2005 blackfin.uclinux.org
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include "gcclib.h"
-
-/* Generic function got from GNU gcc package, libgcc2.c */
-#define __ll_B (1L << (SI_TYPE_SIZE / 2))
-#define __ll_lowpart(t) ((USItype) (t) % __ll_B)
-#define __ll_highpart(t) ((USItype) (t) / __ll_B)
-#define BITS_PER_UNIT 8
-
-#if !defined (umul_ppmm)
-#define umul_ppmm(w1, w0, u, v)						\
-do {									\
-	USItype __x0, __x1, __x2, __x3;					\
-	USItype __ul, __vl, __uh, __vh;					\
-									\
-	__ul = __ll_lowpart (u);					\
-	__uh = __ll_highpart (u);					\
-	__vl = __ll_lowpart (v);					\
-	__vh = __ll_highpart (v);					\
-									\
-	__x0 = (USItype) __ul * __vl;					\
-	__x1 = (USItype) __ul * __vh;					\
-	__x2 = (USItype) __uh * __vl;					\
-	__x3 = (USItype) __uh * __vh;					\
-									\
-	__x1 += __ll_highpart (__x0);/* this can't give carry */	\
-	__x1 += __x2;	/* but this indeed can */			\
-	if (__x1 < __x2)	/* did we get it? */			\
-		__x3 += __ll_B;	/* yes, add it in the proper pos. */	\
-									\
-	(w1) = __x3 + __ll_highpart (__x1);				\
-	(w0) = __ll_lowpart (__x1) * __ll_B + __ll_lowpart (__x0);	\
-} while (0)
-#endif
-
-#if !defined (__umulsidi3)
-#define __umulsidi3(u, v)						\
-	({DIunion __w;							\
-	umul_ppmm (__w.s.high, __w.s.low, u, v);			\
-	__w.ll; })
-#endif
-
-DItype __muldi3 (DItype u, DItype v)
-{
-	DIunion w;
-	DIunion uu, vv;
-
-	uu.ll = u,
-	vv.ll = v;
-	/*  panic("kernel panic for __muldi3"); */
-	w.ll = __umulsidi3 (uu.s.low, vv.s.low);
-	w.s.high += ((USItype) uu.s.low * (USItype) vv.s.high
-	+ (USItype) uu.s.high * (USItype) vv.s.low);
-
-	return w.ll;
-}
diff --git a/arch/blackfin/lib/smulsi3_highpart.S b/arch/blackfin/lib/smulsi3_highpart.S
deleted file mode 100644
index 10b8f8da57..0000000000
--- a/arch/blackfin/lib/smulsi3_highpart.S
+++ /dev/null
@@ -1,30 +0,0 @@
-.align 2
-.global ___smulsi3_highpart;
-.type ___smulsi3_highpart, STT_FUNC;
-
-#ifdef CONFIG_ARITHMETIC_OPS_L1
-.section .l1.text
-#else
-.text
-#endif
-
-___smulsi3_highpart:
-	R2 = R1.L * R0.L (FU);
-	R3 = R1.H * R0.L (IS,M);
-	R0 = R0.H * R1.H, R1 = R0.H * R1.L (IS,M);
-
-	R1.L = R2.H + R1.L;
-	cc = ac0;
-	R2 = cc;
-
-	R1.L = R1.L + R3.L;
-	cc = ac0;
-	R1 >>>= 16;
-	R3 >>>= 16;
-	R1 = R1 + R3;
-	R1 = R1 + R2;
-	R2 = cc;
-	R1 = R1 + R2;
-
-	R0 = R0 + R1;
-	RTS;
diff --git a/arch/blackfin/lib/traps.c b/arch/blackfin/lib/traps.c
deleted file mode 100644
index 2111d255fd..0000000000
--- a/arch/blackfin/lib/traps.c
+++ /dev/null
@@ -1,107 +0,0 @@
-/*
- * barebox - traps.c Routines related to interrupts and exceptions
- *
- * Copyright (c) 2005 blackfin.uclinux.org
- *
- * This file is based on
- * No original Copyright holder listed,
- * Probabily original (C) Roman Zippel (assigned DJD, 1999)
- *
- * Copyright 2003 Metrowerks - for Blackfin
- * Copyright 2000-2001 Lineo, Inc. D. Jeff Dionne <jeff@xxxxxxxx>
- * Copyright 1999-2000 D. Jeff Dionne, <jeff@xxxxxxxxxxx>
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@xxxxxxx.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <common.h>
-#include <restart.h>
-#include <linux/types.h>
-#include <asm/system.h>
-#include <asm/traps.h>
-#include <asm/page.h>
-#include <asm/cplb.h>
-#include <asm/ptrace.h>
-#include <asm/cpu.h>
-
-void dump_regs(struct pt_regs *fp)
-{
-	printf("DCPLB_FAULT_ADDR=%p\n", *pDCPLB_FAULT_ADDR);
-	printf("ICPLB_FAULT_ADDR=%p\n", *pICPLB_FAULT_ADDR);
-
-	printf("stack frame=0x%x, ", (unsigned int) fp);
-	printf("bad PC=0x%04x\n", (unsigned int) fp->pc);
-        printf("RETE:  %08lx  RETN: %08lx  RETX: %08lx  RETS: %08lx\n", fp->rete, fp->retn, fp->retx, fp->rets);
-        printf("IPEND: %04lx  SYSCFG: %04lx\n", fp->ipend, fp->syscfg);
-        printf("SEQSTAT: %08lx    SP: %08lx\n", (long)fp->seqstat, (long)fp);
-        printf("R0: %08lx    R1: %08lx    R2: %08lx    R3: %08lx\n", fp->r0, fp->r1, fp->r2, fp->r3);
-        printf("R4: %08lx    R5: %08lx    R6: %08lx    R7: %08lx\n", fp->r4, fp->r5, fp->r6, fp->r7);
-        printf("P0: %08lx    P1: %08lx    P2: %08lx    P3: %08lx\n", fp->p0, fp->p1, fp->p2, fp->p3);
-        printf("P4: %08lx    P5: %08lx    FP: %08lx\n", fp->p4, fp->p5, fp->fp);
-        printf("A0.w: %08lx    A0.x: %08lx    A1.w: %08lx    A1.x: %08lx\n", fp->a0w, fp->a0x, fp->a1w, fp->a1x);
-
-        printf("LB0: %08lx  LT0: %08lx  LC0: %08lx\n", fp->lb0, fp->lt0, fp->lc0);
-        printf("LB1: %08lx  LT1: %08lx  LC1: %08lx\n", fp->lb1, fp->lt1, fp->lc1);
-        printf("B0: %08lx  L0: %08lx  M0: %08lx  I0: %08lx\n", fp->b0, fp->l0, fp->m0, fp->i0);
-        printf("B1: %08lx  L1: %08lx  M1: %08lx  I1: %08lx\n", fp->b1, fp->l1, fp->m1, fp->i1);
-        printf("B2: %08lx  L2: %08lx  M2: %08lx  I2: %08lx\n", fp->b2, fp->l2, fp->m2, fp->i2);
-        printf("B3: %08lx  L3: %08lx  M3: %08lx  I3: %08lx\n", fp->b3, fp->l3, fp->m3, fp->i3);
-}
-
-static const char *trap_to_string(int trapnr)
-{
-	switch (trapnr) {
-	case VEC_MISALI_D:
-		return "Data access misaligned";
-	case VEC_MISALI_I:
-		return "Instruction fetch misaligned";
-	case VEC_CPLB_I_M:
-		return "Instruction fetch CPLB miss";
-	}
-	return NULL;
-}
-
-void trap_c (struct pt_regs *regs)
-{
-	uint32_t trapnr = (regs->seqstat) & SEQSTAT_EXCAUSE;
-	const char *str;
-
-	printf("Exception occured!\n\n");
-
-	str = trap_to_string(trapnr);
-	if (str)
-		printf("%s\n", str);
-	printf("code=[0x%x]\n", trapnr);
-
-	dump_regs(regs);
-
-	printf("\nPlease reset the board\n");
-
-	restart_machine();
-}
-
-void blackfin_irq_panic(int reason, struct pt_regs *regs)
-{
-	printf("\n\nException: IRQ 0x%x entered\n", reason);
-	dump_regs(regs);
-	printf("Unhandled IRQ or exceptions!\n");
-	printf("Please reset the board \n");
-
-	restart_machine();
-}
-
diff --git a/arch/blackfin/lib/udivsi3.S b/arch/blackfin/lib/udivsi3.S
deleted file mode 100644
index def52cb1d5..0000000000
--- a/arch/blackfin/lib/udivsi3.S
+++ /dev/null
@@ -1,294 +0,0 @@
-/*
- * File:         arch/blackfin/lib/udivsi3.S
- * Based on:
- * Author:
- *
- * Created:
- * Description:
- *
- * Rev:          $Id: udivsi3.S 2795 2007-03-05 06:25:33Z cooloney $
- *
- * Modified:
- *               Copyright 2004-2006 Analog Devices Inc.
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#define CARRY AC0
-
-#ifdef CONFIG_ARITHMETIC_OPS_L1
-.section .l1.text
-#else
-.text
-#endif
-
-
-.globl ___udivsi3;
-
-___udivsi3:
-  CC = R0 < R1 (IU);    /* If X < Y, always return 0 */
-  IF CC JUMP .Lreturn_ident;
-
-  R2 = R1 << 16;
-  CC = R2 <= R0 (IU);
-  IF CC JUMP .Lidents;
-
-  R2 = R0 >> 31;       /* if X is a 31-bit number */
-  R3 = R1 >> 15;       /* and Y is a 15-bit number */
-  R2 = R2 | R3;        /* then it's okay to use the DIVQ builtins (fallthrough to fast)*/
-  CC = R2;
-  IF CC JUMP .Ly_16bit;
-
-/* METHOD 1: FAST DIVQ
-   We know we have a 31-bit dividend, and 15-bit divisor so we can use the
-   simple divq approach (first setting AQ to 0 - implying unsigned division,
-   then 16 DIVQ's).
-*/
-
-  AQ = CC;             /* Clear AQ (CC==0) */
-
-/* ISR States: When dividing two integers (32.0/16.0) using divide primitives,
-   we need to shift the dividend one bit to the left.
-   We have already checked that we have a 31-bit number so we are safe to do
-   that.
-*/
-  R0 <<= 1;
-  DIVQ(R0, R1); // 1
-  DIVQ(R0, R1); // 2
-  DIVQ(R0, R1); // 3
-  DIVQ(R0, R1); // 4
-  DIVQ(R0, R1); // 5
-  DIVQ(R0, R1); // 6
-  DIVQ(R0, R1); // 7
-  DIVQ(R0, R1); // 8
-  DIVQ(R0, R1); // 9
-  DIVQ(R0, R1); // 10
-  DIVQ(R0, R1); // 11
-  DIVQ(R0, R1); // 12
-  DIVQ(R0, R1); // 13
-  DIVQ(R0, R1); // 14
-  DIVQ(R0, R1); // 15
-  DIVQ(R0, R1); // 16
-  R0 = R0.L (Z);
-  RTS;
-
-.Ly_16bit:
-  /* We know that the upper 17 bits of Y might have bits set,
-  ** or that the sign bit of X might have a bit. If Y is a
-  ** 16-bit number, but not bigger, then we can use the builtins
-  ** with a post-divide correction.
-  ** R3 currently holds Y>>15, which means R3's LSB is the
-  ** bit we're interested in.
-  */
-
-  /* According to the ISR, to use the Divide primitives for
-  ** unsigned integer divide, the useable range is 31 bits
-  */
-  CC = ! BITTST(R0, 31);
-
-  /* IF condition is true we can scale our inputs and use the divide primitives,
-  ** with some post-adjustment
-  */
-  R3 += -1;		/* if so, Y is 0x00008nnn */
-  CC &= AZ;
-
-  /* If condition is true we can scale our inputs and use the divide primitives,
-  ** with some post-adjustment
-  */
-  R3 = R1 >> 1;		/* Pre-scaled divisor for primitive case */
-  R2 = R0 >> 16;
-
-  R2 = R3 - R2;		/* shifted divisor < upper 16 bits of dividend */
-  CC &= CARRY;
-  IF CC JUMP .Lshift_and_correct;
-
-  /* Fall through to the identities */
-
-/* METHOD 2: identities and manual calculation
-   We are not able to use the divide primites, but may still catch some special
-   cases.
-*/
-.Lidents:
-  /* Test for common identities. Value to be returned is placed in R2. */
-  CC = R0 == 0;        /* 0/Y => 0 */
-  IF CC JUMP .Lreturn_r0;
-  CC = R0 == R1;       /* X==Y => 1 */
-  IF CC JUMP .Lreturn_ident;
-  CC = R1 == 1;        /* X/1 => X */
-  IF CC JUMP .Lreturn_ident;
-
-  R2.L = ONES R1;
-  R2 = R2.L (Z);
-  CC = R2 == 1;
-  IF CC JUMP .Lpower_of_two;
-
-  [--SP] = (R7:5);                /* Push registers R5-R7 */
-
-  /* Idents don't match. Go for the full operation. */
-
-
-  R6 = 2;                         /* assume we'll shift two */
-  R3 = 1;
-
-  P2 = R1;
-                                  /* If either R0 or R1 have sign set, */
-                                  /* divide them by two, and note it's */
-                                  /* been done. */
-  CC = R1 < 0;
-  R2 = R1 >> 1;
-  IF CC R1 = R2;                  /* Possibly-shifted R1 */
-  IF !CC R6 = R3;                 /* R1 doesn't, so at most 1 shifted */
-
-  P0 = 0;
-  R3 = -R1;
-  [--SP] = R3;
-  R2 = R0 >> 1;
-  R2 = R0 >> 1;
-  CC = R0 < 0;
-  IF CC P0 = R6;                  /* Number of values divided */
-  IF !CC R2 = R0;                 /* Shifted R0 */
-
-                                  /* P0 is 0, 1 (NR/=2) or 2 (NR/=2, DR/=2) */
-
-                                  /* r2 holds Copy dividend  */
-  R3 = 0;                         /* Clear partial remainder */
-  R7 = 0;                         /* Initialise quotient bit */
-
-  P1 = 32;                        /* Set loop counter */
-  LSETUP(.Lulst, .Lulend) LC0 = P1; /* Set loop counter */
-.Lulst:  R6 = R2 >> 31;             /* R6 = sign bit of R2, for carry */
-       R2 = R2 << 1;              /* Shift 64 bit dividend up by 1 bit */
-       R3 = R3 << 1 || R5 = [SP];
-       R3 = R3 | R6;              /* Include any carry */
-       CC = R7 < 0;               /* Check quotient(AQ) */
-                                  /* If AQ==0, we'll sub divisor */
-       IF CC R5 = R1;             /* and if AQ==1, we'll add it. */
-       R3 = R3 + R5;              /* Add/sub divsor to partial remainder */
-       R7 = R3 ^ R1;              /* Generate next quotient bit */
-
-       R5 = R7 >> 31;             /* Get AQ */
-       BITTGL(R5, 0);             /* Invert it, to get what we'll shift */
-.Lulend: R2 = R2 + R5;              /* and "shift" it in. */
-
-  CC = P0 == 0;                   /* Check how many inputs we shifted */
-  IF CC JUMP .Lno_mult;            /* if none... */
-  R6 = R2 << 1;
-  CC = P0 == 1;
-  IF CC R2 = R6;                  /* if 1, Q = Q*2 */
-  IF !CC R1 = P2;                 /* if 2, restore stored divisor */
-
-  R3 = R2;                        /* Copy of R2 */
-  R3 *= R1;                       /* Q * divisor */
-  R5 = R0 - R3;                   /* Z = (dividend - Q * divisor) */
-  CC = R1 <= R5 (IU);             /* Check if divisor <= Z? */
-  R6 = CC;                        /* if yes, R6 = 1 */
-  R2 = R2 + R6;                   /* if yes, add one to quotient(Q) */
-.Lno_mult:
-  SP += 4;
-  (R7:5) = [SP++];                /* Pop registers R5-R7 */
-  R0 = R2;                        /* Store quotient */
-  RTS;
-
-.Lreturn_ident:
-  CC = R0 < R1 (IU);    /* If X < Y, always return 0 */
-  R2 = 0;
-  IF CC JUMP .Ltrue_return_ident;
-  R2 = -1 (X);         /* X/0 => 0xFFFFFFFF */
-  CC = R1 == 0;
-  IF CC JUMP .Ltrue_return_ident;
-  R2 = -R2;            /* R2 now 1 */
-  CC = R0 == R1;       /* X==Y => 1 */
-  IF CC JUMP .Ltrue_return_ident;
-  R2 = R0;             /* X/1 => X */
-  /*FALLTHRU*/
-
-.Ltrue_return_ident:
-  R0 = R2;
-.Lreturn_r0:
-  RTS;
-
-.Lpower_of_two:
-  /* Y has a single bit set, which means it's a power of two.
-  ** That means we can perform the division just by shifting
-  ** X to the right the appropriate number of bits
-  */
-
-  /* signbits returns the number of sign bits, minus one.
-  ** 1=>30, 2=>29, ..., 0x40000000=>0. Which means we need
-  ** to shift right n-signbits spaces. It also means 0x80000000
-  ** is a special case, because that *also* gives a signbits of 0
-  */
-
-  R2 = R0 >> 31;
-  CC = R1 < 0;
-  IF CC JUMP .Ltrue_return_ident;
-
-  R1.l = SIGNBITS R1;
-  R1 = R1.L (Z);
-  R1 += -30;
-  R0 = LSHIFT R0 by R1.L;
-  RTS;
-
-/* METHOD 3: PRESCALE AND USE THE DIVIDE PRIMITIVES WITH SOME POST-CORRECTION
-  Two scaling operations are required to use the divide primitives with a
-  divisor > 0x7FFFF.
-  Firstly (as in method 1) we need to shift the dividend 1 to the left for
-  integer division.
-  Secondly we need to shift both the divisor and dividend 1 to the right so
-  both are in range for the primitives.
-  The left/right shift of the dividend does nothing so we can skip it.
-*/
-.Lshift_and_correct:
-  R2 = R0;
-  // R3 is already R1 >> 1
-  CC=!CC;
-  AQ = CC;                        /* Clear AQ, got here with CC = 0 */
-  DIVQ(R2, R3); // 1
-  DIVQ(R2, R3); // 2
-  DIVQ(R2, R3); // 3
-  DIVQ(R2, R3); // 4
-  DIVQ(R2, R3); // 5
-  DIVQ(R2, R3); // 6
-  DIVQ(R2, R3); // 7
-  DIVQ(R2, R3); // 8
-  DIVQ(R2, R3); // 9
-  DIVQ(R2, R3); // 10
-  DIVQ(R2, R3); // 11
-  DIVQ(R2, R3); // 12
-  DIVQ(R2, R3); // 13
-  DIVQ(R2, R3); // 14
-  DIVQ(R2, R3); // 15
-  DIVQ(R2, R3); // 16
-
-  /* According to the Instruction Set Reference:
-     To divide by a divisor > 0x7FFF,
-     1. prescale and perform divide to obtain quotient (Q) (done above),
-     2. multiply quotient by unscaled divisor (result M)
-     3. subtract the product from the divident to get an error (E = X - M)
-     4. if E < divisor (Y) subtract 1, if E > divisor (Y) add 1, else return quotient (Q)
-   */
-  R3 = R2.L (Z);		/* Q = X' / Y' */
-  R2 = R3;		/* Preserve Q */
-  R2 *= R1;		/* M = Q * Y */
-  R2 = R0 - R2;		/* E = X - M */
-  R0 = R3;		/* Copy Q into result reg */
-
-/* Correction: If result of the multiply is negative, we overflowed
-   and need to correct the result by subtracting 1 from the result.*/
-  R3 = 0xFFFF (Z);
-  R2 = R2 >> 16;		/* E >> 16 */
-  CC = R2 == R3;
-  R3 = 1 ;
-  R1 = R0 - R3;
-  IF CC R0 = R1;
-  RTS;
diff --git a/arch/blackfin/lib/umodsi3.S b/arch/blackfin/lib/umodsi3.S
deleted file mode 100644
index c0b852f55a..0000000000
--- a/arch/blackfin/lib/umodsi3.S
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * File:         arch/blackfin/lib/umodsi3.S
- * Based on:
- * Author:
- *
- * Created:
- * Description:  libgcc1 routines for Blackfin 5xx
- *
- * Rev:          $Id: umodsi3.S 2769 2007-02-19 16:45:53Z hennerich $
- *
- * Modified:
- *               Copyright 2004-2006 Analog Devices Inc.
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifdef CONFIG_ARITHMETIC_OPS_L1
-.section .l1.text
-#else
-.text
-#endif
-
-.extern ___udivsi3;
-.globl	___umodsi3
-___umodsi3:
-
-	CC=R0==0;
-	IF CC JUMP .LRETURN_R0;		/* Return 0, if NR == 0 */
-	CC= R1==0;
-	IF CC JUMP .LRETURN_ZERO_VAL;	/* Return 0, if DR == 0 */
-	CC=R0==R1;
-	IF CC JUMP .LRETURN_ZERO_VAL;	/* Return 0, if NR == DR */
-	CC = R1 == 1;
-	IF CC JUMP .LRETURN_ZERO_VAL;	/* Return 0, if  DR == 1 */
-	CC = R0<R1 (IU);
-	IF CC JUMP .LRETURN_R0;		/* Return dividend (R0),IF NR<DR */
-
-	[--SP] = (R7:6);		/* Push registers and */
-	[--SP] = RETS;			/* Return address */
-	R7 = R0;			/* Copy of R0 */
-	R6 = R1;
-	SP += -12;			/* Should always provide this space */
-	CALL ___udivsi3;		/* Compute unsigned quotient using ___udiv32()*/
-	SP += 12;
-	R0 *= R6;			/* Quotient * divisor */
-	R0 = R7 - R0;			/* Dividend - (quotient * divisor) */
-	RETS = [SP++];			/* Pop return address */
-	( R7:6) = [SP++];		/* And registers */
-	RTS;				/* Return remainder */
-.LRETURN_ZERO_VAL:
-	R0 = 0;
-.LRETURN_R0:
-	RTS;
diff --git a/arch/blackfin/lib/umulsi3_highpart.S b/arch/blackfin/lib/umulsi3_highpart.S
deleted file mode 100644
index aac8218fb2..0000000000
--- a/arch/blackfin/lib/umulsi3_highpart.S
+++ /dev/null
@@ -1,23 +0,0 @@
-.align 2
-.global ___umulsi3_highpart;
-.type ___umulsi3_highpart, STT_FUNC;
-
-#ifdef CONFIG_ARITHMETIC_OPS_L1
-.section .l1.text
-#else
-.text
-#endif
-
-___umulsi3_highpart:
-	R2 = R1.H * R0.H, R3 = R1.L * R0.H (FU);
-	R0 = R1.L * R0.L, R1 = R1.H * R0.L (FU);
-	R0 >>= 16;
-	/* Unsigned multiplication has the nice property that we can
-	   ignore carry on this first addition.  */
-	R0 = R0 + R3;
-	R0 = R0 + R1;
-	cc = ac0;
-	R1 = cc;
-	R1 = PACK(R1.l,R0.h);
-	R0 = R1 + R2;
-	RTS;
-- 
2.23.0


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