The voltage of the ethernet phy needs to be stable before de-asserting the reset pin. Thus set the phy-reset-duration to 10 ms. Signed-off-by: Stefan Riedmueller <s.riedmueller@xxxxxxxxx> --- arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi b/arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi index 8fde27bd0c17..1d39368165db 100644 --- a/arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi +++ b/arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi @@ -110,6 +110,7 @@ phy-handle = <ðphy>; phy-mode = "rgmii"; phy-reset-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; + phy-reset-duration = <10>; /* in msecs */ status = "disabled"; mdio { -- 2.7.4 _______________________________________________ barebox mailing list barebox@xxxxxxxxxxxxxxxxxxx http://lists.infradead.org/mailman/listinfo/barebox