[PATCH 2/2] ARM: dts: imx6ul: phycore: Reduce eth drive strength

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

 



Reduce the drive strength for the MDC, MDIO and TX pins of fec1 to improve
signal quality and EMC. Also disable internal pull ups on the MDC and
MDIO pins.

Signed-off-by: Stefan Riedmueller <s.riedmueller@xxxxxxxxx>
---
 arch/arm/dts/imx6ul-phytec-phycore-som.dtsi | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi b/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi
index 0ec7eae1eff0..c7c657bcd409 100644
--- a/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi
+++ b/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi
@@ -159,16 +159,16 @@
 
 		pinctrl_enet1: enet1grp {
 			fsl,pins = <
-				MX6UL_PAD_GPIO1_IO07__ENET1_MDC		0x1b0b0
-				MX6UL_PAD_GPIO1_IO06__ENET1_MDIO	0x1b0b0
+				MX6UL_PAD_GPIO1_IO07__ENET1_MDC		0x10010
+				MX6UL_PAD_GPIO1_IO06__ENET1_MDIO	0x10010
 				MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN	0x1b0b0
 				MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER	0x1b0b0
 				MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00	0x1b0b0
 				MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01	0x1b0b0
-				MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN	0x1b0b0
-				MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00	0x1b0b0
-				MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01	0x1b0b0
-				MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1	0x4001b031
+				MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN	0x1b010
+				MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00	0x1b010
+				MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01	0x1b010
+				MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1	0x4001b010
 			>;
 		};
 
-- 
2.7.4


_______________________________________________
barebox mailing list
barebox@xxxxxxxxxxxxxxxxxxx
http://lists.infradead.org/mailman/listinfo/barebox



[Index of Archives]     [Linux Embedded]     [Linux USB Devel]     [Linux Audio Users]     [Yosemite News]     [Linux Kernel]     [Linux SCSI]     [XFree86]

  Powered by Linux