On Thu, Jun 13, 2019 at 8:14 AM Yazdani, Reyhaneh <RYazdani@xxxxxxxxxxxxxx> wrote: > > Hello Everyone, > > I am trying to bringup Barebox on i.MX8MM-evk. > > I have followed all the commits related to the i.MX8MQ and added proper files > and changes for i.MX8MM-evk board. > > The problem is Barebox stops at "ddrc_phy_wait_training_complete" function, > exactly at sub-function "ddrc_phy_get_message". The read-value from the > > phy + DDRC_PHY_REG(0xd0004) is not correct, and it remains in while loop. > > I used the ddr_init and ddrphy_train files produced from mscale_ddr_tool of NXP, > and even compared with the value from U-boot. All are similar. > > Does any body have an idea what would be the problem? > What about DDR PHY firmware? Is it the same as in working U-boot image? From what you describe it sounds that DDR PHY is not responding, so I am wondering if DDR firmware is running. Also, did you check that various memory offsets in, say arch/arm/mach-imx/include/mach/imx8-ddrc.h are valid for i.MX8MM and are not values that MQ specific? Another thing to debug this would be to trace all of the register reads/writes in working U-Boot vs Barebox and see what the difference is. Anyway, just my 2 cents. Thanks, Andrey Smirnov _______________________________________________ barebox mailing list barebox@xxxxxxxxxxxxxxxxxxx http://lists.infradead.org/mailman/listinfo/barebox
