On Tue, May 21, 2019 at 8:56 AM Ahmad Fatoum <a.fatoum@xxxxxxxxxxxxxx> wrote:
>
> barebox has inherited the clk_set_parent(ldb_diN_sel, pll5_video_div)
> from upstream kernel commit 32f3b8da22 ("ARM i.MX6q: set the LDB serial
> clock parent to the video PLL"), where it was enabled for all i.MX6Q
> revisions after 1.0. It was applied whenever CONFIG_DRIVER_VIDEO_IMX_IPUV3
> was defined.
>
> The kernel removed this reparenting again as a preventive measure
> against ERR009219 in 03d576f202 ("clk: imx6: Make the LDB_DI0 and
> LDB_DI1 clocks read-only").
>
> As the kernel used the device tree compatible, which is the same
> for e.g. i.MX6Solo and DualLite, but barebox queried ANATOP which
> lists different CPU types for i.MX6Solo and DualLite and because
> i.MX6QuadPlus wasn't supported at first, barebox grew to do
> the reparenting on the odd set of:
> - Quad and Dual rev >1.0
> - DualLite
> - Solo rev >1.0
> - QuadPlus and DualPlus rev >1.0
>
> On all of these, except for the QuadPlus and the DualPlus, this
> reparenting may glitch the LDB so that it permanently locks up.
>
> By removing the reparenting in this commit, producing this glitch is
> avoided, unless the device tree[1] reinstates the old behavior:
>
> &clks {
> assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
> <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
> assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
> <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>;
> };
>
> Follow-up patches will explicitly check for this and do the reparenting
> in a glitch-free manner.
>
> As of v2019.03.0, following mainline boards are potentially broken
> by this (i.e. they're supported by barebox, are in the list above,
> had a LDB enabled and might be defining CONFIG_DRIVER_VIDEO_IMX_IPUV3):
> - imx6qdl-zii-rdu2.dtsi
This particular patch does break a non 6Q+ version of RDU2, but the
follow up ones in the series fix it, so it seems that no action is
really necessary on my part.
Thanks,
Andrey Smirnov
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