Re: [PATCH v2] usb: dwc3: Toggle GCTL.CORESOFTRESET as a first step

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On Wed, Mar 13, 2019 at 12:25:19AM -0700, Andrey Smirnov wrote:
> Toggle GCTL.CORESOFTRESET before trying to access any of the block's
> registers. Without this additional step, first read of DWC3_GHWPARAMS*
> that follows results in assertion of GSTS.CSRTIMEOUT and IP block
> stuck in a non-functional state.
> 
> Note that all above has only been observerd on i.MX8MQ (ZII Zest
> board) for USB1 controller. USB2 doesn't seem to be affected by this.
> 
> Signed-off-by: Andrey Smirnov <andrew.smirnov@xxxxxxxxx>
> ---

Applied, thanks

Sascha


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