[PATCH v2 62/65] PCI: dwc: Enable write permission for Class Code, Interrupt Pin updates

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Port of a Linux commit d91dfe5054d4f2c424bd70ca34fc3328ee179f20

  dw_pcie_setup_rc() contains fixes to update the Class Code and Interrupt
  Pin registers, but the fixes don't actually work because these registers
  are read-only.

  Enable write permission before updating the Class Code and Interrupt
  Pin.

  Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@xxxxxxx>
  Signed-off-by: Bjorn Helgaas <bhelgaas@xxxxxxxxxx>
  Acked-by: Joao Pinto <jpinto@xxxxxxxxxxxx>
  Acked-by: Roy Zang <tie-fei.zang@xxxxxxxxxxxxx>

Signed-off-by: Andrey Smirnov <andrew.smirnov@xxxxxxxxx>
---
 drivers/pci/pcie-designware-host.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/pci/pcie-designware-host.c b/drivers/pci/pcie-designware-host.c
index e98560818..b42d2ac93 100644
--- a/drivers/pci/pcie-designware-host.c
+++ b/drivers/pci/pcie-designware-host.c
@@ -403,8 +403,12 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
 
 	dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0);
 
-	/* Program correct class for RC */
+	/* Enable write permission for the DBI read-only register */
+	dw_pcie_dbi_ro_wr_en(pci);
+        /* Program correct class for RC */
 	dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI);
+	/* Better disable write permission right after the update */
+	dw_pcie_dbi_ro_wr_dis(pci);
 
 	dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val);
 	val |= PORT_LOGIC_SPEED_CHANGE;
-- 
2.19.1


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