[PATCH v2 52/65] PCI: dwc: all: Modify dbi accessors to take dbi_base as argument

[Andrey Smirnov <andrew.smirnov@xxxxxxxxx>]

Port of a Linux commit b50b2db266d8a8c303e8d88590c6416dfe576c6c

  dwc has 2 dbi address space labeled dbics and dbics2. The existing helper
  to access dbi address space can access only dbics. However dbics2 has to
  be accessed for programming the BAR registers in the case of EP mode. This
  is in preparation for adding EP mode support to dwc driver.

  Signed-off-by: Kishon Vijay Abraham I <kishon@xxxxxx>
  Signed-off-by: Bjorn Helgaas <bhelgaas@xxxxxxxxxx>
  Acked-by: Niklas Cassel <niklas.cassel@xxxxxxxx>
  Cc: Jingoo Han <jingoohan1@xxxxxxxxx>
  Cc: Joao Pinto <Joao.Pinto@xxxxxxxxxxxx>

Signed-off-by: Andrey Smirnov <andrew.smirnov@xxxxxxxxx>
---
 drivers/pci/pcie-designware.c | 13 +++++++------
 drivers/pci/pcie-designware.h | 19 +++++++++++++++----
 2 files changed, 22 insertions(+), 10 deletions(-)

diff --git a/drivers/pci/pcie-designware.c b/drivers/pci/pcie-designware.c
index 6687fff8b..25f9f8df1 100644
--- a/drivers/pci/pcie-designware.c
+++ b/drivers/pci/pcie-designware.c
@@ -68,20 +68,21 @@ int dw_pcie_write(void __iomem *addr, int size, u32 val)
 	return PCIBIOS_SUCCESSFUL;
 }
 
-u32 dw_pcie_readl_dbi(struct dw_pcie *pci, u32 reg)
+u32 __dw_pcie_readl_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg)
 {
 	if (pci->ops->readl_dbi)
-		return pci->ops->readl_dbi(pci, reg);
+		return pci->ops->readl_dbi(pci, base, reg);
 
-	return readl(pci->dbi_base + reg);
+	return readl(base + reg);
 }
 
-void dw_pcie_writel_dbi(struct dw_pcie *pci, u32 reg, u32 val)
+void __dw_pcie_writel_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg,
+			  u32 val)
 {
 	if (pci->ops->writel_dbi)
-		pci->ops->writel_dbi(pci, reg, val);
+		pci->ops->writel_dbi(pci, base, reg, val);
 	else
-		writel(val, pci->dbi_base + reg);
+		writel(val, base + reg);
 }
 
 static u32 dw_pcie_readl_unroll(struct dw_pcie *pci, u32 index, u32 reg)
diff --git a/drivers/pci/pcie-designware.h b/drivers/pci/pcie-designware.h
index 97c8b0b3c..10deb577a 100644
--- a/drivers/pci/pcie-designware.h
+++ b/drivers/pci/pcie-designware.h
@@ -134,8 +134,9 @@ struct pcie_port {
 };
 
 struct dw_pcie_ops {
-	u32     (*readl_dbi)(struct dw_pcie *pcie, u32 reg);
-	void    (*writel_dbi)(struct dw_pcie *pcie, u32 reg, u32 val);
+	u32     (*readl_dbi)(struct dw_pcie *pcie, void __iomem *base, u32 reg);
+	void    (*writel_dbi)(struct dw_pcie *pcie, void __iomem *base, u32 reg,
+			      u32 val);
 	int     (*link_up)(struct dw_pcie *pcie);
 };
 
@@ -155,12 +156,22 @@ int dw_pcie_write(void __iomem *addr, int size, u32 val);
 void dw_pcie_setup_rc(struct pcie_port *pp);
 int dw_pcie_host_init(struct pcie_port *pp);
 
-u32 dw_pcie_readl_dbi(struct dw_pcie *pci, u32 reg);
-void dw_pcie_writel_dbi(struct dw_pcie *pci, u32 reg, u32 val);
+u32 __dw_pcie_readl_dbi(struct dw_pcie *pci, void __iomem *addr, u32 reg);
+void __dw_pcie_writel_dbi(struct dw_pcie *pci, void __iomem *addr, u32 reg, u32 val);
 int dw_pcie_link_up(struct dw_pcie *pci);
 int dw_pcie_wait_for_link(struct dw_pcie *pci);
 void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index,
 			       int type, u64 cpu_addr, u64 pci_addr,
 			       u32 size);
 void dw_pcie_setup(struct dw_pcie *pci);
+
+static inline void dw_pcie_writel_dbi(struct dw_pcie *pci, u32 reg, u32 val)
+{
+	__dw_pcie_writel_dbi(pci, pci->dbi_base, reg, val);
+}
+
+static inline u32 dw_pcie_readl_dbi(struct dw_pcie *pci, u32 reg)
+{
+	return  __dw_pcie_readl_dbi(pci, pci->dbi_base, reg);
+}
 #endif /* _PCIE_DESIGNWARE_H */
-- 
2.19.1


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