Hi,
On Thu, Nov 08, 2018 at 03:34:29PM +0100, perachet7@xxxxxxxxx wrote:
> Hi,
>
> We found setting a clock rate which has already been set, rk3188 (radxa rock
> pro) bails out. This is a quick fix only. Underlying situation not (yet)
> investigated: why it is even trying to set it to the same rate again. It
> remains to state that some but not all rrpro boards exhibit this behaviour, no
> other rk3188 boards have been tested.
>
> Signed-off-by: P. Rachet <perachet7@xxxxxxxxx>
> ---
> drivers/clk/rockchip/clk-pll.c | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c
> index f0dc12091..690da4afb 100644
> --- a/drivers/clk/rockchip/clk-pll.c
> +++ b/drivers/clk/rockchip/clk-pll.c
> @@ -164,6 +164,11 @@ static int rockchip_rk3066_pll_set_rate(struct clk *hw,
> unsigned long drate,
> int cur_parent;
> int ret;
>
> + if (old_rate == drate) {
> + pr_debug("%s: not changing rate, old == new rate (clk/old/new/parent):
> %s/%lu/%lu/%lu\n", __func__, __clk_get_name(hw), old_rate, drate, prate);
> + return 0;
> + }
> +
The patch is whitespace damaged. I applied it manually this time, but
please consider using git-send-email next time. It just does it right™
Sascha
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