Re: Help requested with Barebox on Globalscale Mirabox

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Hi Uwe,

On 2018-08-06 19:36, Uwe Kleine-König wrote:
Hello Leigh,

On Tue, Jul 31, 2018 at 02:21:04PM +0100, Leigh Brown wrote:
Have I missed any steps?  Any help would be greatly appreciated.

Looks good.

Which revision are you on (i.e. git rev-parse @ in your barebox copy)?
What is currently running on the device?

I was running against the same revision as you tried (445a7f).  I'm now
running against the latest revision (3307e8) with the same issue.

Do you get an U when applying this patch?:
[snip patch]

I did. Thanks very much for that hint, it helped me debug the issue. I am
booting from the UART as follows:

scripts/kwboot -t -b images/barebox-globalscale-mirabox.img -B 115200 /dev/ttyUSB0

I believe the issue is that in arch/arm/mach-mvebu/common.c the function
armada_370_xp_barebox_entry() calls mvebu_remap_registers() before the stack is
set up (it looks like the SP points somewhere in the SRAM range).  As
mvebu_remap_registers() as compiled by my version of gcc uses the stack, it fails
to return.

Making mvebu_remap_registers() inline fixes the issue, as per the following
patch:

diff --git a/arch/arm/mach-mvebu/common.c b/arch/arm/mach-mvebu/common.c
index 83aeb41ae..588cef515 100644
--- a/arch/arm/mach-mvebu/common.c
+++ b/arch/arm/mach-mvebu/common.c
@@ -183,11 +183,15 @@ mem_initcall(mvebu_meminit);
  * There no way to determine internal registers base address
  * safely later on, as the remap register itself is within the
  * internal registers.
+ *
+ * As this function may be called before we have a working stack,
+ * make it inline to avoid the possibility of using the stack.
+ *
  */
 #define MVEBU_BRIDGE_REG_BASE		0x20000
 #define DEVICE_INTERNAL_BASE_ADDR	(MVEBU_BRIDGE_REG_BASE + 0x80)

-static void mvebu_remap_registers(void)
+static inline void mvebu_remap_registers(void)
 {
 	void __iomem *base = mvebu_get_initial_int_reg_base();


I just tried 7ba0f2d29959256025ece9ae961a6c3421445a7f on my ReadyNAS 104
which has an armada370, too.

I hangs when using second-stage booting from the Vendor U-Boot after:

barebox 2018.07.0-00139-g7ba0f2d29959-dirty #50 Mon Aug 6 20:27:11 CEST 2018


	Board: Marvell Armada 370/XP
	SoC: Marvell 6710 rev 1
	mdio_bus: miibus0: probed
	eth1: got preset MAC address: 28:c6:8e:36:df:57

When enabling DEBUG_INITCALLS I got a prompt, hmm. Didn't debug that
further.

Best regards
Uwe

Once I got past that issue I also had an issue in barebox_multi_pbl_start. I think the following patch is the right solution, but I'm not 100% sure. It
certainly makes it work for me.

diff --git a/arch/arm/cpu/uncompress.c b/arch/arm/cpu/uncompress.c
index b07087e4c..5ee80da9d 100644
--- a/arch/arm/cpu/uncompress.c
+++ b/arch/arm/cpu/uncompress.c
@@ -50,7 +66,7 @@ void __noreturn barebox_multi_pbl_start(unsigned long membase,
 	void *pg_start;
 	unsigned long pc = get_pc();

-	image_end = (void *)&image_end_marker + global_variable_offset();
+	image_end = (void *)&image_end_marker;

 	if (IS_ENABLED(CONFIG_PBL_RELOCATABLE)) {
 		/*
@@ -63,6 +79,8 @@ void __noreturn barebox_multi_pbl_start(unsigned long membase,
 		else
 			relocate_to_adr(membase);
 	}
+	else
+		image_end += global_variable_offset();

 	/*
* image_end is the image_end_marker defined above. It is the last location

Anyway, with the following two fixes I now have it booting on my Mirabox:

barebox 2018.07.0-00143-gf9fc8254b-dirty #53 Thu Aug 9 16:11:01 BST 2018


Board: Marvell Armada 370/XP
SoC: Marvell 6710 rev 1
mdio_bus: miibus0: probed
pci: pci_scan_bus for bus 0
pci: last_io = 0xffe00000, last_mem = 0xe0000000, last_mem_pref = 0x00000000
pci: pci_scan_bus returning with max=01
pci: pci_scan_bus for bus 1
pci: last_io = 0xffe10000, last_mem = 0xe2000000, last_mem_pref = 0x00000000
pci: pci_scan_bus returning with max=02
malloc space: 0x0fefe600 -> 0x1fdfcbff (size 255 MiB)
environment load /dev/env0: No such file or directory
Maybe you have to create the partition.
running /env/bin/init...
/env/bin/init not found
barebox:/

Thanks again for your help. I'll now figure out how to get NAND support working.

Regards,

Leigh.

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