Do not touch PLL_BYPASS bit as a part of clk_pll3_enable/disable execution. For a number of platforms (e.g. Vybrid, i.MX6SL) PLL_BYPASS is specified as a bit controlling a clock MUX represented by a dedicated 'struct clk'. Altering that bit as a part of clk_pll3_enable/disable is equivalent to calling clk_set_parent() and it makes in the following code: clk_enable(clk_disable(<some pll>)) change clock chain instead of being a no-op. Signed-off-by: Andrey Smirnov <andrew.smirnov@xxxxxxxxx> --- drivers/clk/imx/clk-pllv3.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c index 6d4399b..a14d36e 100644 --- a/drivers/clk/imx/clk-pllv3.c +++ b/drivers/clk/imx/clk-pllv3.c @@ -56,7 +56,6 @@ static int clk_pllv3_enable(struct clk *clk) int timeout = 10000; val = readl(pll->base); - val &= ~BM_PLL_BYPASS; if (pll->powerup_set) val |= pll->power_bit; else @@ -88,7 +87,6 @@ static void clk_pllv3_disable(struct clk *clk) val &= ~BM_PLL_ENABLE; writel(val, pll->base); - val |= BM_PLL_BYPASS; if (pll->powerup_set) val &= ~pll->power_bit; else -- 2.9.4 _______________________________________________ barebox mailing list barebox@xxxxxxxxxxxxxxxxxxx http://lists.infradead.org/mailman/listinfo/barebox
