Everyone,
It looks like my test setup was somehow contaminated -- possibly by
using JTAG to initalize SoC and upload Barebox binary -- so
21921f7f419dfaabcd385595ada24f0352310f1a ("i.MX: vf610: Ramp CPU clock
to maximum frequency") didn't actually work as I thought it was and
instead it made Barebox not boot on Vybrid.
This patch series contains all of the changes I had to make in order
to make CPU clock switching work/"unbreak" Barebox on Vybrid.
Let me know if anything needs changing.
Thanks,
Andrey Smirnov
Andrey Smirnov (3):
clk-vf610: Mark all of CCSR muxes with CLK_OPS_PARENT_ENABLE
i.MX: clk-pllv3: Do not touch PLL_BYPASS bit
i.MX: clk: Remove imx_clk_pllv3_locked()
drivers/clk/imx/clk-pllv3.c | 26 --------------------------
drivers/clk/imx/clk-vf610.c | 28 ++++++++++++++++++++--------
drivers/clk/imx/clk.h | 4 ----
3 files changed, 20 insertions(+), 38 deletions(-)
--
2.9.4
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