On AT91 GPIOs default to being inputs, so we need to explicitly
configure CS gpio to being an output.
Signed-off-by: Andrey Smirnov <andrew.smirnov@xxxxxxxxx>
---
drivers/spi/atmel_spi.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/spi/atmel_spi.c b/drivers/spi/atmel_spi.c
index 68466ef..b183344 100644
--- a/drivers/spi/atmel_spi.c
+++ b/drivers/spi/atmel_spi.c
@@ -173,6 +173,8 @@ static int atmel_spi_setup(struct spi_device *spi)
struct spi_master *master = spi->master;
struct atmel_spi *as = to_atmel_spi(master);
+ int npcs_pin;
+ unsigned active = spi->mode & SPI_CS_HIGH;
u32 scbr, csr;
unsigned int bits = spi->bits_per_word;
unsigned long bus_hz;
@@ -184,6 +186,8 @@ static int atmel_spi_setup(struct spi_device *spi)
return -EINVAL;
}
+ npcs_pin = as->cs_pins[spi->chip_select];
+
if (bits < 8 || bits > 16) {
dev_dbg(&spi->dev,
"setup: invalid bits_per_word %u (8 to 16)\n",
@@ -236,7 +240,7 @@ static int atmel_spi_setup(struct spi_device *spi)
csr |= SPI_BF(DLYBS, 0);
csr |= SPI_BF(DLYBCT, 0);
- /* gpio_direction_output(npcs_pin, !(spi->mode & SPI_CS_HIGH)); */
+ gpio_direction_output(npcs_pin, !active);
dev_dbg(master->dev,
"setup: %lu Hz bpw %u mode 0x%x -> csr%d %08x\n",
bus_hz / scbr, bits, spi->mode, spi->chip_select, csr);
--
2.9.3
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