On 08/11/16 08:59, Steffen Trumtrar wrote:
Hi!
On Mon, Nov 07, 2016 at 05:56:51PM +0000, Ian Abbott wrote:
Hi everyone,
I'm using barebox 2016.10.0 with some custom BSP patches for my Cyclone V
socfpga based board. I've noticed that after issuing a reboot in Linux,
followed by an 'ifup eth0' command in barebox, I get a "eth0: MAC reset
timeout" error, which causes dwc_ether_init() to bail out early. My Linux
kernel is Linux 4.1.17, plus LTSI-4.1.17 patches, plus Altera patches from
linux-socfpga kernel branch socfpga-4.1.22-ltsi, in that order (git rebase
is a wonderful thing!).
FYI: I just tested on a Socrates board with Linux 4.9-rc3 and barebox 2016.08.0
and can not reproduce your problem. Does that always happen or just sometimes?
It always happens on my board. I could try reproducing it on a Socrates
board. I have a couple of Socrates version 1.2 boards and a Socrates
2.0 board, so I could try and reproduce the problem if I find time to
set it up.
My board is actually a prototype. The PHY clock was originally wired up
to completely the wrong pin on the FPGA (since it was based on an older
NiosII based design). It has been surgically altered so the PHY clock
is on a different wrong pin, but at least the new pin is clocked at the
correct frequency. This may or may not be related to my problem, but
the PHY seems to work OK before bringing up the MAC controller - miitool
shows it manages to establish a link at the physical level.
--
-=( Ian Abbott @ MEV Ltd. E-mail: <abbotti@xxxxxxxxx> )=-
-=( Web: http://www.mev.co.uk/ )=-
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