On Mon, Jun 20, 2016 at 03:34:06PM -0400, Michael D. Burkey wrote: > In a quest to support the new Variscite SOM's EEPROM based DDR > configuration, I am continuing to try to get all the pieces together. > > Now that I have the SOM actually booting from IRAM, I am actually > trying to get the "real" DDR configuration values out of the EEPROM on > the SOM. > > Which brings me to the next hurdle -- getting early I2C access up and running. > > Thanks to some pointers from Sascha, I have been working with the > fsl_i2c.c code that had already been used for this task on the mpc85xx > PPC platform, and while the I2C controller is essentially the same, > the clock tree setup, etc. for the iMX6 is quite different. The fsl_i2c.c driver as currently in arch/ppc/ needs the input clock frequency and some timer for a timeout loop. The timeout could be dropped from the loop which is ok for a early bringup driver. For the input clock frequency you can pass in the reset default value, statically compiled into the binary; no need to calculate it during runtime. I still think fsl_i2c.c is the way to go, but you could also you whatever else "early" variant of the driver, I wouldn't start from a driver implementing the Linux I2C API though. Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | _______________________________________________ barebox mailing list barebox@xxxxxxxxxxxxxxxxxxx http://lists.infradead.org/mailman/listinfo/barebox
