Add RAM timings for phyCORE-AM335x-R2 256MB RAM.
Signed-off-by: Teresa Remmet <t.remmet@xxxxxxxxx>
---
arch/arm/boards/phytec-som-am335x/lowlevel.c | 1 +
arch/arm/boards/phytec-som-am335x/ram-timings.h | 20 ++++++++++++++++++++
images/Makefile.am33xx | 6 ++++++
3 files changed, 27 insertions(+)
diff --git a/arch/arm/boards/phytec-som-am335x/lowlevel.c b/arch/arm/boards/phytec-som-am335x/lowlevel.c
index 8af450e..4240f40 100644
--- a/arch/arm/boards/phytec-som-am335x/lowlevel.c
+++ b/arch/arm/boards/phytec-som-am335x/lowlevel.c
@@ -124,6 +124,7 @@ PHYTEC_ENTRY_MLO(start_am33xx_phytec_phycore_sram_512mb, am335x_phytec_phycore_s
PHYTEC_ENTRY_MLO(start_am33xx_phytec_phycore_sram_2x512mb, am335x_phytec_phycore_som_mlo, PHYCORE_MT41J512M8125IT_2x512MB);
PHYTEC_ENTRY_MLO(start_am33xx_phytec_phycore_sram_1024mb, am335x_phytec_phycore_som_mlo, PHYCORE_IM8G16D3FBBG15EI_1024MB);
PHYTEC_ENTRY_MLO(start_am33xx_phytec_phycore_r2_sram_512mb, am335x_phytec_phycore_som_mlo, PHYCORE_R2_MT41K256M16TW107IT_512MB);
+PHYTEC_ENTRY_MLO(start_am33xx_phytec_phycore_r2_sram_256mb, am335x_phytec_phycore_som_mlo, PHYCORE_R2_MT41K128M16JT_256MB);
PHYTEC_ENTRY(start_am33xx_phytec_phycore_sdram, am335x_phytec_phycore_som);
PHYTEC_ENTRY(start_am33xx_phytec_phycore_no_spi_sdram, am335x_phytec_phycore_som_no_spi);
PHYTEC_ENTRY(start_am33xx_phytec_phycore_no_eeprom_sdram, am335x_phytec_phycore_som_no_eeprom);
diff --git a/arch/arm/boards/phytec-som-am335x/ram-timings.h b/arch/arm/boards/phytec-som-am335x/ram-timings.h
index b89d561..884874c 100644
--- a/arch/arm/boards/phytec-som-am335x/ram-timings.h
+++ b/arch/arm/boards/phytec-som-am335x/ram-timings.h
@@ -31,6 +31,7 @@ enum {
PHYCORE_MT41J512M8125IT_2x512MB,
PHYCORE_IM8G16D3FBBG15EI_1024MB,
PHYCORE_R2_MT41K256M16TW107IT_512MB,
+ PHYCORE_R2_MT41K128M16JT_256MB,
PHYCARD_NT5CB128M16BP_256MB,
};
@@ -212,6 +213,25 @@ struct am335x_sdram_timings physom_timings[] = {
.wr_slave_ratio0 = 0x72,
},
},
+
+ /* 256MB R2 */
+ [PHYCORE_R2_MT41K128M16JT_256MB] = {
+ .regs = {
+ .emif_read_latency = 0x7,
+ .emif_tim1 = 0x0AAAD4DB,
+ .emif_tim2 = 0x26437FDA,
+ .emif_tim3 = 0x501F83FF,
+ .sdram_config = 0x61C052B2,
+ .zq_config = 0x50074BE4,
+ .sdram_ref_ctrl = 0x00000C30,
+ },
+ .data = {
+ .rd_slave_ratio0 = 0x36,
+ .wr_dqs_slave_ratio0 = 0x38,
+ .fifo_we_slave_ratio0 = 0x99,
+ .wr_slave_ratio0 = 0x73,
+ },
+ },
};
#endif
diff --git a/images/Makefile.am33xx b/images/Makefile.am33xx
index eec6fc5..6c7e81a 100644
--- a/images/Makefile.am33xx
+++ b/images/Makefile.am33xx
@@ -47,6 +47,12 @@ FILE_barebox-am33xx-phytec-phycore-mlo-256mb.spi.img = start_am33xx_phytec_phyco
am33xx-mlo-$(CONFIG_MACH_PHYTEC_SOM_AM335X) += barebox-am33xx-phytec-phycore-mlo-256mb.img
am33xx-mlospi-$(CONFIG_MACH_PHYTEC_SOM_AM335X) += barebox-am33xx-phytec-phycore-mlo-256mb.spi.img
+pblx-$(CONFIG_MACH_PHYTEC_SOM_AM335X) += start_am33xx_phytec_phycore_r2_sram_256mb
+FILE_barebox-am33xx-phytec-phycore-r2-mlo-256mb.img = start_am33xx_phytec_phycore_r2_sram_256mb.pblx.mlo
+FILE_barebox-am33xx-phytec-phycore-r2-mlo-256mb.spi.img = start_am33xx_phytec_phycore_r2_sram_256mb.pblx.mlospi
+am33xx-mlo-$(CONFIG_MACH_PHYTEC_SOM_AM335X) += barebox-am33xx-phytec-phycore-r2-mlo-256mb.img
+am33xx-mlospi-$(CONFIG_MACH_PHYTEC_SOM_AM335X) += barebox-am33xx-phytec-phycore-r2-mlo-256mb.spi.img
+
pblx-$(CONFIG_MACH_PHYTEC_SOM_AM335X) += start_am33xx_phytec_phycore_sram_128mb
FILE_barebox-am33xx-phytec-phycore-mlo-128mb.img = start_am33xx_phytec_phycore_sram_128mb.pblx.mlo
FILE_barebox-am33xx-phytec-phycore-mlo-128mb.spi.img = start_am33xx_phytec_phycore_sram_128mb.pblx.mlospi
--
1.9.1
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