There are systems like the Calxeda Highbank, which need to do SMC
calls in order to access the secure L2C registers, which means they
want to replace the outer cache disable function with their own.
As the cache flush before entering the boot target is still needed
and to avoid exposing L2C internals to the architectures move the
flush before disable into the only current user.
Signed-off-by: Lucas Stach <l.stach@xxxxxxxxxxxxxx>
---
arch/arm/cpu/cache-l2x0.c | 2 --
arch/arm/cpu/cpu.c | 4 +++-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/cpu/cache-l2x0.c b/arch/arm/cpu/cache-l2x0.c
index 6bd540ea69b3..0aa2482321e8 100644
--- a/arch/arm/cpu/cache-l2x0.c
+++ b/arch/arm/cpu/cache-l2x0.c
@@ -124,8 +124,6 @@ static void l2x0_flush_all(void)
static void l2x0_disable(void)
{
- writel(0xff, l2x0_base + L2X0_CLEAN_INV_WAY);
- while (readl(l2x0_base + L2X0_CLEAN_INV_WAY));
writel(0, l2x0_base + L2X0_CTRL);
}
diff --git a/arch/arm/cpu/cpu.c b/arch/arm/cpu/cpu.c
index ff8f43d175ec..e8191ecde5a8 100644
--- a/arch/arm/cpu/cpu.c
+++ b/arch/arm/cpu/cpu.c
@@ -80,8 +80,10 @@ struct outer_cache_fns outer_cache;
void mmu_disable(void)
{
__mmu_cache_flush();
- if (outer_cache.disable)
+ if (outer_cache.disable) {
+ outer_cache.flush_all();
outer_cache.disable();
+ }
__mmu_cache_off();
}
--
2.6.0
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