On 10.10.2015 10:44, Robert Jarzmik wrote:
Sebastian Hesselbarth <sebastian.hesselbarth@xxxxxxxxx> writes:
Marvell NAND controller allows to enable an Auto Read Status feature
that will monitor NAND status during Erase and Program operations.
Okay, I seem to remember barebox nand core code does read it after erase and
write anyway by issuing a status read command. Could you tell me what this
brings I don't see ?
The Auto RS feature makes the controller poll NAND status and holds
the READY bit until it is sure the NAND has finished erase/pageprog
command.
I have timeout issues without it and I am pretty sure it just hides
some timing misconfiguration on my side. _But_ at this point I think
it is better than reworking timing setup now. I will have a deeper look
at timing configuration for sure but this involves in-depth PXA vs
Armada (vs Berlin) timing register comparison.
And the reason why I didn't do any timing rework is that DT
infrastructure for passing timing information, ONFI parsing, aso
is still very vague. I really need more time to think about the
best way to deal with it.
For example, ONFI timings give you a set of timings but they do
not specify tPROG, tERASE and friends. Those have to be parsed
from some other ONFI commands. I really want to do this step
by step and it has to be in-sync with Linux mtd... something
that would stall NAND support on Armada a little while.
Bottom-line: If the Auto RS feature doesn't break PXA, I'd
appreciate if it is enabled at least until I can confirm
proper timings are being read for the device I have.
Sebastian
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