When flushing the cache L1 has to be flushed before L2, not the
other way round.
Signed-off-by: Sascha Hauer <s.hauer@xxxxxxxxxxxxxx>
---
arch/arm/cpu/mmu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/cpu/mmu.c b/arch/arm/cpu/mmu.c
index 37bfa05..1bd6080 100644
--- a/arch/arm/cpu/mmu.c
+++ b/arch/arm/cpu/mmu.c
@@ -159,9 +159,9 @@ static u32 *find_pte(unsigned long adr)
static void dma_flush_range(unsigned long start, unsigned long end)
{
+ __dma_flush_range(start, end);
if (outer_cache.flush_range)
outer_cache.flush_range(start, end);
- __dma_flush_range(start, end);
}
static void dma_inv_range(unsigned long start, unsigned long end)
--
2.4.6
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