On 10.04.2015 09:23, Lucas Stach wrote:
Am Freitag, den 10.04.2015, 03:01 +0200 schrieb Sebastian Hesselbarth:
Commit a76c62f80d95860e6c5904ab5cb91667c43f61eb
("net: mvneta: convert to streaming DMA ops")
converted explicit ARM cache flushes to streaming DMA calls.
However, in mvneta_send() we are not interested in the sent data buffer
anymore. Also, in mvneta_recv() the device does not care about received
data buffer.
Remove unnecessary dma_sync_single_for_cpu() in mvneta_send() and
dma_sync_single_for_device() in mvneta_recv().
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@xxxxxxxxx>
NACK: see below.
---
Cc: barebox@xxxxxxxxxxxxxxxxxxx
Cc: Lucas Stach <dev@xxxxxxxxxx>
Cc: Ezequiel Garcia <ezequiel.garcia@xxxxxxxxxxxxxxxxxx>
Cc: Thomas Petazzoni <thomas.petazzoni@xxxxxxxxxxxxxxxxxx>
---
drivers/net/mvneta.c | 4 ----
1 file changed, 4 deletions(-)
diff --git a/drivers/net/mvneta.c b/drivers/net/mvneta.c
index 3be2ec531fb1..e1c7f15210e4 100644
--- a/drivers/net/mvneta.c
+++ b/drivers/net/mvneta.c
@@ -409,7 +409,6 @@ static int mvneta_send(struct eth_device *edev, void *data, int len)
* the Tx port status register (PTXS).
*/
ret = wait_on_timeout(TRANSFER_TIMEOUT, !mvneta_pending_tx(priv));
- dma_sync_single_for_cpu((unsigned long)data, len, DMA_TO_DEVICE);
This makes sure the CPU has a consistent view of memory. If something
got speculatively loaded into the cache you will write out invalid data
on the next send.
if (ret) {
dev_err(&edev->dev, "transmit timeout\n");
return ret;
@@ -468,9 +467,6 @@ static int mvneta_recv(struct eth_device *edev)
rxdesc->data_size - MVNETA_MH_SIZE);
ret = 0;
- dma_sync_single_for_device((unsigned long)rxdesc->buf_phys_addr,
- ALIGN(PKTSIZE, 8), DMA_FROM_DEVICE);
-
The buffer is reused for the next receive operation. This isn't syncing
the data to the device, but is actually a cache invalidate to make sure
there is no pending cache writeback that may corrupt your received data.
recv_err:
/* reset this and get next rx descriptor*/
rxdesc->data_size = 0;
The DMA API has a notion of buffer ownership. Accessing a buffer without
transferring the ownership to the appropriate entity (cpu or device) is
illegal. Using the DMA API in a non balanced manner is skipping the
ownership transfer.
Lucas,
I checked the Linux DMA-API documentation again, I guess this is what
you are referring to? The documents neither mention "owner" nor
"balance" in any way.
However, I do agree that balancing the calls makes sense as long as we
cannot guarantee that receive buffers are treated read-only and transmit
buffers write-only.
So, the NACK is correct, please drop this patch.
Sebastian
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