It is required for Rockchip SoCs where clock settings registers have
write-enable mask in high word.
Signed-off-by: Andrey Panov <rockford@xxxxxxxxx>
---
drivers/clk/clk-divider.c | 4 ++++
include/linux/clk.h | 2 ++
2 files changed, 6 insertions(+)
diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index 506a966..eb48334 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -197,6 +197,10 @@ static int clk_divider_set_rate(struct clk *clk, unsigned long rate,
val = readl(divider->reg);
val &= ~(div_mask(divider) << divider->shift);
val |= value << divider->shift;
+
+ if (clk->flags & CLK_DIVIDER_HIWORD_MASK)
+ val |= div_mask(divider) << (divider->shift + 16);
+
writel(val, divider->reg);
return 0;
diff --git a/include/linux/clk.h b/include/linux/clk.h
index 89cb44e..258bbe3 100644
--- a/include/linux/clk.h
+++ b/include/linux/clk.h
@@ -248,6 +248,8 @@ struct clk_divider {
int table_size;
};
+#define CLK_DIVIDER_HIWORD_MASK (1 << 3)
+
#define CLK_MUX_HIWORD_MASK (1 << 2)
extern struct clk_ops clk_divider_ops;
--
2.1.4
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