A part of the existing comments was incomplete or missleading. Adding the register name to mcr/mrc instructions helps finding the corresponding documentation in the manuals. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@xxxxxxxxxxxxxx> --- arch/arm/cpu/lowlevel.S | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/arch/arm/cpu/lowlevel.S b/arch/arm/cpu/lowlevel.S index e000cd8eae4c..de7afba2c317 100644 --- a/arch/arm/cpu/lowlevel.S +++ b/arch/arm/cpu/lowlevel.S @@ -5,7 +5,7 @@ .section ".text_bare_init_","ax" ENTRY(arm_cpu_lowlevel_init) mov r2, lr - /* set the cpu to SVC32 mode */ + /* set the cpu to SVC32 mode, mask irq and fiq */ mrs r12, cpsr bic r12, r12, #0x1f orr r12, r12, #0xd3 @@ -34,10 +34,12 @@ ENTRY(arm_cpu_lowlevel_init) mcr p15, 0, r12, c7, c5, 4 #endif - /* disable MMU stuff and caches */ - mrc p15, 0, r12, c1, c0, 0 - bic r12, r12 , #(CR_M | CR_C | CR_B) + /* disable MMU stuff and data/unified caches */ + mrc p15, 0, r12, c1, c0, 0 /* SCTLR */ + bic r12, r12, #(CR_M | CR_C | CR_B) bic r12, r12, #(CR_S | CR_R | CR_V) + + /* enable instruction cache */ orr r12, r12, #CR_I #if __LINUX_ARM_ARCH__ >= 6 @@ -51,7 +53,7 @@ ENTRY(arm_cpu_lowlevel_init) orr r12, r12, #CR_B #endif - mcr p15, 0, r12, c1, c0, 0 + mcr p15, 0, r12, c1, c0, 0 /* SCTLR */ mov pc, r2 ENDPROC(arm_cpu_lowlevel_init) -- 2.1.3 _______________________________________________ barebox mailing list barebox@xxxxxxxxxxxxxxxxxxx http://lists.infradead.org/mailman/listinfo/barebox
