The corresponding code doesn't use the lr register (neither explicitly nor implicitly by the bl instruction), so there is no gain in using r2 here. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@xxxxxxxxxxxxxx> --- arch/arm/cpu/lowlevel.S | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/cpu/lowlevel.S b/arch/arm/cpu/lowlevel.S index de7afba2c317..b76222d8f3c0 100644 --- a/arch/arm/cpu/lowlevel.S +++ b/arch/arm/cpu/lowlevel.S @@ -4,7 +4,6 @@ .section ".text_bare_init_","ax" ENTRY(arm_cpu_lowlevel_init) - mov r2, lr /* set the cpu to SVC32 mode, mask irq and fiq */ mrs r12, cpsr bic r12, r12, #0x1f @@ -55,5 +54,5 @@ ENTRY(arm_cpu_lowlevel_init) mcr p15, 0, r12, c1, c0, 0 /* SCTLR */ - mov pc, r2 + mov pc, lr ENDPROC(arm_cpu_lowlevel_init) -- 2.1.3 _______________________________________________ barebox mailing list barebox@xxxxxxxxxxxxxxxxxxx http://lists.infradead.org/mailman/listinfo/barebox
