>> if (mxs_nand_is_imx6(nand_info)) {
>> + val = readl(MXC_CCM_CCGR2);
>> + val &= ~MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK;
>> + writel(val, MXC_CCM_CCGR2);
>> +
>> clk_set_rate(nand_info->clk, 96000000);
>> +
>> + val = readl(MXC_CCM_CCGR2);
>> + val |= MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK;
>> + writel(val, MXC_CCM_CCGR2);
>> +
>> clk_enable(nand_info->clk);
>
> First of all please look at the kernel driver. It uses a clock of 22MHz
> normally and 100 or 80MHz for EDO mode, which seems to require setup of
> other registers. So it might be that there's something else that makes
> trouble here.
I have looked in kernel driver but didn’t found anything related to this issue.
This solution was ported from similar clock initialisation in u-boot.
> The clk API is for abstracting the clock providers from its consumers.
> It's unnecessary to directly fiddle with the clock registers in the nand
> driver. Instead of passing the enfc_podf to the nand controller
> arch/arm/mach-imx/clk-imx6.c should be changed to pass the gate to the
> controller and here. In the final enabling of all the gates in
> clk-imx6.c clear MXC_CCM_CCGR2[14..15] and enable the clock here after
> setting the rate.
so if I understood correctly
* I should both set enfc clock rate and enable it in clk-imx6.c while
clock is gated off. For this I should create gated clock like:
clks[enfc] = imx_clk_gate2("enfc", "enfc_pred", base + 0x70, 14);
for which I should implement the imx_clk_gate2() itself for operating on two-bits gate
clocks (I see such function in kernel clk code).
* Setting clock rate and enabling it in nand_mxs.c becomes unnecessary
and can be removed.
Am I right?
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