Use external phy clock so that the kernel configures GPR1 bit 21 correctly. Signed-off-by: Sascha Hauer <s.hauer@xxxxxxxxxxxxxx> --- arch/arm/dts/imx6q-guf-santaro.dts | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/dts/imx6q-guf-santaro.dts b/arch/arm/dts/imx6q-guf-santaro.dts index 7978d80..98fb78f 100644 --- a/arch/arm/dts/imx6q-guf-santaro.dts +++ b/arch/arm/dts/imx6q-guf-santaro.dts @@ -51,6 +51,12 @@ power-supply = <®_backlight>; status = "okay"; }; + + phyclk: phyclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; }; &fec { @@ -58,6 +64,9 @@ pinctrl-0 = <&pinctrl_enet>; phy-mode = "rmii"; status = "okay"; + clocks = <&clks IMX6QDL_CLK_ENET>, + <&clks IMX6QDL_CLK_ENET>, + <&phyclk>; }; &i2c1 { -- 2.1.1 _______________________________________________ barebox mailing list barebox@xxxxxxxxxxxxxxxxxxx http://lists.infradead.org/mailman/listinfo/barebox