This patch set adds support for reading SoC ID and revision from PCIe controllers found on Marvell MVEBU SoCs. Patch 1 adds PCI bus specific OF address translation required for reg property parsing of PCIe controller nodes. Patch 2 selects above PCI OF address translation for MVEBU SoCs. Patch 3 adds common code to find and parse PCIe controller nodes from MVEBU SoC DT and read out SoC ID and revision registers. The patches are based on barebox next with latest MVEBU patches for cleanup and PBL images applied. They have been tested on Marvell Kirkwood, Dove, and Armada 370. Sebastian Hesselbarth (3): drivers: of: import PCI bus specific translator ARM: mvebu: select PCI specific DT bus translator ARM: mvebu: determine SoC id and revision from PCIe nodes arch/arm/Kconfig | 1 + arch/arm/mach-mvebu/common.c | 64 ++++++++++++++++++++++++ arch/arm/mach-mvebu/include/mach/socid.h | 76 +++++++++++++++++++++++++++++ drivers/of/Kconfig | 3 ++ drivers/of/address.c | 83 ++++++++++++++++++++++++++++++++ 5 files changed, 227 insertions(+) create mode 100644 arch/arm/mach-mvebu/include/mach/socid.h --- Cc: barebox@xxxxxxxxxxxxxxxxxxx -- 2.0.0 _______________________________________________ barebox mailing list barebox@xxxxxxxxxxxxxxxxxxx http://lists.infradead.org/mailman/listinfo/barebox
