On Thu, Feb 27, 2014 at 03:51:26PM +0800, zzs wrote:
> >
> > The lr (r14) register has different instances, one for each mode. It
> > could be that once we switch to a different mode in arm_cpu_lowlevel_init
> > we see another instance of r14. So to me the patch looks correct, we
> > shouldn't rely on lr as return address but rather use another register
> > for storing the address.
> > The above only happens though when the CPU is not in SVC32 mode already.
> > What first stage loader are you using? Could you analyze in which mode
> > the CPU is when the loader jumps to barebox?
> >
> The first stage loader was written by myself longlong ago. So forgot the
> details. I just look the code closer, Found the flowwing line just
> before jumps to barebox.
>
> asm ("msr CPSR_c, %0" : :"i"(ARM_MODE_SYS|I_BIT|F_BIT));
>
> So it seems the cpu is in system mode when run barebox.
> Your explanation is right.
Ok, so arm_cpu_lowlevel_init currently only works if the CPU is in SVC32
mode already. Could you send a formal patch with the change you made
with a Signed-off-by line? Then I'll include it in barebox.
Sascha
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