Drop useless BUG(), we are too early for them to be of any use. Make sure we build the AVP code as ARMv4 even in PBL case. Signed-off-by: Lucas Stach <dev@xxxxxxxxxx> --- arch/arm/mach-tegra/Makefile | 1 + arch/arm/mach-tegra/tegra_avp_init.c | 4 ---- arch/arm/mach-tegra/tegra_maincomplex_init.c | 2 +- 3 files changed, 2 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index fd6a870..0fa8430 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile @@ -1,4 +1,5 @@ CFLAGS_tegra_avp_init.o := -mcpu=arm7tdmi -march=armv4t +CFLAGS_pbl-tegra_avp_init.o := -mcpu=arm7tdmi -march=armv4t lwl-y += tegra_avp_init.o lwl-y += tegra_maincomplex_init.o obj-y += tegra20.o diff --git a/arch/arm/mach-tegra/tegra_avp_init.c b/arch/arm/mach-tegra/tegra_avp_init.c index ba275ad..557af66 100644 --- a/arch/arm/mach-tegra/tegra_avp_init.c +++ b/arch/arm/mach-tegra/tegra_avp_init.c @@ -109,8 +109,6 @@ static void init_pllx(void) return; chiptype = tegra_get_chiptype(); - if (chiptype < 0) - BUG(); osc_freq = (readl(TEGRA_CLK_RESET_BASE + CRC_OSC_CTRL) & CRC_OSC_CTRL_OSC_FREQ_MASK) >> CRC_OSC_CTRL_OSC_FREQ_SHIFT; @@ -197,8 +195,6 @@ void barebox_arm_reset_vector(void) /* get the number of cores in the main CPU complex of the current SoC */ num_cores = tegra_get_num_cores(); - if (!num_cores) - BUG(); /* bring down main CPU complex (this may be a warm boot) */ enable_maincomplex_powerrail(); diff --git a/arch/arm/mach-tegra/tegra_maincomplex_init.c b/arch/arm/mach-tegra/tegra_maincomplex_init.c index dea9c91..343edd6 100644 --- a/arch/arm/mach-tegra/tegra_maincomplex_init.c +++ b/arch/arm/mach-tegra/tegra_maincomplex_init.c @@ -33,7 +33,7 @@ void tegra_maincomplex_entry(void) break; default: /* If we don't know the chiptype, better bail out */ - BUG(); + unreachable(); } /* -- 1.8.3.1 _______________________________________________ barebox mailing list barebox@xxxxxxxxxxxxxxxxxxx http://lists.infradead.org/mailman/listinfo/barebox
