Am Dienstag, den 04.06.2013, 16:53 +0200 schrieb Sascha Hauer: > Hi Jan, > > On Tue, May 28, 2013 at 01:51:40PM +0200, Jan Weitzel wrote: > > In omap4_enable_all_clocks we not only enable the mcbsp clocks, but also > > change the source from ABE_24M_FCLK to 24M_FCLK. Revert this and default > > to the reset state. > > Can you add a description why this is necessary? We had some trouble because the kernel takes the default clock sources from the registers. There seams to be no reason to change them in the boot loader. Is clean up a good enough answer? Could someone test it on pandaboard and ArchosG9? I didn't have (working) hardware here. Jan > > Sascha > > > > > Signed-off-by: Jan Weitzel <j.weitzel@xxxxxxxxx> > > --- > > arch/arm/mach-omap/omap4_clock.c | 6 +++--- > > 1 files changed, 3 insertions(+), 3 deletions(-) > > > > diff --git a/arch/arm/mach-omap/omap4_clock.c b/arch/arm/mach-omap/omap4_clock.c > > index 0621fd3..889d1f9 100644 > > --- a/arch/arm/mach-omap/omap4_clock.c > > +++ b/arch/arm/mach-omap/omap4_clock.c > > @@ -253,9 +253,9 @@ void omap4_enable_all_clocks(void) > > sr32(CM1_ABE_PDM_CLKCTRL, 0, 32, 0x2); > > sr32(CM1_ABE_DMIC_CLKCTRL, 0, 32, 0x2); > > sr32(CM1_ABE_MCASP_CLKCTRL, 0, 32, 0x2); > > - sr32(CM1_ABE_MCBSP1_CLKCTRL, 0, 32, 0x08000002); > > - sr32(CM1_ABE_MCBSP2_CLKCTRL, 0, 32, 0x08000002); > > - sr32(CM1_ABE_MCBSP3_CLKCTRL, 0, 32, 0x08000002); > > + sr32(CM1_ABE_MCBSP1_CLKCTRL, 0, 32, 0x2); > > + sr32(CM1_ABE_MCBSP2_CLKCTRL, 0, 32, 0x2); > > + sr32(CM1_ABE_MCBSP3_CLKCTRL, 0, 32, 0x2); > > sr32(CM1_ABE_SLIMBUS_CLKCTRL, 0, 32, 0xf02); > > sr32(CM1_ABE_TIMER5_CLKCTRL, 0, 32, 0x2); > > sr32(CM1_ABE_TIMER6_CLKCTRL, 0, 32, 0x2); > > -- > > 1.7.0.4 > > > > > > _______________________________________________ > > barebox mailing list > > barebox@xxxxxxxxxxxxxxxxxxx > > http://lists.infradead.org/mailman/listinfo/barebox > > > _______________________________________________ barebox mailing list barebox@xxxxxxxxxxxxxxxxxxx http://lists.infradead.org/mailman/listinfo/barebox
