From: Oleksij Rempel <bug-track@xxxxxxxxxxxxxxxxx>
Many cfi chips support 16 and 8 bit modes. Most important
difference is use of so called "Q15/A-1" pin. In 16bit mode this
pin is used for data IO. In 8bit mode, it is an address input
which add one more least significant bit (LSB). In this case
we should shift all adresses by one:
For example 0xaa << 1 = 0x154
---
drivers/nor/Kconfig | 8 ++++++++
drivers/nor/cfi_flash.h | 4 ++++
2 files changed, 12 insertions(+)
diff --git a/drivers/nor/Kconfig b/drivers/nor/Kconfig
index c8ce24f..b556b0c 100644
--- a/drivers/nor/Kconfig
+++ b/drivers/nor/Kconfig
@@ -50,6 +50,14 @@ config DRIVER_CFI_BANK_WIDTH_8
If you wish to support CFI devices on a physical bus which is
64 bits wide, say 'Y'.
+config DRIVER_CFI_BANK_SHIFT_1
+ bool "Shift addressspace of flash at one bit"
+ depends on DRIVER_CFI
+ default n
+ help
+ If you have flash with enabled LSB bit, then you
+ wont to enable this function.
+
config CFI_BUFFER_WRITE
bool "use cfi driver with buffer write"
depends on DRIVER_CFI || DRIVER_CFI
diff --git a/drivers/nor/cfi_flash.h b/drivers/nor/cfi_flash.h
index 8f818ba..6c7cac4 100644
--- a/drivers/nor/cfi_flash.h
+++ b/drivers/nor/cfi_flash.h
@@ -295,7 +295,11 @@ static inline u64 flash_read64(void *addr)
*/
static inline uchar *flash_make_addr (struct flash_info *info, flash_sect_t sect, uint offset)
{
+#ifdef CONFIG_DRIVER_CFI_BANK_SHIFT_1
+ return ((uchar *) (info->start[sect] + (offset * info->portwidth << 1)));
+#else
return ((uchar *) (info->start[sect] + (offset * info->portwidth)));
+#endif
}
uchar flash_read_uchar (struct flash_info *info, uint offset);
--
1.7.10.4
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