Since commit:
2ccd451 ARM i.MX28: change default watchdog reset method
the external reset via the reset pin is broken. That commit overwrites the
HW_CLKCTRL_RESET register with only WDOG_POR_DISABLE set, which results in
disabling the external reset.
This patch uses read-modify-write to set the WDOG_POR_DISABLE, leaving the
WDOG_POR_DISABLE untouched.
Cc: Steffen Trumtrar <s.trumtrar@xxxxxxxxxxxxxx>
Signed-off-by: Marc Kleine-Budde <mkl@xxxxxxxxxxxxxx>
---
changes since v1:
* use r-m-w to change HW_CLKCTRL_RESET register (thanks jbe)
arch/arm/mach-mxs/soc-imx28.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-mxs/soc-imx28.c b/arch/arm/mach-mxs/soc-imx28.c
index 8972a3d..ed931af 100644
--- a/arch/arm/mach-mxs/soc-imx28.c
+++ b/arch/arm/mach-mxs/soc-imx28.c
@@ -39,12 +39,16 @@ EXPORT_SYMBOL(reset_cpu);
static int imx28_init(void)
{
+ u32 reg;
+
/*
* The default setting for the WDT is to do a POR. If the SoC is only
* powered via battery, then a WDT reset powers the chip down instead
* of resetting it. Use a software reset only.
*/
- writel(HW_CLKCTRL_WDOG_POR_DISABLE, IMX_CCM_BASE + HW_CLKCTRL_RESET);
+ reg = readl(IMX_CCM_BASE + HW_CLKCTRL_RESET) |
+ HW_CLKCTRL_WDOG_POR_DISABLE;
+ writel(reg, IMX_CCM_BASE + HW_CLKCTRL_RESET);
return 0;
}
--
1.8.2.rc2
_______________________________________________
barebox mailing list
barebox@xxxxxxxxxxxxxxxxxxx
http://lists.infradead.org/mailman/listinfo/barebox
