> On Thu, 2013-03-14 at 14:46 +0100, Christoph Fritz wrote: > > On Thu, 2013-03-14 at 14:33 +0100, Sascha Hauer wrote: > > > > I wouldn't expect a bug in the code. This would have been discovered > > > already. > > > > Register CM_DSS_DSS_CLKCTRL (0x4a009120) reads 0x00070F02 and so the > > field [17:16] IDLEST reads 0x3 which means "Module is disabled and > > cannot be accessed". On linux, its 0x2 which means "functional". > > I already asked about this on the TI E2E Community forum > http://e2e.ti.com/support/omap/f/849/t/251717.aspx but without gaining > success. > > Overall, isn't it weird that DSS is offline (as indicated by IDLEST)? > > I suppose in ./arch/arm/mach-omap/omap4_clock.c this check: > > /* Check for DSS Clocks */ > while ((__raw_readl(0x4A009100) & 0xF00) != 0xE00) > ; > > should get extended to also check for correct IDLEST ...which would > currently end in an endless loop :) I revised commands/mem. All correct in the code, so problem is not here. About DSS: I cannot help you with this CPU, but here is one point from OMAP4430TRM: "The main access to all DSS registers is through the L3 interconnect. The access through the L4_PER interconnect is provided for back software compatibility." Maybe it help you. --- _______________________________________________ barebox mailing list barebox@xxxxxxxxxxxxxxxxxxx http://lists.infradead.org/mailman/listinfo/barebox
