On Fri, 2013-02-15 at 10:54 -0500, Xavier Douville wrote:
> On 02/14/2013 11:23, Jan Lübbe wrote:
> >
> > Which kernel & barebox are you using?
> >
>
> I am using kernel 3.2.0 and barebox 2012.11.0.
> Both with patches from Phytec (phyCORE-AM335x-PD12.1.1).
I'm not sure if that barebox is different to the latest one regarding
the GPMC NAND support...
Does it actually fail on your board without this patch?
I have here:
...
NAND device: Manufacturer ID: 0x2c, Chip ID: 0xda (Micron NAND 256MiB 3,3V 8-bit), page size: 2048, OOB size: 64
...
barebox:/ devinfo nand0
resources:
driver: none
bus: none
Parameters:
size = 268435456
erasesize = 131072
writesize = 2048
oobsize = 64
barebox:/ ubiattach /dev/nand0.root
UBI: attaching mtd0 to ubi0
UBI: physical eraseblock size: 131072 bytes (128 KiB)
UBI: logical eraseblock size: 126976 bytes
UBI: smallest flash I/O unit: 2048
UBI: VID header offset: 2048 (aligned 2048)
UBI: data offset: 4096
registering /dev/ubi0
registering root as /dev/ubi0.root
UBI: attached mtd0 to ubi0
UBI: MTD device name: "nand0.root"
UBI: MTD device size: 96 MiB
UBI: number of good PEBs: 768
UBI: number of bad PEBs: 0
UBI: max. allowed volumes: 128
UBI: wear-leveling threshold: 4096
UBI: number of internal volumes: 1
UBI: number of user volumes: 1
UBI: available PEBs: 33
UBI: total number of reserved PEBs: 735
UBI: number of PEBs reserved for bad PEB handling: 7
UBI: max/mean erase counter: 15/8
barebox:/
So it figures out the VID offset correctly from the writesize of 2048.
Regards,
Jan
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