...
> > diff --git a/arch/arm/boards/clep7212/lowlevel.c b/arch/arm/boards/clep7212/lowlevel.c
> > index b7d6d1d..fcf8285 100644
> > --- a/arch/arm/boards/clep7212/lowlevel.c
> > +++ b/arch/arm/boards/clep7212/lowlevel.c
> > @@ -14,9 +14,13 @@
> >
> > #include <mach/clps711x.h>
> >
> > +#if (CONFIG_CLPS711X_CPU_PLL_MULT < 20) || (CONFIG_CLPS711X_CPU_PLL_MULT > 50)
> > +# error "CPU PLL multiplier out of range"
> > +#endif
> > +
> > void __naked __bare_init barebox_arm_reset_vector(void)
> > {
> > arm_cpu_lowlevel_init();
> >
> > - clps711x_barebox_entry();
> > + clps711x_barebox_entry(CONFIG_CLPS711X_CPU_PLL_MULT);
> > }
> > diff --git a/arch/arm/mach-clps711x/Kconfig b/arch/arm/mach-clps711x/Kconfig
> > index f0adeda..d2873b4 100644
> > --- a/arch/arm/mach-clps711x/Kconfig
> > +++ b/arch/arm/mach-clps711x/Kconfig
> > @@ -10,6 +10,19 @@ config MACH_CLEP7212
> >
> > endchoice
> >
> > +menu "CLPS711X specific settings"
> > +
> > +config CLPS711X_CPU_PLL_MULT
> > + int "CPU PLL multiplier (20-50)"
> > + range 20 50
> > + default "40"
> > + help
> > + Define CPU PLL multiplier. PLL is calculated by formula:
> > + PLL Frequency = (PLL Multiplier / 2) * 3686400 Hz
> > + Default value is 40, for achieve 73 MHz.
> > +
> Nack NO KConfig for such sensitve value
>
> if it's soc detect it I do not have the datasheet but I'm sure you can
There are two possible clock sources: 3.6864 MHz crystal or 13 MHz
clock. Only source can be detected. When crystal is chosen, CPU starts at
low speed, so we should setup PLL register to increase speed.
Detect more is impossible.
Datasheet, if you interest, here www.cirrus.com/en/pubs/manual/ep73xx_um-f.pdf
But I am doubt if you find more.
Thanks!
---
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