On Mon, Feb 11, 2013 at 12:35:19PM +0100, Jean-Christophe PLAGNIOL-VILLARD wrote:
> On 09:30 Mon 11 Feb , Sascha Hauer wrote:
> > On Fri, Feb 08, 2013 at 10:28:44AM +0100, Jean-Christophe PLAGNIOL-VILLARD wrote:
> > > Cc: Nicolas Ferre <nicolas.ferre@xxxxxxxxx>
> > > Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@xxxxxxxxxxxx>
> > > ---
> > > arch/arm/boards/sama5d3xek/init.c | 31 +++++++++++++++++++++++++++++++
> > > 1 file changed, 31 insertions(+)
> > >
> >
> > Applied, thanks.
> >
> > > +static int ksz9021rn_phy_fixup(struct phy_device *phy)
> > > +{
> > > + int value;
> > > +
> > > +#define GMII_RCCPSR 260
> > > +#define GMII_RRDPSR 261
> > > +#define GMII_ERCR 11
> > > +#define GMII_ERDWR 12
> > > +
> > > + /* Set delay values */
> > > + value = GMII_RCCPSR | 0x8000;
> > > + phy_write(phy, GMII_ERCR, value);
> > > + value = 0xF2F4;
> > > + phy_write(phy, GMII_ERDWR, value);
> > > + value = GMII_RRDPSR | 0x8000;
> > > + phy_write(phy, GMII_ERCR, value);
> > > + value = 0x2222;
> > > + phy_write(phy, GMII_ERDWR, value);
> > > +
> > > + return 0;
> >
> > This delay line setup really needs some generic code. We have this on
> > i.MX6 aswell. Currently this means that each board needs to know the
> > phy it has, not a really good situation.
> the pb that it's hardware specific (PCB layout) so I do not see how we can fix
> this
The delay setup is PCB specific, but the register offsets/bits are phy
specific.
I think we need a callback in the phy drivers to configure the delay
lines, with values provided by the boards. I do not know the exact
background of this issue, but I see more and more often that boards bang
arbitrary values in the phy registers, and mostly this seems to be the
configuration of these delay lines.
Currently we have the same problem in the kernel, so it should be fixed
there aswell.
Sascha
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