Re: [PATCH 0/7] [RFC][PATCH] archosg9: add support for tablet

[vj <vicencb@xxxxxxxxx>]

Hi Sascha,
 I'm not an expert in ARM assembly, so, if this is correct:
    u32 r=0;
    asm ("mrc p15, 0, %0, c12, c0, 0" : "=r" (r));
    printf("MRC p15, 0, <Rd>, c12, c0, 0 returns 0x%08X\n", r);
    r=-1;
    asm ("mrc p15, 0, %0, c12, c0, 0" : "=r" (r));
    printf("MRC p15, 0, <Rd>, c12, c0, 0 returns 0x%08X\n", r);
the return value is:
    MRC p15, 0, <Rd>, c12, c0, 0 returns 0x00030000
    MRC p15, 0, <Rd>, c12, c0, 0 returns 0x00030000
Which is the base address of "ROM exception vectors" and the address of the "Reset" exception vector.
This is the value when omap_vector_init is disabled.

Hope this helps,
  Vicente.

On Wed, Sep 26, 2012 at 9:06 AM, Sascha Hauer <s.hauer@xxxxxxxxxxxxxx> wrote:

On Wed, Sep 26, 2012 at 12:59:47AM +0200, vj wrote:
> Hello,
> A this is my first contribution, so I'm basically requesting for comments.
>
> The attached patch adds support for Archos G9 tablet wich uses an OMAP4460 cpu.

Nice :)
I should have bought that one instead of a Acer.

>
> A question I have is what does omap_vector_init do?
> It breaks usb-booting.

I digged around a bit. The funny thing is that this was introduced with
OMAP4 support and is only done on OMAP4. U-Boot instead has the following:

> #if !defined(CONFIG_TEGRA2)
> /*
>  * Setup vector:
>  * (OMAP4 spl TEXT_BASE is not 32 byte aligned.
>  * Continue to use ROM code vector only in OMAP4 spl)
>  */
> #if !(defined(CONFIG_OMAP44XX) && defined(CONFIG_SPL_BUILD))
>       /* Set V=0 in CP15 SCTRL register - for VBAR to point to vector
>  * */
>       mrc     p15, 0, r0, c1, c0, 0   @ Read CP15 SCTRL Register
>       bic     r0, #CR_V               @ V = 0
>       mcr     p15, 0, r0, c1, c0, 0   @ Write CP15 SCTRL Register
>
>       /* Set vector address in CP15 VBAR register */
>       ldr     r0, =_start
>       mcr     p15, 0, r0, c12, c0, 0  @Set VBAR
> #endif
> #endif        /* !Tegra2 */

So in U-Boot it's done for every ARMv7 *except* OMAP4 (and Tegra)

ARM has this information about it:

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0434b/CIHHDAIH.html

> Purpose
>
>     Provides the exception base address for exceptions that are not
>     handled in monitor mode.
>
> Usage constraints
>
>     The VBAR is:
>
>         * only accessible in privileged modes
>         * only accessible in Secure state.

I think this is necessary to move the exception vector from ROM to our
own code. Does it work to read the VBAR register using the following
instruction:

        MRC p15, 0, <Rd>, c12, c0, 0 ; Read VBAR Register

Sascha

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