Hi > Sascha Hauer wrote: > > On Thu, Jun 21, 2012 at 11:16:18AM +0200, Juergen Beisert wrote: > > > These are examples how to provide the reset source. Not really tested on > > > the corresponding hardware yet. > > > > I did. On i.MX1 it does not work. The reset source register is not > > inside the watchdog module, but at 0x0021b800 (Reset source register, > > RSR) > > Hmm, in my old MC9328MX1 manual the watchdog register at 0x201008 (=Watchdog > Status Register) reports in bit 0 (=TOUT) if the watchdog timed out. > > But the RSR seems a more reliable source to read the status. > > > On i.MX27 it correctly detects a watchdog reset but not a power on > > reset. On i.MX27 it must be: > > > > # define WDOG_WRSR_EXT (1 << 3) > > # define WDOG_WRSR_PWR (1 << 4) > > Ups, sure. "not really tested"...I told you so ;) > Time for a #ifdef hell? On i.MX258 it's 0x53FDC000 + 0x0004 (WRSR) and bits 0 and 1, as follows: Bit: 1 (TOUT) Time-out. Indicates whether the reset is the result of a WDOG time-out. 0 Reset is not the result of a WDOG time-out. 1 Reset is the result of a WDOG time-out. Bit: 0 (SFTW) Software Reset. Indicates whether the reset is the result of a WDOG software reset by asserting SRS bit 0 Reset is not the result of a software reset. 1 Reset is the result of a software reset. Cheers Roberto _______________________________________________ barebox mailing list barebox@xxxxxxxxxxxxxxxxxxx http://lists.infradead.org/mailman/listinfo/barebox
