Hi Alexander, On Thu, May 24, 2012 at 12:44:29PM +0400, Alexander Shiyan wrote: > Currently, both SDHC clock source is PLL3. We can raise clock > for SDHC driver by change source from PLL3 to PLL2. > Below, is debug ouputs with old and new settings. As the kernel does the same change I assume this is fine. Applied. Sascha > > Detection (PLL3): > set clock: wanted: 400000 got: 375000 > Operation (PLL3): > set clock: wanted: 25000000 got: 18000000 > Operation SD4.0 (PLL3): > set clock: wanted: 52000000 got: 27000000 > > Detection (PLL2): > set clock: wanted: 400000 got: 399639 > Operation (PLL2): > set clock: wanted: 25000000 got: 23750000 > Operation SD4.0 (PLL2): > set clock: wanted: 52000000 got: 41562500 > > Signed-off-by: Alexander Shiyan <shc_work@xxxxxxx> > --- > arch/arm/mach-imx/imx51.c | 2 +- > 1 files changed, 1 insertions(+), 1 deletions(-) > > diff --git a/arch/arm/mach-imx/imx51.c b/arch/arm/mach-imx/imx51.c > index 25cc6da..53205a9 100644 > --- a/arch/arm/mach-imx/imx51.c > +++ b/arch/arm/mach-imx/imx51.c > @@ -269,7 +269,7 @@ void imx51_init_lowlevel(unsigned int cpufreq_mhz) > writel(0xffffffff, ccm + MX5_CCM_CCGR6); > > /* Use PLL 2 for UART's, get 66.5MHz from it */ > - writel(0xA5A2A020, ccm + MX5_CCM_CSCMR1); > + writel(0xA591A020, ccm + MX5_CCM_CSCMR1); > writel(0x00C30321, ccm + MX5_CCM_CSCDR1); > > /* make sure divider effective */ > -- > 1.7.3.4 > > > _______________________________________________ > barebox mailing list > barebox@xxxxxxxxxxxxxxxxxxx > http://lists.infradead.org/mailman/listinfo/barebox > -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | _______________________________________________ barebox mailing list barebox@xxxxxxxxxxxxxxxxxxx http://lists.infradead.org/mailman/listinfo/barebox
