Hello Sascha, Am Donnerstag, den 28.07.2011, 15:43 +0200 schrieb Sascha Hauer: > Hi Teresa, > > On Thu, Jul 28, 2011 at 03:14:13PM +0200, Teresa Gámez wrote: > > Update RAM timings with extended row cycle delay. > > > > Signed-off-by: Teresa Gámez <t.gamez@xxxxxxxxx> > > --- > > arch/arm/boards/pcm043/lowlevel.c | 2 +- > > 1 files changed, 1 insertions(+), 1 deletions(-) > > > > diff --git a/arch/arm/boards/pcm043/lowlevel.c b/arch/arm/boards/pcm043/lowlevel.c > > index eff96f9..bbe586b 100644 > > --- a/arch/arm/boards/pcm043/lowlevel.c > > +++ b/arch/arm/boards/pcm043/lowlevel.c > > @@ -146,7 +146,7 @@ void __bare_init __naked board_init_lowlevel(void) > > writel(0x00000304, ESDMISC); /* was 0x00000004 */ > > > > /* set timing paramters */ > > - writel(0x00255417, ESDCFG0); > > + writel(0x0025541F, ESDCFG0); > > Does this work on all boards or is this an update for newer sdrams? Sorry for my late answer. The timings are an update for newer sdrams. But the timings where successfully tested with older sdrams. I'll resend the patch with a new description. Teresa > > Sascha > _______________________________________________ barebox mailing list barebox@xxxxxxxxxxxxxxxxxxx http://lists.infradead.org/mailman/listinfo/barebox
