zoltan@xxxxxxxxxxxxx wrote: > On Tue, 22 Feb 2011, Juergen Beisert wrote: > > From: Juergen Beisert <juergen@xxxxxxxxxxxxxx> > > > > When booting from NAND, its important to know the correct page size. > > Isn't that info available as soon as SteppingStone sucked in the first 4K > into the internal SRAM? > > As far as I can follow the s3c2440 manual, bit 0 and the read-only bits 1 > to 3 of the NFCONF register convey that information and these bits are set > by sampling a few GPIO (NCON and GPG13-GPG15) pins at reset. Supposedly > these pins are pulled up/low during reset so that SteppingStone itself can > read the boot code from the NAND. > > What am I missing? I did a look at it. On my board this register states "0110" which means: - 8 bit NAND - 512 bytes per page (e.g. "normal" NAND) - 4 address cycles And this setting is all right, my flash is a K9F1208U0A. But Marek's board states "1110" which means: - 8 bit NAND - 2048 bytes per page (e.g. "advanced" NAND) - 5 address cycles And this setting is bad, because his K9F1G08U0B uses 4 address cycles only. Maybe it works because the NAND ignores the 5th address cycle? Others here around with a mini2440? Can you send me your NAND device type and the content of register 0x4e000000? jbe -- Pengutronix e.K. | Juergen Beisert | Linux Solutions for Science and Industry | Phone: +49-8766-939 228 | Vertretung Sued/Muenchen, Germany | Fax: +49-5121-206917-5555 | Amtsgericht Hildesheim, HRA 2686 | http://www.pengutronix.de/ | _______________________________________________ barebox mailing list barebox@xxxxxxxxxxxxxxxxxxx http://lists.infradead.org/mailman/listinfo/barebox
