This is a note to let you know that I've just added the patch titled
MIPS: Fix cpu_has_mips_r2_exec_hazard.
to the 4.0-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
mips-fix-cpu_has_mips_r2_exec_hazard.patch
and it can be found in the queue-4.0 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.
>From ralf@xxxxxxxxxxxxxx Fri May 8 16:39:53 2015
From: Ralf Baechle <ralf@xxxxxxxxxxxxxx>
Date: Wed, 25 Mar 2015 13:14:16 +0100
Subject: MIPS: Fix cpu_has_mips_r2_exec_hazard.
To: stable@xxxxxxxxxxxxxxx
Message-ID: <62b458a293df11aef74befe68888a9443862a1ad.1431087908.git.ralf@xxxxxxxxxxxxxx>
From: Ralf Baechle <ralf@xxxxxxxxxxxxxx>
Commit 9cdf30bd3bac697fc533988f44a117434a858f69 upstream.
Returns a non-zero value if the current processor implementation requires
an IHB instruction to deal with an instruction hazard as per MIPS R2
architecture specification, zero otherwise.
For a discussion, see http://patchwork.linux-mips.org/patch/9539/.
Signed-off-by: Ralf Baechle <ralf@xxxxxxxxxxxxxx>
Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx>
---
arch/mips/include/asm/cpu-features.h | 33 ++++++++++++++++++++++++++++++++-
1 file changed, 32 insertions(+), 1 deletion(-)
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -235,8 +235,39 @@
/* MIPSR2 and MIPSR6 have a lot of similarities */
#define cpu_has_mips_r2_r6 (cpu_has_mips_r2 | cpu_has_mips_r6)
+/*
+ * cpu_has_mips_r2_exec_hazard - return if IHB is required on current processor
+ *
+ * Returns non-zero value if the current processor implementation requires
+ * an IHB instruction to deal with an instruction hazard as per MIPS R2
+ * architecture specification, zero otherwise.
+ */
#ifndef cpu_has_mips_r2_exec_hazard
-#define cpu_has_mips_r2_exec_hazard (cpu_has_mips_r2 | cpu_has_mips_r6)
+#define cpu_has_mips_r2_exec_hazard \
+({ \
+ int __res; \
+ \
+ switch (current_cpu_type()) { \
+ case CPU_M14KC: \
+ case CPU_74K: \
+ case CPU_1074K: \
+ case CPU_PROAPTIV: \
+ case CPU_P5600: \
+ case CPU_M5150: \
+ case CPU_QEMU_GENERIC: \
+ case CPU_CAVIUM_OCTEON: \
+ case CPU_CAVIUM_OCTEON_PLUS: \
+ case CPU_CAVIUM_OCTEON2: \
+ case CPU_CAVIUM_OCTEON3: \
+ __res = 0; \
+ break; \
+ \
+ default: \
+ __res = 1; \
+ } \
+ \
+ __res; \
+})
#endif
/*
Patches currently in stable-queue which might be from ralf@xxxxxxxxxxxxxx are
queue-4.0/mips-octeon-remove-udelay-causing-huge-irq-latency.patch
queue-4.0/mips-makefile-fix-mips-ase-detection-code.patch
queue-4.0/mips-r4kcache-use-correct-base-register-for-mips-r6-cache-flushes.patch
queue-4.0/mips-fix-cpu_has_mips_r2_exec_hazard.patch
queue-4.0/mips-ralink-fix-bad-config-symbol-in-pci-makefile.patch
queue-4.0/revert-mips-remove-race-window-in-page-fault-handling.patch
queue-4.0/mips-fix-race-condition-in-lazy-cache-flushing.patch
queue-4.0/mips-bcm63xx-move-bcm63xx_gpio_init-to-bcm63xx_register_devices.patch
queue-4.0/mips-octeon-delete-override-of-cpu_has_mips_r2_exec_hazard.patch
queue-4.0/mips-asm-spinlock-fix-addiu-instruction-for-r10000_llsc_war-case.patch
queue-4.0/mips-kconfig-disable-smp-cps-for-64-bit.patch
queue-4.0/mips-bcm47xx-fix-detecting-microsoft-mn-700-asus-wl500g.patch
queue-4.0/mips-octeon-use-correct-csr-to-soft-reset.patch
queue-4.0/revert-mips-avoid-pipeline-stalls-on-some-mips32r2-cores.patch
queue-4.0/mips-octeon-dma-octeon-fix-ohci-usb-config-check.patch
queue-4.0/mips-octeon-fix-pci-interrupt-mapping-for-d-link-dsr-1000n.patch
queue-4.0/mips-kconfig-fix-typo-for-the-r2-to-r6-emulator-kernel-parameter.patch
queue-4.0/ssb-fix-kconfig-dependencies.patch
queue-4.0/mips-kernel-entry.s-set-correct-isa-level-for-mips_ihb.patch
queue-4.0/mips-netlogic-fix-for-sata-phy-init.patch
queue-4.0/mips-ralink-add-missing-symbol-for-ralink_ill_acc.patch
queue-4.0/mips-asm-elf-set-o32-default-fpu-flags.patch
queue-4.0/mips-smp-cps-cpu_set-fpu-mask-if-fpu-present.patch
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