On Tue, Nov 26, 2024 at 06:13:01PM +0000, Matthew Auld wrote:
> On some HW we want to avoid the host caching PTEs, since access from GPU
> side can be incoherent. However here the special migrate object is
> mapping PTEs which are written from the host and potentially cached. Use
> XE_BO_FLAG_PAGETABLE to ensure that non-cached mapping is used, on
> platforms where this matters.
>
> Fixes: 7a060d786cc1 ("drm/xe/mtl: Map PPGTT as CPU:WC")
> Signed-off-by: Matthew Auld <matthew.auld@xxxxxxxxx>
> Cc: Matthew Brost <matthew.brost@xxxxxxxxx>
Reviewed-by: Matthew Brost <matthew.brost@xxxxxxxxx>
> Cc: Nirmoy Das <nirmoy.das@xxxxxxxxx>
> Cc: <stable@xxxxxxxxxxxxxxx> # v6.8+
> ---
> drivers/gpu/drm/xe/xe_migrate.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_migrate.c b/drivers/gpu/drm/xe/xe_migrate.c
> index 48e205a40fd2..1b97d90aadda 100644
> --- a/drivers/gpu/drm/xe/xe_migrate.c
> +++ b/drivers/gpu/drm/xe/xe_migrate.c
> @@ -209,7 +209,8 @@ static int xe_migrate_prepare_vm(struct xe_tile *tile, struct xe_migrate *m,
> num_entries * XE_PAGE_SIZE,
> ttm_bo_type_kernel,
> XE_BO_FLAG_VRAM_IF_DGFX(tile) |
> - XE_BO_FLAG_PINNED);
> + XE_BO_FLAG_PINNED |
> + XE_BO_FLAG_PAGETABLE);
> if (IS_ERR(bo))
> return PTR_ERR(bo);
>
> --
> 2.47.0
>
