On 11/26/2024 7:13 PM, Matthew Auld wrote:
> XE_CACHE_WB must be converted into the per-platform pat index for that
> particular caching mode, otherwise we are just encoding whatever happens
> to be the value of that enum.
>
> Fixes: e8babb280b5e ("drm/xe: Convert multiple bind ops into single job")
> Signed-off-by: Matthew Auld <matthew.auld@xxxxxxxxx>
> Cc: Matthew Brost <matthew.brost@xxxxxxxxx>
> Cc: Nirmoy Das <nirmoy.das@xxxxxxxxx>
> Cc: <stable@xxxxxxxxxxxxxxx> # v6.12+
Reviewed-by: Nirmoy Das <nirmoy.das@xxxxxxxxx>
> ---
> drivers/gpu/drm/xe/xe_migrate.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_migrate.c b/drivers/gpu/drm/xe/xe_migrate.c
> index cfd31ae49cc1..48e205a40fd2 100644
> --- a/drivers/gpu/drm/xe/xe_migrate.c
> +++ b/drivers/gpu/drm/xe/xe_migrate.c
> @@ -1350,6 +1350,7 @@ __xe_migrate_update_pgtables(struct xe_migrate *m,
>
> /* For sysmem PTE's, need to map them in our hole.. */
> if (!IS_DGFX(xe)) {
> + u16 pat_index = xe->pat.idx[XE_CACHE_WB];
> u32 ptes, ofs;
>
> ppgtt_ofs = NUM_KERNEL_PDE - 1;
> @@ -1409,7 +1410,7 @@ __xe_migrate_update_pgtables(struct xe_migrate *m,
> pt_bo->update_index = current_update;
>
> addr = vm->pt_ops->pte_encode_bo(pt_bo, 0,
> - XE_CACHE_WB, 0);
> + pat_index, 0);
> bb->cs[bb->len++] = lower_32_bits(addr);
> bb->cs[bb->len++] = upper_32_bits(addr);
> }
